From e3b30dbd83f5b3497c2b0aeb20e75d80b91a0a38 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 1 Nov 2019 17:17:57 -0700 Subject: [PATCH 001/153] [FireChip] Use clock in BridgeBinders --- generators/firechip/src/main/scala/BridgeBinders.scala | 10 +++++----- generators/firechip/src/main/scala/TargetMixins.scala | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 95133561d7..a14102128d 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -32,19 +32,19 @@ class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryD }) class WithSerialBridge extends RegisterBridgeBinder({ - case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p)) + case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial)(target.p)) }) class WithNICBridge extends RegisterBridgeBinder({ - case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) + case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.clock, target.net)(target.p)) }) class WithUARTBridge extends RegisterBridgeBinder({ - case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) + case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(target.clock, u)(target.p)) }) class WithBlockDeviceBridge extends RegisterBridgeBinder({ - case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p)) + case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.clock ,target.bdev, target.reset.toBool)(target.p)) }) class WithFASEDBridge extends RegisterBridgeBinder({ @@ -55,7 +55,7 @@ class WithFASEDBridge extends RegisterBridgeBinder({ val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - FASEDBridge(axi4Bundle, t.reset.toBool, + FASEDBridge(t.clock, axi4Bundle, t.reset.toBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index c3982d956e..b96a660636 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -41,6 +41,7 @@ trait HasTraceIOImp extends LazyModuleImp { (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) => port := DeclockedTracedInstruction.fromVec(tileTrace) }) + traceIO.clock := clock // Enabled to test TracerV trace capture if (p(PrintTracePort)) { From 12485b8e5cabe8c564bf7f005bd94efc1ee1a4d3 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 20 Nov 2019 13:31:11 -0800 Subject: [PATCH 002/153] [firesim] Update TraceGen BridgeBinder --- generators/firechip/src/main/scala/BridgeBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index a14102128d..a6e6791ad2 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -67,7 +67,7 @@ class WithTracerVBridge extends RegisterBridgeBinder({ class WithTraceGenBridge extends RegisterBridgeBinder({ case target: HasTraceGenTilesModuleImp => - Seq(GroundTestBridge(target.success)(target.p)) + Seq(GroundTestBridge(target.clock, target.success)(target.p)) }) // Shorthand to register all of the provided bridges above From bcddd6e0f66c26f0fed18bb7f80b89384c5bca1f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 22 Nov 2019 16:29:55 -0800 Subject: [PATCH 003/153] [Firechip] Add support for Tile <-> Uncore rational division --- .../example/src/main/scala/ConfigMixins.scala | 1 + .../src/main/scala/TargetConfigs.scala | 18 ++++++++++++++++-- .../firechip/src/main/scala/TargetMixins.scala | 13 +++++++++++++ .../firechip/src/main/scala/Targets.scala | 2 ++ .../src/test/scala/ScalaTestSuite.scala | 3 +++ 5 files changed, 35 insertions(+), 2 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 7d7e74af03..dc9eed3623 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -182,3 +182,4 @@ class WithInitZeroTop extends Config((site, here, up) => { Module(LazyModule(new TopWithInitZero()(p)).module) }) // DOC include end: WithInitZero + diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 37df379965..f7b70322e4 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -11,7 +11,8 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.DebugModuleParams -import boom.common.BoomTilesKey +import freechips.rocketchip.diplomacy.{RationalCrossing} +import boom.common.{BoomCrossingKey, BoomTilesKey} import testchipip.{BlockDeviceKey, BlockDeviceConfig} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} @@ -19,7 +20,7 @@ import tracegen.TraceGenKey import icenet._ import firesim.bridges._ -import firesim.util.{WithNumNodes} +import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters} import firesim.configs._ class WithBootROM extends Config((site, here, up) => { @@ -320,3 +321,16 @@ class FireSimTraceGenL2Config extends Config( outerLatencyCycles = 50) ++ new WithTraceGenBridge ++ new FireSimRocketChipConfig) + + +class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => { + case FireSimClockKey => FireSimClockParameters(Seq(multiplier -> divisor)) + case RocketCrossingKey => up(RocketCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } + case BoomCrossingKey => up(BoomCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } +}) + +class HalfRateUncore extends WithRationalTiles(2,1) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index b96a660636..6320038a0d 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.tile.RocketTile import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} +import firesim.util.{HasAdditionalClocks, FireSimClockKey} import midas.targetutils.MemModelAnnotation @@ -73,3 +74,15 @@ trait CanHaveMultiCycleRegfileImp { } } +trait HasFireSimClockingImp extends HasAdditionalClocks { + val outer: HasTiles + val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { + case Some((numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) + case None => (clocks(0), reset) + } + + outer.tiles.foreach({ case tile => + tile.module.clock := tileClock + tile.module.reset := tileReset + }) +} diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 4c79019535..3a73b0d957 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -60,6 +60,7 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l) with HasPeripheryIceNICModuleImpValidOnly with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with HasFireSimClockingImp with CanHaveMultiCycleRegfileImp class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) @@ -84,6 +85,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with HasFireSimClockingImp with CanHaveMultiCycleRegfileImp class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index f4f55cd9a6..74af7fcb9b 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -139,6 +139,9 @@ class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_Fir class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams") class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams") +// Multiclock tests +class RocketMulticlockF1Tests extends FireSimTestSuite("FireSimNoNIC", "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config") + abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs From 38834a99e143f2281df0f52a677b28b167be293a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 9 Jan 2020 16:51:27 -0800 Subject: [PATCH 004/153] [firesim] Update the multiclock test --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 74af7fcb9b..a2f39523d9 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -140,7 +140,10 @@ class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRoc class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams") // Multiclock tests -class RocketMulticlockF1Tests extends FireSimTestSuite("FireSimNoNIC", "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config") +class RocketMulticlockF1Tests extends FireSimTestSuite( + "FireSimNoNIC", + "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", + "WithSynthAsserts_BaseF1Config") abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { From 524299bd39e1ecedccb62abdfbfc9ed41f15b1d4 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 9 Jan 2020 16:52:02 -0800 Subject: [PATCH 005/153] [firechip] Commit some Eagle X-related mock configs --- .../firechip/src/main/scala/TargetConfigs.scala | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index f7b70322e4..d83506263b 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -334,3 +334,16 @@ class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, her }) class HalfRateUncore extends WithRationalTiles(2,1) + +// Eagle X Mock Configs +class EagleMockConfig(numCores: Int) extends Config( + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks = 16, capacityKB = 8192) ++ + new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator + new WithNBigCores(numCores) ++ + new FireSimRocketChipConfig) + +class EX20C extends EagleMockConfig(20) +class EX16C extends EagleMockConfig(16) +class EX12C extends EagleMockConfig(12) +class EX8C extends EagleMockConfig(8) From 3fbc074b0191382c900becb7a66c76c9d7524b4f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 17 Jan 2020 17:56:37 -0800 Subject: [PATCH 006/153] [firechip] Instantiate multiple TracerV bridges --- .../src/main/scala/BridgeBinders.scala | 4 +-- .../src/main/scala/TargetMixins.scala | 35 +++++++++---------- .../src/test/scala/ScalaTestSuite.scala | 15 ++++---- 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index a6e6791ad2..6406d6c60a 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -61,9 +61,7 @@ class WithFASEDBridge extends RegisterBridgeBinder({ }).toSeq }) -class WithTracerVBridge extends RegisterBridgeBinder({ - case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p) -}) +class WithTracerVBridge extends Config((_,_,_) => { case InstantiateTracerVBridges => true }) class WithTraceGenBridge extends RegisterBridgeBinder({ case target: HasTraceGenTilesModuleImp => diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 6320038a0d..50d51269ff 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.tile.RocketTile import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction -import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} +import firesim.bridges.{TracerVBridge} import firesim.util.{HasAdditionalClocks, FireSimClockKey} import midas.targetutils.MemModelAnnotation @@ -22,34 +22,33 @@ import boom.common.BoomTile /* Wires out tile trace ports to the top; and wraps them in a Bundle that the * TracerV bridge can match on. */ -object PrintTracePort extends Field[Boolean](false) +case object PrintTracePort extends Field[Boolean](false) +case object InstantiateTracerVBridges extends Field[Boolean](false) trait HasTraceIO { this: HasTiles => val module: HasTraceIOImp // Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp - val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]] - val tileTraceNodes = tiles.map(tile => tile.traceNode) - tileTraceNodes foreach { traceNexus := _ } + val tileTraceNodes = tiles.map({ tile => + val node = BundleBridgeSink[Vec[TracedInstruction]] + node := tile.traceNode + node + }) } trait HasTraceIOImp extends LazyModuleImp { val outer: HasTraceIO - - val traceIO = IO(Output(new TraceOutputTop( - DeclockedTracedInstruction.fromNode(outer.traceNexus.in)))) - (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) => - port := DeclockedTracedInstruction.fromVec(tileTrace) + outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) => + if (p(InstantiateTracerVBridges)) { + val b = TracerVBridge(node.bundle) + if (p(PrintTracePort)) { + val traceprint = WireDefault(0.U(512.W)) + traceprint := b.io.traces.asUInt + printf(s"TRACEPORT ${idx}: %x\n", traceprint) + } + } }) - traceIO.clock := clock - - // Enabled to test TracerV trace capture - if (p(PrintTracePort)) { - val traceprint = Wire(UInt(512.W)) - traceprint := Cat(traceIO.traces.map(_.asUInt)) - printf("TRACEPORT: %x\n", traceprint) - } } trait CanHaveMultiCycleRegfileImp { diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index a2f39523d9..7f505ab1bb 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -106,14 +106,17 @@ abstract class FireSimTestSuite( def diffTracelog(verilatedLog: String) { behavior of "captured instruction trace" it should s"match the chisel printf in ${verilatedLog}" in { - def getLines(file: File, dropLines: Int = 0): Seq[String] = { + def getLines(file: File, dropLines: Int = 0, prefixFilter: String = ""): Seq[String] = { val lines = Source.fromFile(file).getLines.toList - lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) + lines.filter(_.startsWith(prefixFilter)) + .drop(dropLines) + .map(_.stripPrefix(prefixFilter)) } val resetLength = 51 - val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) - assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, "Outputs differ in length") + val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}"), prefixFilter = "TRACEPORT 0: ") + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), dropLines = resetLength) + assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, + s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}") assert(verilatedOutput.nonEmpty) for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { assert(vPrint == sPrint) @@ -125,7 +128,7 @@ abstract class FireSimTestSuite( mkdirs elaborate generateTestSuiteMakefrags - runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0""")) + runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) runSuite("verilator")(FastBlockdevTests) From 924f4403850df60edc533d83140225e161c248bf Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 20 Jan 2020 12:00:23 -0800 Subject: [PATCH 007/153] [Firechip] Include reset in tracerv tokens --- .../src/main/scala/TargetMixins.scala | 9 ++++++--- .../src/test/scala/ScalaTestSuite.scala | 19 ++++++++++--------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 50d51269ff..d7714527ae 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -42,10 +42,13 @@ trait HasTraceIOImp extends LazyModuleImp { outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) => if (p(InstantiateTracerVBridges)) { val b = TracerVBridge(node.bundle) + // Used for verifying the TracerV bridge if (p(PrintTracePort)) { - val traceprint = WireDefault(0.U(512.W)) - traceprint := b.io.traces.asUInt - printf(s"TRACEPORT ${idx}: %x\n", traceprint) + withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) { + val traceprint = WireDefault(0.U(512.W)) + traceprint := b.io.traces.asUInt + printf(s"TRACEPORT ${idx}: %x\n", traceprint) + } } } }) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 7f505ab1bb..9a8da363bd 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -106,15 +106,16 @@ abstract class FireSimTestSuite( def diffTracelog(verilatedLog: String) { behavior of "captured instruction trace" it should s"match the chisel printf in ${verilatedLog}" in { - def getLines(file: File, dropLines: Int = 0, prefixFilter: String = ""): Seq[String] = { - val lines = Source.fromFile(file).getLines.toList - lines.filter(_.startsWith(prefixFilter)) - .drop(dropLines) - .map(_.stripPrefix(prefixFilter)) - } - val resetLength = 51 - val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}"), prefixFilter = "TRACEPORT 0: ") - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), dropLines = resetLength) + def getLines(file: File): Seq[String] = Source.fromFile(file).getLines.toList + + val printfPrefix = "TRACEPORT 0: " + val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")).collect({ + case line if line.startsWith(printfPrefix) => line.stripPrefix(printfPrefix) }) + + // Last bit indicates the core was under reset; reject those tokens + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).filter(line => + (line.last.toInt & 1) == 0) + assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}") assert(verilatedOutput.nonEmpty) From b47e692b4b06905494368c509495921ab416e191 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 20 Jan 2020 12:55:47 -0800 Subject: [PATCH 008/153] [TracerV] Drop the first token in comparison tests --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 9a8da363bd..14146ba55f 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -113,7 +113,8 @@ abstract class FireSimTestSuite( case line if line.startsWith(printfPrefix) => line.stripPrefix(printfPrefix) }) // Last bit indicates the core was under reset; reject those tokens - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).filter(line => + // Tail to drop the first token which is initialized in the channel + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).tail.filter(line => (line.last.toInt & 1) == 0) assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, From e45c83f810105e8596cc93cd19adef51cfa25e2d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 21 Jan 2020 13:35:29 -0800 Subject: [PATCH 009/153] [Firechip] Make reverse instruction order in trace printf --- generators/firechip/src/main/scala/TargetConfigs.scala | 5 +++++ generators/firechip/src/main/scala/TargetMixins.scala | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d83506263b..a3f637d0c0 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -76,6 +76,10 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => { )) }) +class WithBoomEnableTrace extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) +}) + // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false) @@ -170,6 +174,7 @@ class FireSimBoomConfig extends Config( new WithUARTKey ++ new WithNICKey ++ new WithBlockDevice ++ + new WithBoomEnableTrace ++ new WithBoomL2TLBs(1024) ++ new WithoutClockGating ++ new WithDefaultMemModel ++ diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index d7714527ae..557612338d 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -46,7 +46,8 @@ trait HasTraceIOImp extends LazyModuleImp { if (p(PrintTracePort)) { withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) { val traceprint = WireDefault(0.U(512.W)) - traceprint := b.io.traces.asUInt + // The reverse is here to match the behavior the Cat used in the bridge + traceprint := b.io.traces.reverse.asUInt printf(s"TRACEPORT ${idx}: %x\n", traceprint) } } From 43008adc8e08f596a6a568f6ab601bef35f4e8eb Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 21 Jan 2020 14:28:54 -0800 Subject: [PATCH 010/153] WARNING: Point at a fork of boom @ davidbiancolin --- .gitmodules | 2 +- generators/boom | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 282dc73109..0240e78c79 100644 --- a/.gitmodules +++ b/.gitmodules @@ -18,7 +18,7 @@ url = https://github.com/ucb-bar/riscv-torture.git [submodule "generators/boom"] path = generators/boom - url = https://github.com/riscv-boom/riscv-boom.git + url = https://github.com/davidbiancolin/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks url = https://github.com/sifive/sifive-blocks.git diff --git a/generators/boom b/generators/boom index 2a0ea2e7ac..84c81dcc54 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 2a0ea2e7acfd4605eed513e15062848e4e5be309 +Subproject commit 84c81dcc54e87598c6635f08787ad7f133fdd45e From f3d1bb8219a41d4d347a4680d2b07ea1c3d99734 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 27 Feb 2020 16:34:39 -0800 Subject: [PATCH 011/153] WIP: Add the ability to generate a hammer-sim config for gate-level sims Still need to work on the asm-test/benchmark integration --- sims/vcs/Makefile | 5 +- vcs.mk | 35 ++++++++++++++ vlsi/Makefile | 114 +++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 149 insertions(+), 5 deletions(-) create mode 100644 vcs.mk diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 86c28f23cd..e8a30b0c5e 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,10 +25,7 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - -WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +include $(base_dir)/vcs.mk .PHONY: default debug default: $(sim) diff --git a/vcs.mk b/vcs.mk new file mode 100644 index 0000000000..c0450da5c3 --- /dev/null +++ b/vcs.mk @@ -0,0 +1,35 @@ +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off + +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd + +VCS_CC_OPTS = \ + -CC "-I$(VCS_HOME)/include" \ + -CC "-I$(RISCV)/include" \ + -CC "-std=c++11" + +VCS_NONCC_OPTS = \ + $(RISCV)/lib/libfesvr.a \ + +lint=all,noVCDE,noONGS,noUI \ + -error=PCWM-L \ + -timescale=1ns/10ps \ + -quiet \ + -q \ + +rad \ + +v2k \ + +vcs+lic+wait \ + +vc+list \ + -f $(sim_common_files) \ + -sverilog \ + +incdir+$(build_dir) \ + $(sim_vsrcs) \ + +libext+.v + +VCS_DEFINE_OPTS = \ + +define+CLOCK_PERIOD=1.0 \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN diff --git a/vlsi/Makefile b/vlsi/Makefile index a41368c5c7..800411bd7e 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -87,11 +87,123 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator cd $(vlsi_dir) && cp output.json $@ +######################################################################################### +# simulation input configuration +######################################################################################### +include $(base_dir)/vcs.mk +SIM_CONF = $(OBJ_DIR)/sim-inputs.yml +SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml + +$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " level: 'gl'" >> $@ + echo " input_files:" >> $@ + for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo " timescale: '1ns/10ps'" >> $@ + echo " options: [" >> $@ + echo " '$(RISCV)/lib/libfesvr.a'," >> $@ + echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ + echo " '-error=PCWM-L'," >> $@ + echo " '-quiet'," >> $@ + echo " '-q'," >> $@ + echo " '+rad'," >> $@ + echo " '+v2k'," >> $@ + echo " '+vcs+lic+wait'," >> $@ + echo " '+vc+list'," >> $@ + echo " '-f $(sim_common_files)'," >> $@ + echo " '-sverilog']" >> $@ + echo " options_meta: 'append'" >> $@ + echo " defines: [" >> $@ + echo " 'CLOCK_PERIOD=1.0'," >> $@ + echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ + echo " 'STOP_COND=!$(TB).reset'," >> $@ + echo " 'RANDOMIZE_MEM_INIT'," >> $@ + echo " 'RANDOMIZE_REG_INIT'," >> $@ + echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ + echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " compiler_opts: [" >> $@ + echo " '-I$(RISCV)/include'," >> $@ + echo " '-std=c++11']" >> $@ + echo " compiler_opts_meta: 'append'" >> $@ + echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ + echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ + echo " execution_flags: [" >> $@ + echo " '+max-cycles=$(timeout_cycles)'," >> $@ + for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + echo ' "'$$x'",' >> $@; \ + done + echo " ]" >> $@ + echo " execution_flags_meta: 'append'" >> $@ + echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ + +$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " level: 'gl'" >> $@ + echo " input_files:" >> $@ + for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo " timescale: '1ns/10ps'" >> $@ + echo " options: [" >> $@ + echo " '$(RISCV)/lib/libfesvr.a'," >> $@ + echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ + echo " '-error=PCWM-L'," >> $@ + echo " '-quiet'," >> $@ + echo " '-q'," >> $@ + echo " '+rad'," >> $@ + echo " '+v2k'," >> $@ + echo " '+vcs+lic+wait'," >> $@ + echo " '+vc+list'," >> $@ + echo " '-f $(sim_common_files)'," >> $@ + echo " '-sverilog'," >> $@ + echo " '-debug_pp']" >> $@ + echo " options_meta: 'append'" >> $@ + echo " defines: [" >> $@ + echo " 'DEBUG'," >> $@ + echo " 'CLOCK_PERIOD=1.0'," >> $@ + echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ + echo " 'STOP_COND=!$(TB).reset'," >> $@ + echo " 'RANDOMIZE_MEM_INIT'," >> $@ + echo " 'RANDOMIZE_REG_INIT'," >> $@ + echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ + echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " compiler_opts: [" >> $@ + echo " '-I$(RISCV)/include'," >> $@ + echo " '-std=c++11']" >> $@ + echo " compiler_opts_meta: 'append'" >> $@ + echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ + echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ + echo " execution_flags: [" >> $@ + echo " '+max-cycles=$(timeout_cycles)'," >> $@ + for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + echo ' "'$$x'",' >> $@; \ + done + echo " '+vcdplusfile=$(OBJ_DIR)/sim-tool-output.vpd']" >> $@ + echo " execution_flags_meta: 'append'" >> $@ + echo " tb_dut: 'testHarness.top'" >> $@ + echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ + + #echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add']" >> $@ + +$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "power.inputs:" > $@ + +sim_conf_temp: $(SIM_CONF) $(SIM_DEBUG_CONF) + ######################################################################################### # synthesis input configuration ######################################################################################### SYN_CONF = $(OBJ_DIR)/inputs.yml -GENERATED_CONFS = $(SYN_CONF) +GENERATED_CONFS = $(SYN_CONF) $(SIM_CONF) ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif From 86a5c47ef94505b18edc1fe8899cb5c7baa2afba Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 2 Mar 2020 11:10:18 -0800 Subject: [PATCH 012/153] Bump Hammer --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 2f37cd3121..2d3890bfca 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 2f37cd3121d9a9e775efbe4554d9b74c30d01f61 +Subproject commit 2d3890bfca2ef8a8e8c74ed447bddbb30789fd5c From 958332e1bf1bfc2f931605f9f51a9b63df9044dc Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 12 Mar 2020 21:58:24 -0700 Subject: [PATCH 013/153] [firesim] Update ClockBridge API --- generators/firechip/src/main/scala/TargetConfigs.scala | 3 ++- generators/firechip/src/main/scala/TargetMixins.scala | 3 ++- tools/firrtl | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0d8f38dd55..ffcb681106 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -22,6 +22,7 @@ import icenet._ import firesim.bridges._ import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters} import firesim.configs._ +import midas.widgets.RationalClock class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -348,7 +349,7 @@ class FireSimTraceGenL2Config extends Config( class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(multiplier -> divisor)) + case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) case RocketCrossingKey => up(RocketCrossingKey, site) map { r => r.copy(crossingType = RationalCrossing()) } diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 557612338d..653a450f2a 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -16,6 +16,7 @@ import firesim.bridges.{TracerVBridge} import firesim.util.{HasAdditionalClocks, FireSimClockKey} import midas.targetutils.MemModelAnnotation +import midas.widgets.RationalClock import boom.common.BoomTile @@ -80,7 +81,7 @@ trait CanHaveMultiCycleRegfileImp { trait HasFireSimClockingImp extends HasAdditionalClocks { val outer: HasTiles val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { - case Some((numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) + case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) case None => (clocks(0), reset) } diff --git a/tools/firrtl b/tools/firrtl index f738fbe866..7eb1c7c074 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit f738fbe8667ed6b76ec00a15960b9c3a42b8654a +Subproject commit 7eb1c7c074713335f252bc8e7b48b9f3e057056c From e94dc287b1ec6e30eee5a446fd7acd1fcb4f1120 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 17 Mar 2020 10:48:18 -0700 Subject: [PATCH 014/153] [docs/ci] cleanup docs and add ci to check it (#485) --- .circleci/config.yml | 14 ++++++++++++++ docs/Generators/IceNet.rst | 2 +- docs/Makefile | 4 ++-- docs/TileLink-Diplomacy-Reference/Widgets.rst | 18 +++++++++--------- docs/Tools/Barstools.rst | 2 +- docs/VLSI/Building-A-Chip.rst | 4 ++-- 6 files changed, 29 insertions(+), 15 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index dfadcba68b..dc0188592c 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -145,6 +145,17 @@ jobs: name: Check that the tutorial-setup patches apply command: | scripts/tutorial-setup.sh + documentation-check: + executor: main-env + steps: + - checkout + - run: + name: Check that documentation builds with no warnings/errors + command: | + sudo apt-get update -y + sudo apt-get install -y python3-pip + sudo pip3 install -r docs/requirements.txt + make -C docs html install-riscv-toolchain: executor: main-env @@ -357,6 +368,9 @@ workflows: # Attempt to apply the tutorial patches - tutorial-setup-check + # Check that documentation builds + - documentation-check + # Build extra tests - build-extra-tests: requires: diff --git a/docs/Generators/IceNet.rst b/docs/Generators/IceNet.rst index a859503867..f7daa71e73 100644 --- a/docs/Generators/IceNet.rst +++ b/docs/Generators/IceNet.rst @@ -78,7 +78,7 @@ Configuration To add IceNIC to your design, add ``HasPeripheryIceNIC`` to your lazy module and ``HasPeripheryIceNICModuleImp`` to the module implementation. If you are confused about the distinction between lazy module and module -implementation, refer to :ref:`Cake Pattern`. +implementation, refer to :ref:`Cake Pattern / Mixin`. Then add the ``WithIceNIC`` config fragment to your configuration. This will define ``NICKey``, which IceNIC uses to determine its parameters. The config fragment diff --git a/docs/Makefile b/docs/Makefile index fe9f096356..a6e1b4fd9a 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -2,8 +2,8 @@ # # You can set these variables from the command line. -SPHINXOPTS = -w warnings.txt -SPHINXBUILD = python -msphinx +SPHINXOPTS = -w warnings.txt -n -W +SPHINXBUILD = python3 -msphinx SPHINXPROJ = Chipyard SOURCEDIR = . BUILDDIR = _build diff --git a/docs/TileLink-Diplomacy-Reference/Widgets.rst b/docs/TileLink-Diplomacy-Reference/Widgets.rst index 41fc033bc2..7eba871b59 100644 --- a/docs/TileLink-Diplomacy-Reference/Widgets.rst +++ b/docs/TileLink-Diplomacy-Reference/Widgets.rst @@ -169,7 +169,7 @@ transactions. - ``minSize: Int`` - Minimum size of transfers supported by all outward managers. - ``maxSize: Int`` - Maximum size of transfers supported after the Fragmenter is applied. - ``alwaysMin: Boolean`` - (optional) Fragment all requests down to minSize (else fragment to maximum supported by manager). (default: false) - - ``earlyAck: EarlyAck.T`` - (optional) Should a multibeat Put be acknowledged on the first beat or last beat? + - ``earlyAck: EarlyAck.T`` - (optional) Should a multibeat Put be acknowledged on the first beat or last beat? Possible values (default: ``EarlyAck.None``): - ``EarlyAck.AllPuts`` - always acknowledge on first beat. @@ -270,7 +270,7 @@ the client to see a particular width. **Example Usage:** -.. code-block:: +.. code-block:: scala // Assume the manager node sets beatBytes to 8 // With WidthWidget, client sees beatBytes of 4 @@ -398,11 +398,11 @@ package, not the ``freechips.rocketchip.tilelink`` package like the others. - ``size: Int`` - The size of the memory in bytes - ``contentsDelayed: => Seq[Byte]`` - A function which, when called generates the byte contents of the ROM. - - ``executable: Boolean`` - (optional) Specify whether the CPU can fetch + - ``executable: Boolean`` - (optional) Specify whether the CPU can fetch instructions from the ROM (default: ``true``). - - ``beatBytes: Int`` - (optional) The width of the interface in bytes. + - ``beatBytes: Int`` - (optional) The width of the interface in bytes. (default: 4). - - ``resources: Seq[Resource]`` - (optional) Sequence of resources to add to + - ``resources: Seq[Resource]`` - (optional) Sequence of resources to add to the device tree. **Example Usage:** @@ -429,13 +429,13 @@ The TLRAM and AXI4RAM widgets provide read-write memories implemented as SRAMs. **Arguments:** - ``address: AddressSet`` - The address range that this RAM will cover. - - ``cacheable: Boolean`` - (optional) Can the contents of this RAM be cached. + - ``cacheable: Boolean`` - (optional) Can the contents of this RAM be cached. (default: ``true``) - - ``executable: Boolean`` - (optional) Can the contents of this RAM be fetched + - ``executable: Boolean`` - (optional) Can the contents of this RAM be fetched as instructions. (default: ``true``) - - ``beatBytes: Int`` - (optional) Width of the TL/AXI4 interface in bytes. + - ``beatBytes: Int`` - (optional) Width of the TL/AXI4 interface in bytes. (default: 4) - - ``atomics: Boolean`` - (optional, TileLink only) Does the RAM support + - ``atomics: Boolean`` - (optional, TileLink only) Does the RAM support atomic operations? (default: ``false``) **Example Usage:** diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 3456222784..9089c94788 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -131,5 +131,5 @@ This, unfortunately, breaks the process-agnostic RTL abstraction, so it is recom The simplest way to do this is to have a config fragment that when included updates instantiates the IO cells and connects them in the test harness. When simulating chip-specific designs, it is important to include the IO cells. The IO cell behavioral models will often assert if they are connected incorrectly, which is a useful runtime check. -They also keep the IO interface at the chip and test harness boundary (see :ref:`Separating the top module from the test harness`) consistent after synthesis and place-and-route, +They also keep the IO interface at the chip and test harness boundary (see :ref:`Separating the Top module from the TestHarness module`) consistent after synthesis and place-and-route, which allows the RTL simulation test harness to be reused. diff --git a/docs/VLSI/Building-A-Chip.rst b/docs/VLSI/Building-A-Chip.rst index b684a07b30..9ce283eb6f 100644 --- a/docs/VLSI/Building-A-Chip.rst +++ b/docs/VLSI/Building-A-Chip.rst @@ -45,8 +45,8 @@ It is possible to write this IR directly, or to generate it using simple python While we certainly look forward to having a more featureful toolkit, we have built many chips to date in this way. -Running the VLSI flow ---------------------- +Running the VLSI tool flow +-------------------------- For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. For an example of how to use the VLSI in the context of Chipyard, see :ref:`ASAP7 Tutorial`. From e7730f667c5a202d00cc694bb7cb16c8589f49d1 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 17 Mar 2020 18:04:48 -0700 Subject: [PATCH 015/153] WIP: Fix hammer-sim makefile integration to support debug builds --- vlsi/Makefile | 103 ++++++++++++++++++----------------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 4 files changed, 56 insertions(+), 53 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 800411bd7e..42ca934ad1 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -94,10 +94,45 @@ include $(base_dir)/vcs.mk SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml +.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) +# Update hammer top-level sim targets to include our generated sim configs +redo-sim: $(SIM_CONF) +redo-sim: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-debug: $(SIM_DEBUG_CONF) redo-sim +redo-sim-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +redo-sim-syn: $(SIM_CONF) +redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn +redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +redo-sim-par: $(SIM_CONF) +redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par +redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +sim: $(SIM_CONF) +sim: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-debug: $(SIM_DEBUG_CONF) sim +sim-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + +sim-syn: $(SIM_CONF) +sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn +sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + +sim-par: $(SIM_CONF) +sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-par-debug: $(SIM_DEBUG_CONF) sim-par +sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-par-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ - echo " level: 'gl'" >> $@ + echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ echo ' - "'$$x'"' >> $@; \ @@ -115,7 +150,8 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file echo " '+vcs+lic+wait'," >> $@ echo " '+vc+list'," >> $@ echo " '-f $(sim_common_files)'," >> $@ - echo " '-sverilog']" >> $@ + echo " '-sverilog'," >> $@ + echo " '-debug_pp']" >> $@ echo " options_meta: 'append'" >> $@ echo " defines: [" >> $@ echo " 'CLOCK_PERIOD=1.0'," >> $@ @@ -134,83 +170,50 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags: [" >> $@ echo " '+max-cycles=$(timeout_cycles)'," >> $@ - for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + for x in $(SIM_FLAGS); do \ echo ' "'$$x'",' >> $@; \ done echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ - echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ + echo " benchmarks: ['$(BINARY)']" >> $@ + echo " tb_dut: 'testHarness.top'" >> $@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ - echo " level: 'gl'" >> $@ - echo " input_files:" >> $@ - for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " input_files_meta: 'append'" >> $@ - echo " timescale: '1ns/10ps'" >> $@ - echo " options: [" >> $@ - echo " '$(RISCV)/lib/libfesvr.a'," >> $@ - echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ - echo " '-error=PCWM-L'," >> $@ - echo " '-quiet'," >> $@ - echo " '-q'," >> $@ - echo " '+rad'," >> $@ - echo " '+v2k'," >> $@ - echo " '+vcs+lic+wait'," >> $@ - echo " '+vc+list'," >> $@ - echo " '-f $(sim_common_files)'," >> $@ - echo " '-sverilog'," >> $@ - echo " '-debug_pp']" >> $@ - echo " options_meta: 'append'" >> $@ echo " defines: [" >> $@ - echo " 'DEBUG'," >> $@ - echo " 'CLOCK_PERIOD=1.0'," >> $@ - echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ - echo " 'STOP_COND=!$(TB).reset'," >> $@ - echo " 'RANDOMIZE_MEM_INIT'," >> $@ - echo " 'RANDOMIZE_REG_INIT'," >> $@ - echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ - echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " 'DEBUG']" >> $@ echo " defines_meta: 'append'" >> $@ - echo " compiler_opts: [" >> $@ - echo " '-I$(RISCV)/include'," >> $@ - echo " '-std=c++11']" >> $@ - echo " compiler_opts_meta: 'append'" >> $@ - echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ - echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags: [" >> $@ - echo " '+max-cycles=$(timeout_cycles)'," >> $@ - for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ echo ' "'$$x'",' >> $@; \ done - echo " '+vcdplusfile=$(OBJ_DIR)/sim-tool-output.vpd']" >> $@ + echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ - echo " tb_dut: 'testHarness.top'" >> $@ - echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ - #echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add']" >> $@ $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "power.inputs:" > $@ -sim_conf_temp: $(SIM_CONF) $(SIM_DEBUG_CONF) - ######################################################################################### # synthesis input configuration ######################################################################################### SYN_CONF = $(OBJ_DIR)/inputs.yml -GENERATED_CONFS = $(SYN_CONF) $(SIM_CONF) +GENERATED_CONFS = $(SYN_CONF) ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) mkdir -p $(dir $@) - echo "synthesis.inputs:" > $@ + echo "sim.inputs:" > $@ + echo " input_files:" >> $@ + for x in $(VLSI_RTL); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ for x in $(VLSI_RTL) `cat $(VLSI_BB)`; do \ @@ -236,4 +239,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) ######################################################################################### .PHONY: clean clean: - rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) + rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) diff --git a/vlsi/hammer b/vlsi/hammer index 2d3890bfca..b1aebbef2f 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 2d3890bfca2ef8a8e8c74ed447bddbb30789fd5c +Subproject commit b1aebbef2f53da746e86f93f945302eb97abec6d diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 8f23bfa8c9..fdc3ad051a 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 8f23bfa8c971ceb39b10aa52d6c9f446c5303cd3 +Subproject commit fdc3ad051a2c2edae8346730ce7c0f569aaa97b0 diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index f812f8ce85..f8579e55b9 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit f812f8ce85b5f77b563807bbb490b46ce82c1711 +Subproject commit f8579e55b96208758c0ed43f3bdba0bbc67ef6b5 From a2177ee20989297935939d3e9aabbfaaa1fe88f2 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 18 Mar 2020 11:03:58 -0700 Subject: [PATCH 016/153] Add Gemmini to README [ci skip] (#487) --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 0eec2d87e2..8d4cccc526 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. @@ -64,3 +64,4 @@ These publications cover many of the internal components used in Chipyard. Howev [boom]: https://github.com/ucb-bar/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ [ariane]: https://github.com/pulp-platform/ariane/ +[gemmini]: https://github.com/ucb-bar/gemmini From 7a17323bed90dc8a7e64dc286b57a1d0fa456e94 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 19 Mar 2020 10:00:17 -0700 Subject: [PATCH 017/153] [firechip] Isolate all firesim-multiclock stuff in a single file --- build.sbt | 3 +- .../firechip/src/main/scala/FireSim.scala | 41 ++----- .../src/main/scala/FireSimMulticlockPOC.scala | 104 ++++++++++++++++++ .../src/main/scala/TargetConfigs.scala | 17 +-- .../src/test/scala/ScalaTestSuite.scala | 13 ++- 5 files changed, 122 insertions(+), 56 deletions(-) create mode 100644 generators/firechip/src/main/scala/FireSimMulticlockPOC.scala diff --git a/build.sbt b/build.sbt index a633066f73..b0eea0a82b 100644 --- a/build.sbt +++ b/build.sbt @@ -204,5 +204,6 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, - testGrouping in Test := isolateAllTests( (definedTests in Test).value ) + testGrouping in Test := isolateAllTests( (definedTests in Test).value ), + testOptions in Test += Tests.Argument("-oF") ) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index c6293e908a..221548c331 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -5,11 +5,9 @@ package firesim.firesim import chisel3._ import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} -import freechips.rocketchip.subsystem.{HasTiles} -import freechips.rocketchip.util.{ResetCatchAndSync} +import freechips.rocketchip.diplomacy.{LazyModule} -import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} +import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge} import chipyard.{BuildTop} import chipyard.iobinders.{IOBinders} @@ -22,43 +20,20 @@ class WithNumNodes(n: Int) extends Config((pname, site, here) => { case NumNodes => n }) -case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) { - def numClocks(): Int = additionalClocks.size + 1 -} -case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq())) - -trait HasAdditionalClocks extends LazyModuleImp { - val clocks = IO(Vec(p(FireSimClockKey).numClocks, Input(Clock()))) -} - -trait HasFireSimClockingImp extends HasAdditionalClocks { - val outer: HasTiles - val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { - case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) - case None => (clocks(0), reset) - } - - outer.tiles.foreach({ case tile => - tile.module.clock := tileClock - tile.module.reset := tileReset - }) -} - -class FireSim[T <: LazyModule](implicit val p: Parameters) extends RawModule { - val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) - val refClock = clockBridge.io.clocks(0) +class FireSim(implicit val p: Parameters) extends RawModule { + val clockBridge = Module(new RationalClockBridge) + val clock = clockBridge.io.clocks.head val reset = WireInit(false.B) - withClockAndReset(refClock, reset) { + withClockAndReset(clock, reset) { // Instantiate multiple instances of the DUT to implement supernode val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) - val peekPokeBridge = PeekPokeBridge(refClock, reset) + val peekPokeBridge = PeekPokeBridge(clock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance for ((target) <- targets) { - p(IOBinders).values.map(fn => fn(refClock, reset.asBool, false.B, target)) + p(IOBinders).values.map(fn => fn(clock, reset.asBool, false.B, target)) } - targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks }) } } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala new file mode 100644 index 0000000000..318e3547a6 --- /dev/null +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -0,0 +1,104 @@ +//See LICENSE for license details. + +package firesim.firesim + +import chisel3._ + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, RationalCrossing} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.util.{ResetCatchAndSync} + +import boom.common.{BoomTilesKey, BoomCrossingKey} + +import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} +import firesim.configs._ + +import chipyard.{BuildTop, Top, TopModule} +import chipyard.config.ConfigValName._ +import chipyard.iobinders.{IOBinders} + +// WIP! This file is a sketch of one means of defining a multiclock target-design +// that can be simulated in FireSim, pending a canonicalized form in Chipyard. +// +// Note, the main prerequisite for supporting an additional clock domain in a +// FireSim simulation is to supply an additional clock parameter +// (RationalClock) to the clock bridge (RationalClockBridge). The bridge +// produces a vector of clocks, based on the provided parameter list, which you +// may use freely without further modifications to your target design. + +case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) { + def numClocks(): Int = additionalClocks.size + 1 +} +case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq())) + +trait HasAdditionalClocks extends LazyModuleImp { + val clocks = IO(Vec(p(FireSimClockKey).numClocks, Input(Clock()))) +} + +// Presupposes only 1 or 2 clocks. +trait HasFireSimClockingImp extends HasAdditionalClocks { + val outer: HasTiles + val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { + case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) + case None => (clocks.head, reset) + } + + outer.tiles.foreach({ case tile => + tile.module.clock := tileClock + tile.module.reset := tileReset + }) +} + +// Config Fragment +class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => { + case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) + case RocketCrossingKey => up(RocketCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } + case BoomCrossingKey => up(BoomCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } +}) + +class HalfRateUncore extends WithSingleRationalTileDomain(2,1) + +class WithFiresimMulticlockTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("Top").module) +}) + +// Complete Config +class FireSimQuadRocketMulticlockConfig extends Config( + new HalfRateUncore ++ + new WithFiresimMulticlockTop ++ + new FireSimQuadRocketConfig) + +// Top Definition +class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.Top +{ + override lazy val module = new FiresimMulticlockTopModule(this) +} + +class FiresimMulticlockTopModule[+L <: Top](l: L) extends chipyard.TopModule(l) with HasFireSimClockingImp + +// Harness Definition +class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { + val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) + val refClock = clockBridge.io.clocks.head + val reset = WireInit(false.B) + withClockAndReset(refClock, reset) { + // Instantiate multiple instances of the DUT to implement supernode + val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) + val peekPokeBridge = PeekPokeBridge(refClock, reset) + // A Seq of partial functions that will instantiate the right bridge only + // if that Mixin trait is present in the target's class instance + // + // Apply each partial function to each DUT instance + for ((target) <- targets) { + p(IOBinders).values.map(fn => fn(refClock, reset.asBool, false.B, target)) + } + targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks }) + } +} + + diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index ae5d785231..1f9791ee67 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -12,9 +12,8 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} -import freechips.rocketchip.diplomacy.{RationalCrossing} import freechips.rocketchip.diplomacy.LazyModule -import boom.common.{BoomTilesKey, BoomCrossingKey} +import boom.common.BoomTilesKey import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} @@ -24,7 +23,6 @@ import ariane.ArianeTilesKey import testchipip.WithRingSystemBus import firesim.bridges._ -import midas.widgets.{RationalClock} import firesim.configs._ import chipyard.{BuildTop} import chipyard.config.ConfigValName._ @@ -47,18 +45,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq) }) -class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) - case RocketCrossingKey => up(RocketCrossingKey, site) map { r => - r.copy(crossingType = RationalCrossing()) - } - case BoomCrossingKey => up(BoomCrossingKey, site) map { r => - r.copy(crossingType = RationalCrossing()) - } -}) - -class HalfRateUncore extends WithRationalTiles(2,1) - class WithPerfCounters extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( @@ -197,7 +183,6 @@ class SupernodeFireSimRocketConfig extends Config( //********************************************************************************** //* Ariane Configurations //*********************************************************************************/ - class FireSimArianeConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 161167d928..ee368052bd 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -131,23 +131,24 @@ abstract class FireSimTestSuite( elaborate generateTestSuiteMakefrags runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) - diffTracelog("rv64ui-p-simple.out") + //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) runSuite("verilator")(FastBlockdevTests) } -class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "BaseF1Config") +class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } -class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") -class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") +// Disabled until RAM optimizations re-enabled in multiclock +//class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") +//class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") // Multiclock tests class RocketMulticlockF1Tests extends FireSimTestSuite( - "FireSim", - "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", + "FireSimMulticlockPOC", + "FireSimQuadRocketMulticlockConfig", "WithSynthAsserts_BaseF1Config") abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) From 2528708c15a189c216250b65f95877fce27273aa Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 16 Mar 2020 13:59:06 -0700 Subject: [PATCH 018/153] add documentation on ring network and system bus --- docs/Customization/Memory-Hierarchy.rst | 14 ++++++++++++++ docs/Generators/TestChipIP.rst | 16 +++++++++++++++- .../src/main/scala/config/RocketConfigs.scala | 2 ++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 6c924ceb32..733e70c6e8 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -38,6 +38,20 @@ Note that these configurations fully remove the L2 cache and mbus. This configuration fully removes the L2 cache and memory bus by setting the number of channels and number of banks to 0. +The System Bus +-------------- + +The system bus is the TileLink network that sits between the tiles and the L2 +agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, +but TestChipIP provides a version that uses a ring network instead. This can +be useful when taping out larger systems. To use the ring network system +bus, simply add the ``WithRingSystemBus`` config fragment to your configuration. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala + :language: scala + :start-after: DOC include start: RingSystemBusRocket + :end-before: DOC include end: RingSystemBusRocket + The SiFive L2 Cache ------------------- diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index f85636b138..31f9ce536b 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -3,7 +3,8 @@ Test Chip IP Chipyard includes a Test Chip IP library which provides various hardware widgets that may be useful when designing SoCs. This includes a :ref:`Serial Adapter`, -:ref:`Block Device Controller`, :ref:`TileLink SERDES`, :ref:`TileLink Switcher`, and :ref:`UART Adapter`. +:ref:`Block Device Controller`, :ref:`TileLink SERDES`, :ref:`TileLink Switcher`, +:ref:`TileLink Ring Network`, and :ref:`UART Adapter`. Serial Adapter -------------- @@ -60,6 +61,19 @@ the select signal once TileLink messages have begun sending. For an example of how to use the switcher, take a look at the ``SwitcherTest`` unit test in the `Test Chip IP unit tests `_. +TileLink Ring Network +--------------------- + +TestChipIP provides a TLRingNetwork generator that has a similar interface +to the TLXbar provided by RocketChip, but uses ring networks internally rather +than crossbars. This can be useful for chips with very wide TileLink networks +(many cores and L2 banks) that can sacrifice cross-section bandwidth to relieve +wire routing congestion. Documentation on how to use the ring network can be +found in :ref:`The System Bus`. The implementation itself can be found +`here `_, +and may serve as an example of how to implement your own TileLink network with +a different topology. + UART Adapter ------------ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 954c531b01..e25680ca28 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -364,6 +364,7 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) // DOC include end: scratchpadrocket +// DOC include start: RingSystemBusRocket class RingSystemBusRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ @@ -382,3 +383,4 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +// DOC include end: RingSystemBusRocket From b17de6a4ddb9c9edf61c1d689b2f0dddeec8c7d4 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 20 Mar 2020 16:29:05 -0700 Subject: [PATCH 019/153] Hide my sins Also begin power integration --- vlsi/Makefile | 62 ++++++++++++++++++++++----------------------------- vlsi/hammer | 2 +- vlsi/power.mk | 6 +++++ vlsi/sim.mk | 38 +++++++++++++++++++++++++++++++ 4 files changed, 72 insertions(+), 36 deletions(-) create mode 100644 vlsi/power.mk create mode 100644 vlsi/sim.mk diff --git a/vlsi/Makefile b/vlsi/Makefile index 42ca934ad1..cbeceb3eb1 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -93,42 +93,9 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) include $(base_dir)/vcs.mk SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml +SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml -.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) -# Update hammer top-level sim targets to include our generated sim configs -redo-sim: $(SIM_CONF) -redo-sim: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) -redo-sim-debug: $(SIM_DEBUG_CONF) redo-sim -redo-sim-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) - -redo-sim-syn: $(SIM_CONF) -redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) -redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn -redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) - -redo-sim-par: $(SIM_CONF) -redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) -redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par -redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) - -sim: $(SIM_CONF) -sim: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) -sim-debug: $(SIM_DEBUG_CONF) sim -sim-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) - -sim-syn: $(SIM_CONF) -sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) -sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn -sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -$(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) - -sim-par: $(SIM_CONF) -sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) -sim-par-debug: $(SIM_DEBUG_CONF) sim-par -sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -$(OBJ_DIR)/sim-par-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) - +include $(vlsi_dir)/sim.mk $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ @@ -190,11 +157,36 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo done echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ + echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ +$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " defines: [" >> $@ + echo " 'NTC']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " timing_annotated: 'true'" >> $@ +POWER_CONF = $(OBJ_DIR)/power-inputs.yml +include $(vlsi_dir)/power.mk +LOWER_VLSI_TOP = $(shell echo $(VLSI_TOP) | tr A-Z a-z) $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "power.inputs:" > $@ + echo " tb_dut: 'testHarness/$(LOWER_VLSI_TOP)'" >> $@ + echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ + echo " saifs: [" >> $@ + echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@ + echo " ]" >> $@ + echo " waveforms: [" >> $@ + echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@ + echo " ]" >> $@ + echo " start_times: [" >> $@ + echo " 0" >> $@ + echo " ]" >> $@ + echo " end_times: [" >> $@ + echo " 15000" >> $@ #timeout_cycles * clock_period + echo " ]" >> $@ ######################################################################################### # synthesis input configuration diff --git a/vlsi/hammer b/vlsi/hammer index b1aebbef2f..493657c1ac 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit b1aebbef2f53da746e86f93f945302eb97abec6d +Subproject commit 493657c1ac1a6764a592bd013208648ba19d4fbd diff --git a/vlsi/power.mk b/vlsi/power.mk new file mode 100644 index 0000000000..a5e1633b02 --- /dev/null +++ b/vlsi/power.mk @@ -0,0 +1,6 @@ +.PHONY: $(POWER_CONF) +power: $(POWER_CONF) +power: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) +redo-power: $(POWER_CONF) +redo-power: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) +$(OBJ_DIR)/power-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) diff --git a/vlsi/sim.mk b/vlsi/sim.mk new file mode 100644 index 0000000000..71b05ae780 --- /dev/null +++ b/vlsi/sim.mk @@ -0,0 +1,38 @@ +.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) +# Update hammer top-level sim targets to include our generated sim configs +redo-sim: $(SIM_CONF) +redo-sim: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-debug: $(SIM_DEBUG_CONF) redo-sim +redo-sim-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +redo-sim-syn: $(SIM_CONF) +redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn +redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +redo-sim-par: $(SIM_CONF) +redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par +redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +redo-sim-par-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug +redo-sim-par-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF) + +sim: $(SIM_CONF) +sim: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-debug: $(SIM_DEBUG_CONF) sim +sim-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + +sim-syn: $(SIM_CONF) +sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn +sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + +sim-par: $(SIM_CONF) +sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-par-debug: $(SIM_DEBUG_CONF) sim-par +sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +sim-par-timing-debug: $(SIM_TIMING_CONF) sim-par-debug +sim-par-timing-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_TIMING_CONF) +$(OBJ_DIR)/sim-par-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) From 1b7158835ae0bb2f09b0b942fd0636a74e55139e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 24 Mar 2020 10:41:17 -0700 Subject: [PATCH 020/153] Bump firesim for CI --- .../src/test/scala/ScalaTestSuite.scala | 69 ++++++++++--------- sims/firesim | 2 +- 2 files changed, 36 insertions(+), 35 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index ee368052bd..83d57e24f4 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -151,37 +151,38 @@ class RocketMulticlockF1Tests extends FireSimTestSuite( "FireSimQuadRocketMulticlockConfig", "WithSynthAsserts_BaseF1Config") -abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) - extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { - val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - - lazy val generatorArgs = GeneratorArgs( - midasFlowKind = "midas", - targetDir = "generated-src", - topModuleProject = "firesim.firesim", - topModuleClass = "FireSimTraceGen", - targetConfigProject = "firesim.firesim", - targetConfigs = targetConfig ++ "_WithScalaTestFeatures", - platformConfigProject = "firesim.firesim", - platformConfigs = platformConfig) - - // From HasFireSimGeneratorUtilities - // For the firesim utilities to use the same directory as the test suite - override lazy val testDir = genDir - - // From TestSuiteCommon - val targetTuple = generatorArgs.tupleName - val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", - s"TARGET_CONFIG=${generatorArgs.targetConfigs}", - s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") - - it should "pass" in { - assert(make("fsim-tracegen") == 0) - } -} - -class FireSimLLCTraceGenTest extends FireSimTraceGenTest( - "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config") - -class FireSimL2TraceGenTest extends FireSimTraceGenTest( - "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config") +// Jerry broke these -- damn it Jerry. +//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) +// extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { +// val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs +// +// lazy val generatorArgs = GeneratorArgs( +// midasFlowKind = "midas", +// targetDir = "generated-src", +// topModuleProject = "firesim.firesim", +// topModuleClass = "FireSimTraceGen", +// targetConfigProject = "firesim.firesim", +// targetConfigs = targetConfig ++ "_WithScalaTestFeatures", +// platformConfigProject = "firesim.firesim", +// platformConfigs = platformConfig) +// +// // From HasFireSimGeneratorUtilities +// // For the firesim utilities to use the same directory as the test suite +// override lazy val testDir = genDir +// +// // From TestSuiteCommon +// val targetTuple = generatorArgs.tupleName +// val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", +// s"TARGET_CONFIG=${generatorArgs.targetConfigs}", +// s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") +// +// it should "pass" in { +// assert(make("fsim-tracegen") == 0) +// } +//} +// +//class FireSimLLCTraceGenTest extends FireSimTraceGenTest( +// "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config") +// +//class FireSimL2TraceGenTest extends FireSimTraceGenTest( +// "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config") diff --git a/sims/firesim b/sims/firesim index ce0d05a10a..552a9764a1 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ce0d05a10a47e58e17e1b081115429dc6328768d +Subproject commit 552a9764a1b5aebfc9b98c11b2cea944b8befbdd From 7704f38d8da2bd38758df2a57d54c789da1eb407 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Mar 2020 00:23:03 -0700 Subject: [PATCH 021/153] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 552a9764a1..998eeaea23 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 552a9764a1b5aebfc9b98c11b2cea944b8befbdd +Subproject commit 998eeaea230884584dd3fe2bd3727c5f30abc3cb From fbc47af67cb8df379347b26e30c3b7ade75306b7 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Mar 2020 10:19:51 -0700 Subject: [PATCH 022/153] Bump testchipip to dev [ci skip] --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 582f17da80..30d44252e8 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 582f17da80dbe0e03a35247a385f34bd88a656ce +Subproject commit 30d44252e8a990da38f1fed6ac6c810fb42dae28 From b5b15878279b2ff86b7b1a76d046e9f65deeb622 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Mar 2020 10:34:14 -0700 Subject: [PATCH 023/153] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 998eeaea23..3cf0d45e07 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 998eeaea230884584dd3fe2bd3727c5f30abc3cb +Subproject commit 3cf0d45e07c0685cafaf02f86d91ff114e160b38 From 3d253c0f6751d5da1b4484a219ddec0dd4bff620 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 30 Mar 2020 17:04:45 -0700 Subject: [PATCH 024/153] [make] split up specific make vars/targets into frags (#499) * [make] split up specific make vars/targets into frags * [make] move dramsim and max-cycles into SIM_FLAGS * [misc] move ariane configs to configs/ folder --- common.mk | 45 ++++++++----------- generators/ariane | 2 +- .../scala/{ => config}/ArianeConfigs.scala | 0 generators/tracegen/tracegen.mk | 18 ++++++++ sims/vcs/Makefile | 11 ++--- sims/verilator/Makefile | 25 ++++++++--- variables.mk | 2 +- 7 files changed, 62 insertions(+), 41 deletions(-) rename generators/chipyard/src/main/scala/{ => config}/ArianeConfigs.scala (100%) create mode 100644 generators/tracegen/tracegen.mk diff --git a/common.mk b/common.mk index bf40e60262..4fb2cf8216 100644 --- a/common.mk +++ b/common.mk @@ -3,6 +3,18 @@ ######################################################################################### SHELL=/bin/bash +######################################################################################### +# extra make variables/rules from subprojects +# +# EXTRA_GENERATOR_REQS - requirements needed for the main generator +# EXTRA_SIM_FLAGS - runtime simulation flags +# EXTRA_SIM_CC_FLAGS - cc flags for simulators +# EXTRA_SIM_SOURCES - simulation sources needed for simulator +# EXTRA_SIM_REQS - requirements to build the simulator +######################################################################################### +include $(base_dir)/generators/ariane/ariane.mk +include $(base_dir)/generators/tracegen/tracegen.mk + ######################################################################################### # variables to get all *.scala files ######################################################################################### @@ -11,7 +23,6 @@ lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -prin SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) -ARIANE_VLOG_SOURCES = $(call lookup_srcs,$(base_dir)/generators/ariane,sv) $(call lookup_srcs,$(base_dir)/generators/ariane,v) ######################################################################################### # rocket and testchipip classes @@ -45,7 +56,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp @echo "" > /dev/null # AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile -generator_temp: $(SCALA_SOURCES) $(ARIANE_VLOG_SOURCES) $(sim_files) +generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" @@ -105,19 +116,19 @@ verilog: $(sim_vsrcs) ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) ######################################################################################### # helper rules to run simulator as fast as possible ######################################################################################### run-binary-fast: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -129,10 +140,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator @@ -141,26 +152,6 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) -include $(build_dir)/$(long_name).d endif -################################################# -# Rules for running and checking tracegen tests # -################################################# - -AXE_DIR=$(base_dir)/tools/axe/src -AXE=$(AXE_DIR)/axe - -$(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh - cd $(AXE_DIR) && ./make.sh - -$(output_dir)/tracegen.out: $(sim) - mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ - -$(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) - $(base_dir)/scripts/check-tracegen.sh $< > $@ - -tracegen: $(output_dir)/tracegen.result - -.PHONY: tracegen - ####################################### # Rules for building DRAMSim2 library # ####################################### diff --git a/generators/ariane b/generators/ariane index 145b5ed106..e02436d2aa 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 145b5ed106efd0b22c2105c20722ab303fa4039b +Subproject commit e02436d2aaf934b6e58d5e11e87276ba0d840f2a diff --git a/generators/chipyard/src/main/scala/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala similarity index 100% rename from generators/chipyard/src/main/scala/ArianeConfigs.scala rename to generators/chipyard/src/main/scala/config/ArianeConfigs.scala diff --git a/generators/tracegen/tracegen.mk b/generators/tracegen/tracegen.mk new file mode 100644 index 0000000000..fc4bd2465b --- /dev/null +++ b/generators/tracegen/tracegen.mk @@ -0,0 +1,18 @@ +############################################################## +# extra variables/targets ingested by the chipyard make system +############################################################## + +AXE_DIR=$(base_dir)/tools/axe/src +AXE=$(AXE_DIR)/axe + +$(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh + cd $(AXE_DIR) && ./make.sh + +$(output_dir)/tracegen.out: $(sim) + mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ + +$(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) + $(base_dir)/scripts/check-tracegen.sh $< > $@ + +.PHONY: tracegen +tracegen: $(output_dir)/tracegen.result diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index e829047cbb..659d1fc03a 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -50,7 +50,8 @@ VCS_CC_OPTS = \ -CC "-I$(dramsim_dir)" \ -CC "-std=c++11" \ $(dramsim_lib) \ - $(RISCV)/lib/libfesvr.a + $(RISCV)/lib/libfesvr.a \ + -CC "$(EXTRA_SIM_CC_FLAGS)" VCS_NONCC_OPTS = \ +lint=all,noVCDE,noONGS,noUI \ @@ -80,16 +81,16 @@ VCS_DEFINES = \ +define+RANDOMIZE_GARBAGE_ASSIGN \ +define+RANDOMIZE_INVALID_ASSIGN -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) $(EXTRA_SIM_SOURCES) ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) +$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) +$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG \ -debug_pp @@ -99,7 +100,7 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) ######################################################################################### .PRECIOUS: $(output_dir)/%.vpd %.vpd $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 13e7d20125..8bd4cd75ee 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -47,14 +47,25 @@ include $(base_dir)/common.mk ######################################################################################### VERILATOR := verilator --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim +CXXFLAGS := \ + $(CXXFLAGS) -O1 -std=c++11 \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -D__STDC_FORMAT_MACROS \ + $(EXTRA_SIM_CC_FLAGS) + +LDFLAGS := \ + $(LDFLAGS) \ + -L$(sim_dir) \ + -lpthread VERILATOR_CC_OPTS = \ -O3 \ -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \ - -LDFLAGS "$(LDFLAGS)" + -LDFLAGS "$(LDFLAGS)" \ + $(RISCV)/lib/libfesvr.a \ + $(dramsim_lib) # default flags added for ariane ARIANE_VERILATOR_FLAGS = \ @@ -87,7 +98,7 @@ VERILATOR_DEFINES = \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) -VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES) ######################################################################################### # verilator build paths and file names @@ -104,13 +115,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules ######################################################################################### -$(model_mk): $(sim_vsrcs) $(sim_common_files) +$(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ -$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) +$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" @@ -132,7 +143,7 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/variables.mk b/variables.mk index 8a1bb1dfc0..5692296bcb 100644 --- a/variables.mk +++ b/variables.mk @@ -143,7 +143,7 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +override SIM_FLAGS += +dramsim +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose sim_out_name = $(subst $() $(),_,$(notdir $(basename $(BINARY))).$(long_name)) From 1f98c842100f4fa1e4b39cc0fc95e7b5f19a8829 Mon Sep 17 00:00:00 2001 From: John Wright Date: Wed, 1 Apr 2020 14:03:56 -0700 Subject: [PATCH 025/153] Add ChipTop to enable real chip configs with IO cells, etc. (#480) This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success). * A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem. * BuildTop now builds a ChipTop dut module in the TestHarness by default * A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top) * The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions). * IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation. * The default for the TOP make variable is now ChipTop (was Top) --- build.sbt | 6 +- common.mk | 2 +- docs/Advanced-Concepts/Top-Testharness.rst | 21 +- .../Configs-Parameters-Mixins.rst | 15 +- docs/Customization/DMA-Devices.rst | 6 +- docs/Customization/IOBinders.rst | 24 +- docs/Customization/Keys-Traits-Configs.rst | 16 +- docs/Customization/MMIO-Peripherals.rst | 18 +- .../chipyard/src/main/scala/ChipTop.scala | 102 ++++++++ .../src/main/scala/ConfigFragments.scala | 16 +- .../scala/{Top.scala => DigitalTop.scala} | 10 +- .../chipyard/src/main/scala/IOBinders.scala | 237 +++++++++++++----- .../chipyard/src/main/scala/TestHarness.scala | 28 ++- .../main/scala/config/TracegenConfigs.scala | 10 +- .../src/main/scala/BridgeBinders.scala | 70 ++++-- .../firechip/src/main/scala/FireSim.scala | 6 +- .../src/main/scala/FireSimMulticlockPOC.scala | 12 +- .../src/main/scala/TargetConfigs.scala | 1 - generators/icenet | 2 +- generators/testchipip | 2 +- scripts/tutorial-patches/build.sbt.patch | 2 +- tools/barstools | 2 +- variables.mk | 2 +- 23 files changed, 444 insertions(+), 166 deletions(-) create mode 100644 generators/chipyard/src/main/scala/ChipTop.scala rename generators/chipyard/src/main/scala/{Top.scala => DigitalTop.scala} (86%) diff --git a/build.sbt b/build.sbt index b0eea0a82b..05f05d7b45 100644 --- a/build.sbt +++ b/build.sbt @@ -122,8 +122,12 @@ lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) +lazy val iocell = (project in file("./tools/barstools/iocell/")) + .dependsOn(chisel) + .settings(commonSettings) + lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches gemmini, icenet, tracegen, ariane) .settings(commonSettings) diff --git a/common.mk b/common.mk index 4fb2cf8216..a98e0e2486 100644 --- a/common.mk +++ b/common.mk @@ -20,7 +20,7 @@ include $(base_dir)/generators/tracegen/tracegen.mk ######################################################################################### lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 8df377692a..ebd5b3702f 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -2,17 +2,28 @@ Tops, Test-Harnesses, and the Test-Driver =========================================== The three highest levels of hierarchy in a Chipyard -SoC are the Top (DUT), ``TestHarness``, and the ``TestDriver``. -The Top and ``TestHarness`` are both emitted by Chisel generators. +SoC are the ``ChipTop`` (DUT), ``TestHarness``, and the ``TestDriver``. +The ``ChipTop`` and ``TestHarness`` are both emitted by Chisel generators. The ``TestDriver`` serves as our testbench, and is a Verilog file in Rocket Chip. -Top/DUT +ChipTop/DUT ------------------------- -The top-level module of a Rocket Chip SoC is composed via cake-pattern. -Specifically, "Tops" extend a ``System``, which extends a ``Subsystem``, which extends a ``BaseSubsystem``. +``ChipTop`` is the top-level module that instantiates the ``System`` submodule, usually an instance of the concrete class ``DigitalTop``. +The vast majority of the design resides in the ``System``. +Other components that exist inside the ``ChipTop`` layer are generally IO cells, clock receivers and multiplexers, reset synchronizers, and other analog IP that needs to exist outside of the ``System``. +The ``IOBinders`` are responsible for instantiating the IO cells and defining the test harness collateral that connects to the top-level ports. +Most of these types of devices can be instantiated using custom ``IOBinders``, so the provided ``ChipTop`` and ``ChipTopCaughtReset`` classes are sufficient. +However, if needed, the ``BaseChipTop`` abstract class can be extended for building more custom ``ChipTop`` designs. + + +System/DigitalTop +------------------------- + +The system module of a Rocket Chip SoC is composed via cake-pattern. +Specifically, ``DigitalTop`` extends a ``System``, which extends a ``Subsystem``, which extends a ``BaseSubsystem``. BaseSubsystem diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index 9d7d86d01d..94067aa119 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -77,10 +77,10 @@ It is used in the Rocket Chip SoC library and Chipyard framework in merging mult This example shows the Chipyard default top that composes multiple traits together into a fully-featured SoC with many optional components. -.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module @@ -88,8 +88,8 @@ implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to all the logical connections between generators and exchanges configuration information among them, while the lazy module implementation performs the actual Chisel RTL elaboration. -In the ``Top`` example class, the "outer" ``Top`` instantiates the "inner" -``TopModule`` as a lazy module implementation. This delays immediate elaboration +In the ``DigitalTop`` example class, the "outer" ``DigitalTop`` instantiates the "inner" +``DigitalTopModule`` as a lazy module implementation. This delays immediate elaboration of the module until all logical connections are determined and all configuration information is exchanged. The ``System`` outer base class, as well as the ``CanHavePeriphery`` outer traits contain code to perform high-level logical @@ -102,8 +102,9 @@ For example, the ``CanHavePeripherySerialModuleImp`` trait optionally physically the ``SerialAdapter`` module, and instantiates queues. In the test harness, the SoC is elaborated with -``val dut = Module(LazyModule(Top))``. -After elaboration, the result will be a ``Top`` module, which contains a +``val dut = p(BuildTop)(p)``. + +After elaboration, the system submodule of ``ChipTop`` will be a ``DigitalTop`` module, which contains a ``SerialAdapter`` module (among others), if the config specified for that block to be instantiated. From a high level, classes which extend ``LazyModule`` *must* reference diff --git a/docs/Customization/DMA-Devices.rst b/docs/Customization/DMA-Devices.rst index 554ff2d4aa..549a155691 100644 --- a/docs/Customization/DMA-Devices.rst +++ b/docs/Customization/DMA-Devices.rst @@ -15,10 +15,10 @@ that writes zeros to the memory at a configured address. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/InitZero.scala :language: scala -.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop We use ``TLHelper.makeClientNode`` to create a TileLink client node for us. We then connect the client node to the memory system through the front bus (fbus). diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 59924a0fce..6332d07a97 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -1,7 +1,7 @@ IOBinders ========= -In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to determine what modules to bind to the IOs of a ``Top`` in the ``TestHarness``. +In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to instantiate IO cells in the ``ChipTop`` layer and determine what modules to bind to the IOs of a ``ChipTop`` in the ``TestHarness``. .. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala :language: scala @@ -9,11 +9,27 @@ In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to determine what :end-before: DOC include end: IOBinders -This special key solves the problem of duplicating test-harnesses for each different ``Top`` type. +This special key solves the problem of duplicating test-harnesses for each different ``System`` type. +You could just as well create a custom harness module that attaches IOs explicitly. +Instead, the ``IOBinders`` key provides a map from Scala traits to attachment behaviors. +Each ``IOBinder`` returns a tuple of three values: the list of ``ChipTop`` ports created by the ``IOBinder``, the list of all IO cell modules instantiated by the ``IOBinder``, and an optional function to be called inside the test harness. +This function is responsible for instantiating logic inside the ``TestHarness`` to appropriately drive the ``ChipTop`` IO ports created by the ``IOBinder``. +Conveniently, because the ``IOBinder`` is generating the port, it may also use the port inside this function, which prevents the ``BaseChipTop`` code from ever needing to access the port ``val``, thus having the ``IOBinder`` house all port specific code. +This scheme prevents the need to have two separate binder functions for each ``System`` trait. +When creating custom ``IOBinders`` it is important to use ``suggestName`` to name ports; otherwise Chisel will raise an exception trying to name the IOs. +The example ``IOBinders`` demonstrate this. -You could just as well create a custom harness module that attaches IOs explicitly. Instead, the IOBinders key provides a map from Scala traits to attachment behaviors. +As an example, the ``WithGPIOTiedOff`` IOBinder creates IO cells for the GPIO module(s) instantiated in the ``System``, then punches out new ``Analog`` ports for each one. +The test harness simply ties these off, but additional logic could be inserted to perform some kind of test in the ``TestHarness``. -For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``Top`` which matches ``CanHaveMasterAXI4MemPortModuleImp`` will have a ``SimAXIMem`` connected. +.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala + :language: scala + :start-after: DOC include start: WithGPIOTiedOff + :end-before: DOC include end: WithGPIOTiedOff + + +``IOBinders`` also do not need to create ports. Some ``IOBinders`` can simply insert circuitry inside the ``ChipTop`` layer. +For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``System`` which matches ``CanHaveMasterAXI4MemPortModuleImp`` will have a ``SimAXIMem`` connected inside ``ChipTop``. .. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala :language: scala diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index ffa303b7ba..f4af3746d8 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -34,25 +34,25 @@ Accessing the value stored in the key is easy in Chisel, as long as the ``implic Traits ------ -Typically, most custom blocks will need to modify the behavior of some pre-existing block. For example, the GCD widget needs the ``Top`` module to instantiate and connect the widget via Tilelink, generate a top-level ``gcd_busy`` port, and connect that to the module as well. Traits let us do this without modifying the existing code for the ``Top``, and enables compartmentalization of code for different custom blocks. +Typically, most custom blocks will need to modify the behavior of some pre-existing block. For example, the GCD widget needs the ``DigitalTop`` module to instantiate and connect the widget via Tilelink, generate a top-level ``gcd_busy`` port, and connect that to the module as well. Traits let us do this without modifying the existing code for the ``DigitalTop``, and enables compartmentalization of code for different custom blocks. -Top-level traits specify that the ``Top`` has been parameterized to read some custom key and optionally instantiate and connect a widget defined by that key. Traits **should not** mandate the instantiation of custom logic. In other words, traits should be written with ``CanHave`` semantics, where the default behavior when the key is unset is a no-op. +Top-level traits specify that the ``DigitalTop`` has been parameterized to read some custom key and optionally instantiate and connect a widget defined by that key. Traits **should not** mandate the instantiation of custom logic. In other words, traits should be written with ``CanHave`` semantics, where the default behavior when the key is unset is a no-op. -Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``Top`` being used by Chipyard. +Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``DigitalTop`` being used by Chipyard. -Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``Top`` to instantiate an additional port and concretely connect it to the GCD module. +Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``DigitalTop`` to instantiate an additional port and concretely connect it to the GCD module. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD imp trait -These traits are added to the default ``Top`` in Chipyard. +These traits are added to the default ``DigitalTop`` in Chipyard. -.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop Config Fragments ---------------- diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index f6b429be1d..15ed5a00fb 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -87,21 +87,21 @@ For peripherals which instantiate a concrete module, or which need to be connect :start-after: DOC include start: GCD imp trait :end-before: DOC include end: GCD imp trait -Constructing the Top and Config -------------------------------- +Constructing the DigitalTop and Config +-------------------------------------- Now we want to mix our traits into the system as a whole. -This code is from ``generators/chipyard/src/main/scala/Top.scala``. +This code is from ``generators/chipyard/src/main/scala/DigitalTop.scala``. -.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop Just as we need separate traits for ``LazyModule`` and module implementation, we need two classes to build the system. -The ``Top`` class contains the set of traits which parameterize and define the ``Top``. Typically these traits will optionally add IOs or peripherals to the ``Top``. -The ``Top`` class includes the pre-elaboration code and also a ``lazy val`` to produce the module implementation (hence ``LazyModule``). -The ``TopModule`` class is the actual RTL that gets synthesized. +The ``DigitalTop`` class contains the set of traits which parameterize and define the ``DigitalTop``. Typically these traits will optionally add IOs or peripherals to the ``DigitalTop``. +The ``DigitalTop`` class includes the pre-elaboration code and also a ``lazy val`` to produce the module implementation (hence ``LazyModule``). +The ``DigitalTopModule`` class is the actual RTL that gets synthesized. diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala new file mode 100644 index 0000000000..328891a8c3 --- /dev/null +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -0,0 +1,102 @@ +package chipyard + +import chisel3._ + +import scala.collection.mutable.{ArrayBuffer} + +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.util.{ResetCatchAndSync} +import chipyard.config.ConfigValName._ +import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple} + +import barstools.iocell.chisel._ + +case object BuildSystem extends Field[Parameters => RawModule]((p: Parameters) => Module(LazyModule(new DigitalTop()(p)).suggestName("system").module)) + +/** + * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter, + * named "system", which is an instance of DigitalTop by default. The default clock and reset for "system" are set by two + * wires, "systemClock" and "systemReset", which are intended to be driven by traits mixed-in with this base class. + */ +abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with HasTestHarnessFunctions { + + // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) + val iocells = ArrayBuffer.empty[IOCell] + // A list of functions to call in the test harness + val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction] + // The system clock + val systemClock = Wire(Input(Clock())) + // The system reset (synchronous to clock) + val systemReset = Wire(Input(Bool())) + + // The system module specified by BuildSystem + val system = withClockAndReset(systemClock, systemReset) { p(BuildSystem)(p) } + + // Call all of the IOBinders and provide them with a default clock and reset + withClockAndReset(systemClock, systemReset) { + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.map(_(system)).flatten.unzip3 + // We ignore _ports for now... + iocells ++= _iocells.flatten + harnessFunctions ++= _harnessFunctions.flatten + } + +} + +/** + * A simple clock and reset implementation that punches out clock and reset ports with the same + * names as the implicit clock and reset for standard Module classes. Reset is synchronous to + * clock, which may not be a good idea to use for tapeouts. + */ +trait HasChipTopSimpleClockAndReset { this: BaseChipTop => + + val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) + val (reset, systemResetIO) = IOCell.generateIOFromSignal(systemReset, Some("iocell_reset")) + + iocells ++= systemClockIO + iocells ++= systemResetIO + + // Add a TestHarnessFunction that connects clock and reset + harnessFunctions += { (th: TestHarness) => { + // Connect clock; it's not done implicitly with RawModule + clock := th.clock + // Connect reset; it's not done implicitly with RawModule + // Note that we need to use dutReset, not harnessReset + reset := th.dutReset + Nil + } } + +} + +/** + * Variant of HasChipTopSimpleClockAndReset that adds a reset synchronizer so that the top-level reset + * can be asynchronous with clock, which is useful for tapeout configs. + */ +trait HasChipTopSimpleClockAndCaughtReset { this: BaseChipTop => + + val asyncResetCore = Wire(Input(Bool())) + systemReset := ResetCatchAndSync(systemClock, asyncResetCore) + + val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) + val (areset, asyncResetIO) = IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_areset")) + + iocells ++= systemClockIO + iocells ++= asyncResetIO + + // Add a TestHarnessFunction that connects clock and areset + harnessFunctions += { (th: TestHarness) => { + // Connect clock; it's not done implicitly with RawModule + clock := th.clock + // Connect reset; it's not done implicitly with RawModule + // Note that we need to use dutReset, not harnessReset + areset := th.dutReset + Nil + } } + +} + +class ChipTop()(implicit p: Parameters) extends BaseChipTop()(p) + with HasChipTopSimpleClockAndReset + +class ChipTopCaughtReset()(implicit p: Parameters) extends BaseChipTop()(p) + with HasChipTopSimpleClockAndCaughtReset diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index dae6e055b8..495c3367ff 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import chipyard.{BuildTop} +import chipyard.{BuildTop, BuildSystem, ChipTopCaughtReset} /** * TODO: Why do we need this? @@ -65,8 +65,8 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => { )) }) -class WithTracegenTop extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) +class WithTracegenSystem extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) }) @@ -150,3 +150,13 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) + + +/** + * Config fragment to use ChipTopCaughtReset as the top module, which adds a reset synchronizer to + * the top-level reset, allowing it to be asynchronous with the clock. + * NOTE: You must remember to set TOP=WithChipTopCaughtReset when building with this config + */ +class WithChipTopCaughtReset extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(new ChipTopCaughtReset()(p).suggestName("top")) +}) diff --git a/generators/chipyard/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/DigitalTop.scala similarity index 86% rename from generators/chipyard/src/main/scala/Top.scala rename to generators/chipyard/src/main/scala/DigitalTop.scala index d81d779a6f..c7b3d49733 100644 --- a/generators/chipyard/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -11,8 +11,8 @@ import freechips.rocketchip.devices.tilelink._ // BOOM and/or Rocket Top Level Systems // ------------------------------------ -// DOC include start: Top -class Top(implicit p: Parameters) extends System +// DOC include start: DigitalTop +class DigitalTop(implicit p: Parameters) extends System with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -23,10 +23,10 @@ class Top(implicit p: Parameters) extends System with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget { - override lazy val module = new TopModule(this) + override lazy val module = new DigitalTopModule(this) } -class TopModule[+L <: Top](l: L) extends SystemModule(l) +class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l) with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp @@ -35,4 +35,4 @@ class TopModule[+L <: Top](l: L) extends SystemModule(l) with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch -// DOC include end: Top +// DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 938ecc5fca..6388c3db5d 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -1,19 +1,22 @@ -package chipyard.iobinders +package chipyard +package object iobinders { import chisel3._ +import chisel3.experimental.{Analog, IO} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ +import barstools.iocell.chisel._ + import testchipip._ -import icenet._ +import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey} import tracegen.{HasTraceGenTilesModuleImp} import scala.reflect.{ClassTag} @@ -26,23 +29,32 @@ import scala.reflect.{ClassTag} // IO connection behavior for tops matching that trait. We use strings to enable // composition and overriding of IOBinders, much like how normal Keys in the config // system are used/ At elaboration, the testharness traverses this set of functions, -// and functions which match the type of the Top are evaluated. +// and functions which match the type of the DigitalTop are evaluated. // You can add your own binder by adding a new (key, fn) pair, typically by using // the OverrideIOBinder or ComposeIOBinder macros + // DOC include start: IOBinders -case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]]( - Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]().withDefaultValue((c: Clock, r: Bool, s: Bool, t: Any) => Nil) +// This type describes a function callable on the TestHarness instance. Its return type is unused. +type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any] +// IOBinders will return a Seq of this tuple, which contains three fields: +// 1. A Seq containing all IO ports created by the IOBinder function +// 2. A Seq containing all IO cell modules created by the IOBinder function +// 3. An optional function to call inside the test harness (e.g. to connect the IOs) +type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction]) + +case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]]( + Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil) ) // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + ((t: Any) => { t match { - case top: T => fn(clock, reset, success, top) + case system: T => fn(system) case _ => Nil } }) @@ -51,12 +63,12 @@ class OverrideIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit ta // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + ((t: Any) => { t match { - case top: T => (up(IOBinders, site)(tag.runtimeClass.toString)(clock, reset, success, top) - ++ fn(clock, reset, success, top)) + case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system) + ++ fn(system)) case _ => Nil } }) @@ -65,74 +77,146 @@ class ComposeIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag // DOC include end: IOBinders +object AddIOCells { + /** + * Add IO cells to a SiFive GPIO devices and name the IO ports. + * @param gpios A Seq of GPIO port bundles + * @param genFn A callable function to generate a DigitalGPIOCell module to use + * @return Returns a tuple of (a 2D Seq of Analog IOs corresponding to individual GPIO pins; a 2D Seq of IOCell module references) + */ + def gpio(gpios: Seq[GPIOPortIO], genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[Seq[Analog]], Seq[Seq[IOCell]]) = { + gpios.zipWithIndex.map({ case (gpio, i) => + gpio.pins.zipWithIndex.map({ case (pin, j) => + val g = IO(Analog(1.W)) + g.suggestName("gpio_${i}_${j}") + val iocell = genFn() + iocell.suggestName(s"iocell_gpio_${i}_${j}") + iocell.io.o := pin.o.oval + iocell.io.oe := pin.o.oe + iocell.io.ie := pin.o.ie + pin.i.ival := iocell.io.i + iocell.io.pad <> g + (g, iocell) + }).unzip + }).unzip + } + + /** + * Add IO cells to a SiFive UART devices and name the IO ports. + * @param gpios A Seq of UART port bundles + * @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references) + */ + def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = { + uartPins.zipWithIndex.map({ case (u, i) => + val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}")) + port.suggestName(s"uart_${i}") + (port, ios) + }).unzip + } + + /** + * Add IO cells to a debug module and name the IO ports. + * @param gpios A PSDIO bundle + * @param debugOpt An optional DebugIO bundle + * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references) + */ + def debug(psd: PSDIO, debugOpt: Option[DebugIO]): (PSDIO, Option[DebugIO], Seq[IOCell]) = { + val (psdPort, psdIOs) = IOCell.generateIOFromSignal(psd, Some("iocell_psd")) + val optTuple = debugOpt.map(d => IOCell.generateIOFromSignal(d, Some("iocell_debug"))) + val debugPortOpt: Option[DebugIO] = optTuple.map(_._1) + val debugIOs: Seq[IOCell] = optTuple.map(_._2).toSeq.flatten + debugPortOpt.foreach(_.suggestName("debug")) + psdPort.suggestName("psd") + (psdPort, debugPortOpt, psdIOs ++ debugIOs) + } + + /** + * Add IO cells to a serial module and name the IO ports. + * @param serial A SerialIO bundle + * @return Returns a tuple of (Top-level SerialIO IO; a list of IOCell module references) + */ + def serial(serial: SerialIO): (SerialIO, Seq[IOCell]) = { + val (port, ios) = IOCell.generateIOFromSignal(serial, Some("iocell_serial")) + port.suggestName("serial") + (port, ios) + } +} + +// DOC include start: WithGPIOTiedOff class WithGPIOTiedOff extends OverrideIOBinder({ - (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil + (system: HasPeripheryGPIOModuleImp) => { + val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) + val harnessFn = (th: chipyard.TestHarness) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } + Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) + } +}) +// DOC include end: WithGPIOTiedOff + +class WithUARTAdapter extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + val (ports, ioCells2d) = AddIOCells.uart(system.uart) + val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports)(system.p); Nil } + Seq((ports, ioCells2d.flatten, Some(harnessFn))) + } }) class WithSimBlockDevice extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectSimBlockDevice(c, r); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectSimBlockDevice(system.clock, system.reset.asBool); Nil }) class WithBlockDeviceModel extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectBlockDeviceModel(); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectBlockDeviceModel(); Nil }) class WithLoopbackNIC extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectNicLoopback(); Nil + (system: CanHavePeripheryIceNICModuleImp) => system.connectNicLoopback(); Nil }) class WithSimNIC extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectSimNetwork(c, r); Nil -}) - -class WithUARTAdapter extends OverrideIOBinder({ - (c, r, s, top: HasPeripheryUARTModuleImp) => { - val defaultBaudRate = 115200 // matches sifive-blocks uart baudrate - top.uart.zipWithIndex.foreach{ case (dut_io, i) => - val uart_sim = Module(new UARTAdapter(i, defaultBaudRate)(top.p)) - uart_sim.io.uart.txd := dut_io.txd - dut_io.rxd := uart_sim.io.uart.rxd - } - Nil - } + (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil }) // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (c, r, s, top: CanHaveMasterAXI4MemPortModuleImp) => top.connectSimAXIMem(); Nil + (system: CanHaveMasterAXI4MemPortModuleImp) => system.connectSimAXIMem(); Nil }) // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ - (clock, reset, _, top: CanHaveMasterAXI4MemPortModuleImp) => { - (top.mem_axi4 zip top.outer.memAXI4Node).foreach { case (io, node) => - val memSize = top.p(ExtMem).get.master.size - val lineSize = top.p(CacheBlockBytes) + (system: CanHaveMasterAXI4MemPortModuleImp) => { + (system.mem_axi4 zip system.outer.memAXI4Node).foreach { case (io, node) => + val memSize = system.p(ExtMem).get.master.size + val lineSize = system.p(CacheBlockBytes) (io zip node.in).foreach { case (axi4, (_, edge)) => val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) mem.io.axi <> axi4 - mem.io.clock := clock - mem.io.reset := reset + mem.io.clock := system.clock + mem.io.reset := system.reset } }; Nil } }) class WithSimAXIMMIO extends OverrideIOBinder({ - (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil + (system: CanHaveMasterAXI4MMIOPortModuleImp) => system.connectSimAXIMMIO(); Nil }) class WithDontTouchPorts extends OverrideIOBinder({ - (c, r, s, top: DontTouch) => top.dontTouchPorts(); Nil + (system: DontTouch) => system.dontTouchPorts(); Nil }) class WithTieOffInterrupts extends OverrideIOBinder({ - (c, r, s, top: HasExtInterruptsBundle) => top.tieOffInterrupts(); Nil + (system: HasExtInterruptsModuleImp) => { + val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) + port.suggestName("interrupts") + val harnessFn = (th: chipyard.TestHarness) => { port := 0.U; Nil } + Seq((Seq(port), ioCells, Some(harnessFn))) + } }) class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (c, r, s, top: CanHaveSlaveAXI4PortModuleImp) => { - top.l2_frontend_bus_axi4.foreach(axi => { + (system: CanHaveSlaveAXI4PortModuleImp) => { + system.l2_frontend_bus_axi4.foreach(axi => { axi.tieoff() experimental.DataMirror.directionOf(axi.ar.ready) match { case ActualDirection.Input => @@ -142,6 +226,7 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ axi.aw.bits := DontCare axi.ar.bits := DontCare axi.w.bits := DontCare + case _ => throw new Exception("Unknown AXI port direction") } }) Nil @@ -149,38 +234,62 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ }) class WithTiedOffDebug extends OverrideIOBinder({ - (c, r, s, top: HasPeripheryDebugModuleImp) => { - Debug.tieoffDebug(top.debug, top.psd) - // tieoffDebug doesn't actually tie everything off :/ - top.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) - Nil + (system: HasPeripheryDebugModuleImp) => { + val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug) + val harnessFn = (th: chipyard.TestHarness) => { + Debug.tieoffDebug(debugPortOpt, psdPort) + // tieoffDebug doesn't actually tie everything off :/ + debugPortOpt.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + Nil + } + Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn))) } }) -class WithSimSerial extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripherySerialModuleImp) => { - val ser_success = top.connectSimSerial() - when (ser_success) { s := true.B } - Nil +class WithSimDebug extends OverrideIOBinder({ + (system: HasPeripheryDebugModuleImp) => { + val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug) + val harnessFn = (th: chipyard.TestHarness) => { + val dtm_success = Wire(Bool()) + Debug.connectDebug(debugPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p) + when (dtm_success) { th.success := true.B } + th.dutReset := th.harnessReset | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B) + Nil + } + Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn))) } }) class WithTiedOffSerial extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripherySerialModuleImp) => top.tieoffSerial(); Nil + (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => + val (port, ioCells) = AddIOCells.serial(serial) + val harnessFn = (th: chipyard.TestHarness) => { + SerialAdapter.tieoff(port) + Nil + } + Seq((Seq(port), ioCells, Some(harnessFn))) + }).getOrElse(Nil) }) - -class WithSimDebug extends OverrideIOBinder({ - (c, r, s, top: HasPeripheryDebugModuleImp) => { - val dtm_success = Wire(Bool()) - top.reset := r | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) - Debug.connectDebug(top.debug, top.psd, c, r, dtm_success)(top.p) - when (dtm_success) { s := true.B } - Nil - } +class WithSimSerial extends OverrideIOBinder({ + (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => + val (port, ioCells) = AddIOCells.serial(serial) + val harnessFn = (th: chipyard.TestHarness) => { + val ser_success = SerialAdapter.connectSimSerial(port, th.clock, th.harnessReset) + when (ser_success) { th.success := true.B } + Nil + } + Seq((Seq(port), ioCells, Some(harnessFn))) + }).getOrElse(Nil) }) - class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (c, r, s, top: HasTraceGenTilesModuleImp) => when (top.success) { s := true.B }; Nil + (system: HasTraceGenTilesModuleImp) => { + val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) + successPort.suggestName("success") + val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } + Seq((Seq(successPort), ioCells, Some(harnessFn))) + } }) + +} diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index ca861288bb..4aaef747c3 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -1,23 +1,21 @@ package chipyard import chisel3._ -import chisel3.experimental._ -import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} - -import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.util.GeneratorApp -import freechips.rocketchip.devices.debug.{Debug} - +import chipyard.iobinders.{TestHarnessFunction} import chipyard.config.ConfigValName._ -import chipyard.iobinders.{IOBinders} // ------------------------------- // BOOM and/or Rocket Test Harness // ------------------------------- -case object BuildTop extends Field[Parameters => Any]((p: Parameters) => Module(LazyModule(new Top()(p)).suggestName("top").module)) +case object BuildTop extends Field[Parameters => HasTestHarnessFunctions]((p: Parameters) => Module(new ChipTop()(p))) + +trait HasTestHarnessFunctions { + val harnessFunctions: Seq[TestHarnessFunction] +} class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { @@ -26,5 +24,15 @@ class TestHarness(implicit val p: Parameters) extends Module { val dut = p(BuildTop)(p) io.success := false.B - p(IOBinders).values.map(fn => fn(clock, reset.asBool, io.success, dut)) + + // dutReset can be overridden via a harnessFunction, but by default it is just reset + val dutReset = Wire(Bool()) + dutReset := reset + + dut.harnessFunctions.foreach(_(this)) + + def success = io.success + def harnessReset = this.reset.asBool + } + diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index ead38869f7..fefa271dcf 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -6,21 +6,21 @@ import freechips.rocketchip.rocket.{DCacheParams} class TraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.system.BaseConfig) class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.system.BaseConfig) @@ -28,7 +28,7 @@ class BoomTraceGenConfig extends Config( class NonBlockingTraceGenL2Config extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.system.BaseConfig) @@ -36,7 +36,7 @@ class NonBlockingTraceGenL2Config extends Config( class NonBlockingTraceGenL2RingConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index ebd12d1b9d..ae6c82fa93 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -7,10 +7,11 @@ import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} +import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp} import icenet.CanHavePeripheryIceNICModuleImp @@ -29,56 +30,55 @@ import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} import chipyard.HasChipyardTilesModuleImp class WithSerialBridge extends OverrideIOBinder({ - (c, r, s, target: CanHavePeripherySerialModuleImp) => - target.serial.map(s => SerialBridge(target.clock, s)(target.p)).toSeq + (system: CanHavePeripherySerialModuleImp) => + system.serial.foreach(s => SerialBridge(system.clock, s)(system.p)); Nil }) class WithNICBridge extends OverrideIOBinder({ - (c, r, s, target: CanHavePeripheryIceNICModuleImp) => - target.net.map(n => NICBridge(target.clock, n)(target.p)).toSeq + (system: CanHavePeripheryIceNICModuleImp) => + system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil }) class WithUARTBridge extends OverrideIOBinder({ - (c, r, s, target: HasPeripheryUARTModuleImp) => - target.uart.map(u => UARTBridge(target.clock, u)(target.p)).toSeq + (system: HasPeripheryUARTModuleImp) => + system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil }) class WithBlockDeviceBridge extends OverrideIOBinder({ - (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => - target.bdev.map(b => BlockDevBridge(target.clock, b, target.reset.toBool)(target.p)).toSeq + (system: CanHavePeripheryBlockDeviceModuleImp) => + system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil }) class WithFASEDBridge extends OverrideIOBinder({ - (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { - implicit val p = t.p - (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => + (system: CanHaveMasterAXI4MemPortModuleImp) => { + implicit val p = system.p + (system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) => (io zip node.in).map({ case (axi4Bundle, (_, edge)) => val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - FASEDBridge(t.clock, axi4Bundle, t.reset.toBool, + FASEDBridge(system.clock, axi4Bundle, system.reset.toBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) - }).toSeq + }) + Nil } }) class WithTracerVBridge extends OverrideIOBinder({ - (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO match { - case Some(t) => t.traces.map(tileTrace => TracerVBridge(tileTrace)(target.p)) - case None => Nil - } + (system: CanHaveTraceIOModuleImp) => + system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil }) class WithTraceGenBridge extends OverrideIOBinder({ - (c, r, s, target: HasTraceGenTilesModuleImp) => - Seq(GroundTestBridge(target.clock, target.success)(target.p)) + (system: HasTraceGenTilesModuleImp) => + GroundTestBridge(system.clock, system.success)(system.p); Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (c, r, s, target: HasChipyardTilesModuleImp) => { - target.outer.tiles.map { + (system: HasChipyardTilesModuleImp) => { + system.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) @@ -100,13 +100,31 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ } }) +class WithTiedOffSystemGPIO extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp) => + system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil +}) + +class WithTiedOffSystemDebug extends OverrideIOBinder({ + (system: HasPeripheryDebugModuleImp) => { + Debug.tieoffDebug(system.debug, system.psd) + // tieoffDebug doesn't actually tie everything off :/ + system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + Nil + } +}) + +class WithTiedOffSystemInterrupts extends OverrideIOBinder({ + (system: HasExtInterruptsModuleImp) => + system.interrupts := 0.U; Nil +}) // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( - new chipyard.iobinders.WithGPIOTiedOff ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithTieOffInterrupts ++ + new WithTiedOffSystemGPIO ++ + new WithTiedOffSystemDebug ++ + new WithTiedOffSystemInterrupts ++ new WithSerialBridge ++ new WithNICBridge ++ new WithUARTBridge ++ diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 221548c331..157b89071d 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule} import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge} -import chipyard.{BuildTop} +import chipyard.{BuildSystem} import chipyard.iobinders.{IOBinders} // Determines the number of times to instantiate the DUT in the harness. @@ -26,14 +26,14 @@ class FireSim(implicit val p: Parameters) extends RawModule { val reset = WireInit(false.B) withClockAndReset(clock, reset) { // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) + val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p)) val peekPokeBridge = PeekPokeBridge(clock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance for ((target) <- targets) { - p(IOBinders).values.map(fn => fn(clock, reset.asBool, false.B, target)) + p(IOBinders).values.map(_(target)) } } } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index 318e3547a6..b16f99c78b 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -14,7 +14,7 @@ import boom.common.{BoomTilesKey, BoomCrossingKey} import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} import firesim.configs._ -import chipyard.{BuildTop, Top, TopModule} +import chipyard.{BuildSystem, DigitalTop, DigitalTopModule} import chipyard.config.ConfigValName._ import chipyard.iobinders.{IOBinders} @@ -64,7 +64,7 @@ class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config class HalfRateUncore extends WithSingleRationalTileDomain(2,1) class WithFiresimMulticlockTop extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("Top").module) + case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module) }) // Complete Config @@ -74,12 +74,12 @@ class FireSimQuadRocketMulticlockConfig extends Config( new FireSimQuadRocketConfig) // Top Definition -class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.Top +class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop { override lazy val module = new FiresimMulticlockTopModule(this) } -class FiresimMulticlockTopModule[+L <: Top](l: L) extends chipyard.TopModule(l) with HasFireSimClockingImp +class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp // Harness Definition class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { @@ -88,14 +88,14 @@ class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { val reset = WireInit(false.B) withClockAndReset(refClock, reset) { // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) + val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p)) val peekPokeBridge = PeekPokeBridge(refClock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance for ((target) <- targets) { - p(IOBinders).values.map(fn => fn(refClock, reset.asBool, false.B, target)) + p(IOBinders).values.map(_(target)) } targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks }) } diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 1f9791ee67..04d9a8f675 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -24,7 +24,6 @@ import testchipip.WithRingSystemBus import firesim.bridges._ import firesim.configs._ -import chipyard.{BuildTop} import chipyard.config.ConfigValName._ class WithBootROM extends Config((site, here, up) => { diff --git a/generators/icenet b/generators/icenet index f227228474..b1f957e6eb 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit f22722847444ecfcd5369f1b33547727d051b834 +Subproject commit b1f957e6eb022c662f0fb33c7ddfbddc686bfde5 diff --git a/generators/testchipip b/generators/testchipip index 30d44252e8..d06d7c7dc2 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 30d44252e8a990da38f1fed6ac6c810fb42dae28 +Subproject commit d06d7c7dc274420a5fc5600ba8bdb2003cc9b0cd diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 422c59c886..6f20a3cecf 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -5,7 +5,7 @@ index a633066..3df8b74 100644 @@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches gemmini, icenet, tracegen, ariane) diff --git a/tools/barstools b/tools/barstools index 63d74bc177..db6776367c 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 63d74bc177cb070126eb0e662ff0ea500722a8d7 +Subproject commit db6776367c7a8f4850266d72f81cd4c90561731a diff --git a/variables.mk b/variables.mk index 5692296bcb..4953c96800 100644 --- a/variables.mk +++ b/variables.mk @@ -36,7 +36,7 @@ ifeq ($(SUB_PROJECT),chipyard) CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= Top + TOP ?= ChipTop endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) From ea8b3487dc6e7e67677e5c8211fce336516b0bea Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 1 Apr 2020 22:25:48 -0700 Subject: [PATCH 026/153] [ci-skip] Bump spec2017 marshal workloads --- software/spec2017 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/spec2017 b/software/spec2017 index b864313643..a4333f243c 160000 --- a/software/spec2017 +++ b/software/spec2017 @@ -1 +1 @@ -Subproject commit b86431364360a9e64487e5dec2962c48bafb67ff +Subproject commit a4333f243cef6bfff08bcbb08f3ec467b4c720d0 From ba199879844ccb163203f39b0ead3ec1393157c5 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 1 Dec 2019 22:27:12 -0800 Subject: [PATCH 027/153] [firechip] Label FASED instances with an associated memory region name --- .../src/main/scala/BridgeBinders.scala | 26 ++++++++++++++++--- .../firechip/src/main/scala/FireSim.scala | 11 +++++++- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index ebd12d1b9d..4276890b38 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -28,9 +28,14 @@ import boom.common.{BoomTile} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} import chipyard.HasChipyardTilesModuleImp +object MainMemoryConsts { + val regionNamePrefix = "MainMemory" + def globalName(): String = s"${regionNamePrefix}_${NodeIdx()}" +} + class WithSerialBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripherySerialModuleImp) => - target.serial.map(s => SerialBridge(target.clock, s)(target.p)).toSeq + target.serial.map(s => SerialBridge(target.clock, s, MainMemoryConsts.globalName)(target.p)).toSeq }) class WithNICBridge extends OverrideIOBinder({ @@ -48,7 +53,19 @@ class WithBlockDeviceBridge extends OverrideIOBinder({ target.bdev.map(b => BlockDevBridge(target.clock, b, target.reset.toBool)(target.p)).toSeq }) -class WithFASEDBridge extends OverrideIOBinder({ +// Assign a unique name to each target memory space, consisting of one or more +// memory channels. In the multi-node case, serial widgets can then disambiguate +// each memory region using this string instead of relying on the assumption +// the target has a single memory channel. +object MemoryRegionNames { + var idx = -1 + def getName(): String = { + idx += 1 + s"memory_${idx}" + } +} + +class WithFASEDBridge extends OverrideIOBinder ({ (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => @@ -57,7 +74,10 @@ class WithFASEDBridge extends OverrideIOBinder({ axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) FASEDBridge(t.clock, axi4Bundle, t.reset.toBool, - CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) + CompleteConfig(p(firesim.configs.MemModelKey), + nastiKey, + Some(AXI4EdgeSummary(edge)), + Some(MainMemoryConsts.globalName))) }) }).toSeq } diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 221548c331..0cd8f410fc 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -20,6 +20,14 @@ class WithNumNodes(n: Int) extends Config((pname, site, here) => { case NumNodes => n }) +// Hacky: Set before each node is generated. Ideally we'd give IO binders +// accesses to the the Harness's parameters instance. We could then alter that. +object NodeIdx { + private var idx = 0 + def increment(): Unit = {idx = idx + 1 } + def apply(): Int = idx +} + class FireSim(implicit val p: Parameters) extends RawModule { val clockBridge = Module(new RationalClockBridge) val clock = clockBridge.io.clocks.head @@ -32,8 +40,9 @@ class FireSim(implicit val p: Parameters) extends RawModule { // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance - for ((target) <- targets) { + for (target <- targets) { p(IOBinders).values.map(fn => fn(clock, reset.asBool, false.B, target)) + NodeIdx.increment() } } } From 64d563d493daad928a43f08c716f52ffb411eab6 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 7 Apr 2020 12:04:39 -0700 Subject: [PATCH 028/153] Bump FireSim for Pow2 fix --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index a4f0a18c0a..b1ff973a25 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit a4f0a18c0aa1690a57dd888be6bc48f52fbc074c +Subproject commit b1ff973a2541f58c30d99ed170bd30527c216414 From 87739a9fe3de48227ebd15812322a8724df520fd Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Wed, 8 Apr 2020 21:18:06 -0700 Subject: [PATCH 029/153] toolchains: Bump libgloss for trap handler support --- toolchains/libgloss | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/libgloss b/toolchains/libgloss index 117b9997bf..e0a2cf5a6e 160000 --- a/toolchains/libgloss +++ b/toolchains/libgloss @@ -1 +1 @@ -Subproject commit 117b9997bf46b93687e52f8ea102bd89478de493 +Subproject commit e0a2cf5a6e317d58fd9c9de5c07a00dae8c5ec36 From 543121972dec2bae6df862df1af5de03950581aa Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 10 Apr 2020 22:01:00 +0000 Subject: [PATCH 030/153] Bump FireSIm --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index b1ff973a25..f04c08a713 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b1ff973a2541f58c30d99ed170bd30527c216414 +Subproject commit f04c08a713014d8835331ed8f8c64525c0d5f2e4 From 4ef3b1a5466202338e0e9db0b37a8d04b4c7166a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 10 Apr 2020 22:26:17 +0000 Subject: [PATCH 031/153] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index f04c08a713..7c121894e9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f04c08a713014d8835331ed8f8c64525c0d5f2e4 +Subproject commit 7c121894e97f32b2fdaf719673c2a2f2ecbe5312 From ada8410ab2e14b0ddd02db6552997efea1d7dda2 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 11 Apr 2020 12:52:55 -0700 Subject: [PATCH 032/153] bump esp spike --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 9163c430be..3c930b4031 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 9163c430be06d43dc0ecc43698791fc36cc3402d +Subproject commit 3c930b403140ac0cd1fc5578a21998f6875459c6 From dc01b4da4b3c8b1539135bd181263f0aec074c13 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 13 Apr 2020 16:31:14 -0700 Subject: [PATCH 033/153] add documentation on baremetal tool flow --- docs/Software/Baremetal.rst | 25 +++++++++++++++++++++++++ docs/Software/index.rst | 1 + 2 files changed, 26 insertions(+) create mode 100644 docs/Software/Baremetal.rst diff --git a/docs/Software/Baremetal.rst b/docs/Software/Baremetal.rst new file mode 100644 index 0000000000..2f0961e9ce --- /dev/null +++ b/docs/Software/Baremetal.rst @@ -0,0 +1,25 @@ +.. _baremetal-programs: + +Baremetal RISC-V Programs +========================== + +To build baremetal RISC-V programs to run in simulation, we use the riscv64-unknown-elf cross-compiler and a fork of the libgloss board support package. To build such a program yourself, simply invoke the cross-compiler with the flags "-fno-common -fno-builtin-printf -specs=htif_nano.specs" and the link with the arguments "-static -specs=htif_nano.specs". For instance, if we want to run a "Hello, World" program in baremetal, we could do the following. + +.. code:: c + + #include + + int main(void) + { + printf("Hello, World!\n"); + return 0; + } + +.. code:: bash + + $ riscv64-unknown-elf-gcc -fno-common -fno-builtin-printf -specs=htif_nano.specs -c hello.c + $ riscv64-unknown-elf-gcc -static -specs=htif_nano.specs hello.o -o hello.riscv + $ spike hello.riscv + Hello, World! + +For more examples, look at the `tests/ directory `_ in the chipyard repository. diff --git a/docs/Software/index.rst b/docs/Software/index.rst index e7fe9925f3..04b5a5fd43 100644 --- a/docs/Software/index.rst +++ b/docs/Software/index.rst @@ -19,3 +19,4 @@ challenging to modify. FireMarshal Spike + Baremetal From d198ef06fd951e338c73500513755ae2bbd03c51 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 15 Apr 2020 09:34:45 -0700 Subject: [PATCH 034/153] Hammer bump --- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/hammer b/vlsi/hammer index 493657c1ac..e9232084e7 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 493657c1ac1a6764a592bd013208648ba19d4fbd +Subproject commit e9232084e7682cd263dab9d887d59900b4242379 diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index fdc3ad051a..6715c3deb0 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit fdc3ad051a2c2edae8346730ce7c0f569aaa97b0 +Subproject commit 6715c3deb074a90860fb151564e83e04bbd24e44 From a6d9589ed8fbc22288eeb40503d213af964a1e43 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 15 Apr 2020 13:38:49 -0700 Subject: [PATCH 035/153] [ci] add approval button (#510) --- .circleci/config.yml | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index dc0188592c..5469c56c1a 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -356,20 +356,35 @@ workflows: build-and-test-chipyard-integration: jobs: + - ci-approval: + type: approval + # Make the toolchains - - install-riscv-toolchain + - install-riscv-toolchain: + requires: + - ci-approval - - install-esp-toolchain + - install-esp-toolchain: + requires: + - ci-approval - - install-verilator + - install-verilator: + requires: + - ci-approval - - commit-on-master-check + - commit-on-master-check: + requires: + - ci-approval # Attempt to apply the tutorial patches - - tutorial-setup-check + - tutorial-setup-check: + requires: + - ci-approval # Check that documentation builds - - documentation-check + - documentation-check: + requires: + - ci-approval # Build extra tests - build-extra-tests: From e6ff6874d411351b3477517d050f157d555e8595 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 15 Apr 2020 14:21:12 -0700 Subject: [PATCH 036/153] add link to libgloss-htif README --- docs/Software/Baremetal.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/Software/Baremetal.rst b/docs/Software/Baremetal.rst index 2f0961e9ce..4bfeaef4bc 100644 --- a/docs/Software/Baremetal.rst +++ b/docs/Software/Baremetal.rst @@ -23,3 +23,5 @@ To build baremetal RISC-V programs to run in simulation, we use the riscv64-unkn Hello, World! For more examples, look at the `tests/ directory `_ in the chipyard repository. + +For more information about the libgloss port, take a look at `its README `_. From 24b63c95773ff9d27521ca777284c8e273de5149 Mon Sep 17 00:00:00 2001 From: Tynan McAuley <16469394+tymcauley@users.noreply.github.com> Date: Wed, 15 Apr 2020 20:35:56 -0700 Subject: [PATCH 037/153] Fix bug in verilator Makefile for 'debug' rule (#513) The 'debug' rule is currently cleaning out the non-debug-model directory rather than the debug-model directory. This commit fixes that, and changes both the debug and non-debug rules to use the variables defined for referring to these two model directories. Co-authored-by: Tynan McAuley --- sims/verilator/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 8bd4cd75ee..0ab0016c90 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -116,14 +116,14 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk # build makefile fragment that builds the verilator sim rules ######################################################################################### $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) - rm -rf $(build_dir)/$(long_name) - mkdir -p $(build_dir)/$(long_name) + rm -rf $(model_dir) + mkdir -p $(model_dir) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) - rm -rf $(build_dir)/$(long_name) - mkdir -p $(build_dir)/$(long_name).debug + rm -rf $(model_dir_debug) + mkdir -p $(model_dir_debug) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ From 629a0449d6e18b7ba1ef0541c82873de7b85b909 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 16 Apr 2020 15:43:18 -0700 Subject: [PATCH 038/153] toolchains: Bump libgloss for trap handler fix (#516) --- toolchains/libgloss | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/libgloss b/toolchains/libgloss index e0a2cf5a6e..a88e50f2e1 160000 --- a/toolchains/libgloss +++ b/toolchains/libgloss @@ -1 +1 @@ -Subproject commit e0a2cf5a6e317d58fd9c9de5c07a00dae8c5ec36 +Subproject commit a88e50f2e1b0411e0a7d5e5c29d5b40117560912 From b303cf6e81fe3c12431a019b81c12d1c2cce5056 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 8 Apr 2020 14:47:57 -0700 Subject: [PATCH 039/153] Rocket Chip Stage/Phase Bump (#503) [WIP] Minimally elaborating design Bring up a feature-complete Chipyard stage Pull in Makefrag generation; Bump submodules Update config generation, and global reset scheme Bump submodules; clean up Bump FireSim Remove some unhygenic comments / WS Remove the rocketchip subproject [CI] Lengthen ariane tests timeout Address some remaining reviewer comments [firechip] Refresh a Field that cannot be used across repeated instantiations Bump all submodules --- .circleci/config.yml | 1 + .circleci/defaults.sh | 1 - build.sbt | 1 + common.mk | 6 +- generators/ariane | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/ChipTop.scala | 95 +++++++++++-------- .../src/main/scala/ConfigFragments.scala | 14 +-- .../chipyard/src/main/scala/Generator.scala | 40 +------- .../chipyard/src/main/scala/IOBinders.scala | 68 ++++++++----- .../chipyard/src/main/scala/Subsystem.scala | 16 +--- .../chipyard/src/main/scala/System.scala | 3 - .../chipyard/src/main/scala/TestHarness.scala | 5 +- .../chipyard/src/main/scala/TestSuites.scala | 83 ++++++++-------- .../scala/stage/ChipyardAnnotations.scala | 20 ++++ .../src/main/scala/stage/ChipyardCli.scala | 15 +++ .../src/main/scala/stage/ChipyardStage.scala | 36 +++++++ .../scala/stage/phases/AddDefaultTests.scala | 62 ++++++++++++ .../phases/GenerateTestSuiteMakefrags.scala | 49 ++++++++++ .../src/main/scala/BridgeBinders.scala | 31 +++--- .../firechip/src/main/scala/FireSim.scala | 18 +++- .../src/main/scala/FireSimMulticlockPOC.scala | 13 ++- .../firechip/src/main/scala/Generator.scala | 21 ++-- .../src/main/scala/TargetConfigs.scala | 2 +- .../src/test/scala/ScalaTestSuite.scala | 2 +- generators/hwacha | 2 +- generators/icenet | 2 +- generators/rocket-chip | 2 +- generators/sifive-blocks | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/System.scala | 1 - project/build.properties | 2 +- project/plugins.sbt | 1 + sims/firesim | 2 +- tools/barstools | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- variables.mk | 34 +------ 38 files changed, 406 insertions(+), 256 deletions(-) create mode 100644 generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala create mode 100644 generators/chipyard/src/main/scala/stage/ChipyardCli.scala create mode 100644 generators/chipyard/src/main/scala/stage/ChipyardStage.scala create mode 100644 generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala create mode 100644 generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala diff --git a/.circleci/config.yml b/.circleci/config.yml index dc0188592c..d91e711507 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -338,6 +338,7 @@ jobs: steps: - run-tests: project-key: "chipyard-ariane" + timeout: "30m" # Order and dependencies of jobs to run workflows: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 552ac1dbe5..7d4fdaa3b8 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,6 @@ mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" -mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" diff --git a/build.sbt b/build.sbt index 05f05d7b45..b0e8c84daf 100644 --- a/build.sbt +++ b/build.sbt @@ -166,6 +166,7 @@ lazy val gemmini = (project in file("generators/gemmini")) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) .dependsOn(chisel_testers, chipyard) .settings(commonSettings) + .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) diff --git a/common.mk b/common.mk index a98e0e2486..696e0f8315 100644 --- a/common.mk +++ b/common.mk @@ -58,7 +58,11 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp # AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) - cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" + cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator \ + --target-dir $(build_dir) \ + --name $(long_name) \ + --top-module $(MODEL_PACKAGE).$(MODEL) \ + --legacy-configs $(CONFIG_PACKAGE).$(CONFIG)" .PHONY: firrtl firrtl: $(FIRRTL_FILE) diff --git a/generators/ariane b/generators/ariane index e02436d2aa..621201b1d5 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit e02436d2aaf934b6e58d5e11e87276ba0d840f2a +Subproject commit 621201b1d5a929ab0e89f1a857b76a33e7e2e8a8 diff --git a/generators/boom b/generators/boom index a26504f34d..90911dde1b 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit a26504f34db8327a5d4d9bb3a342dddf79e02b35 +Subproject commit 90911dde1b8730f10c958d172f26f72d718be5ae diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 328891a8c3..d0b4df0228 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -12,7 +12,42 @@ import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple} import barstools.iocell.chisel._ -case object BuildSystem extends Field[Parameters => RawModule]((p: Parameters) => Module(LazyModule(new DigitalTop()(p)).suggestName("system").module)) +case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => LazyModule(new DigitalTop()(p))) + +/** + * Chipyard provides three baseline, top-level reset schemes, set using the + * [[GlobalResetSchemeKey]] in a Parameters instance. These are: + * + * 1) Synchronous: The input coming to the chip is synchronous to the provided + * clocks and will be used without modification as a synchronous reset. + * This is safe only for use in FireSim and SW simulation. + * + * 2) Asynchronous: The input reset is asynchronous to the input clock, but it + * is caught and synchronized to that clock before it is dissemenated. + * Thus, downsteam modules will be emitted with synchronously reset state + * elements. + * + * 3) Asynchronous Full: The input reset is asynchronous to the input clock, + * and is used globally as an async reset. Downstream modules will be emitted + * with asynchronously reset state elements. + * + */ +sealed trait GlobalResetScheme { + def pinIsAsync: Boolean +} +sealed trait HasAsyncInput { self: GlobalResetScheme => + def pinIsAsync = true +} + +sealed trait HasSyncInput { self: GlobalResetScheme => + def pinIsAsync = false +} + +case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput +case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput +case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput +case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous) + /** * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter, @@ -26,16 +61,21 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with // A list of functions to call in the test harness val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction] // The system clock + // These are given so that IOCell can use DataMirror and generate ports with + // the right flow (Input/Output) val systemClock = Wire(Input(Clock())) - // The system reset (synchronous to clock) - val systemReset = Wire(Input(Bool())) + val systemReset = Wire(Input(Reset())) // The system module specified by BuildSystem - val system = withClockAndReset(systemClock, systemReset) { p(BuildSystem)(p) } + val lSystem = p(BuildSystem)(p).suggestName("system") + val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) } // Call all of the IOBinders and provide them with a default clock and reset withClockAndReset(systemClock, systemReset) { - val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.map(_(system)).flatten.unzip3 + // Call each IOBinder on both the lazyModule instance and the module + // instance. Generally, an IOBinder PF should only be defined on one, so + // this should not lead to two invocations. + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3 // We ignore _ports for now... iocells ++= _iocells.flatten harnessFunctions ++= _harnessFunctions.flatten @@ -45,13 +85,22 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with /** * A simple clock and reset implementation that punches out clock and reset ports with the same - * names as the implicit clock and reset for standard Module classes. Reset is synchronous to - * clock, which may not be a good idea to use for tapeouts. + * names as the implicit clock and reset for standard Module classes. Three basic reset schemes + * are provided. See [[GlobalResetScheme]]. */ trait HasChipTopSimpleClockAndReset { this: BaseChipTop => val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) - val (reset, systemResetIO) = IOCell.generateIOFromSignal(systemReset, Some("iocell_reset")) + val (reset, systemResetIO) = p(GlobalResetSchemeKey) match { + case GlobalResetSynchronous => + IOCell.generateIOFromSignal(systemReset, Some("iocell_reset")) + case GlobalResetAsynchronousFull => + IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"), abstractResetAsAsync = true) + case GlobalResetAsynchronous => + val asyncResetCore = Wire(Input(AsyncReset())) + systemReset := ResetCatchAndSync(systemClock, asyncResetCore.asBool) + IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_reset"), abstractResetAsAsync = true) + } iocells ++= systemClockIO iocells ++= systemResetIO @@ -68,35 +117,5 @@ trait HasChipTopSimpleClockAndReset { this: BaseChipTop => } -/** - * Variant of HasChipTopSimpleClockAndReset that adds a reset synchronizer so that the top-level reset - * can be asynchronous with clock, which is useful for tapeout configs. - */ -trait HasChipTopSimpleClockAndCaughtReset { this: BaseChipTop => - - val asyncResetCore = Wire(Input(Bool())) - systemReset := ResetCatchAndSync(systemClock, asyncResetCore) - - val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) - val (areset, asyncResetIO) = IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_areset")) - - iocells ++= systemClockIO - iocells ++= asyncResetIO - - // Add a TestHarnessFunction that connects clock and areset - harnessFunctions += { (th: TestHarness) => { - // Connect clock; it's not done implicitly with RawModule - clock := th.clock - // Connect reset; it's not done implicitly with RawModule - // Note that we need to use dutReset, not harnessReset - areset := th.dutReset - Nil - } } - -} - class ChipTop()(implicit p: Parameters) extends BaseChipTop()(p) with HasChipTopSimpleClockAndReset - -class ChipTopCaughtReset()(implicit p: Parameters) extends BaseChipTop()(p) - with HasChipTopSimpleClockAndCaughtReset diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 495c3367ff..dee1a40aff 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import chipyard.{BuildTop, BuildSystem, ChipTopCaughtReset} +import chipyard.{BuildTop, BuildSystem} /** * TODO: Why do we need this? @@ -66,7 +66,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => { }) class WithTracegenSystem extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) + case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) }) @@ -150,13 +150,3 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) - - -/** - * Config fragment to use ChipTopCaughtReset as the top module, which adds a reset synchronizer to - * the top-level reset, allowing it to be asynchronous with the clock. - * NOTE: You must remember to set TOP=WithChipTopCaughtReset when building with this config - */ -class WithChipTopCaughtReset extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => Module(new ChipTopCaughtReset()(p).suggestName("top")) -}) diff --git a/generators/chipyard/src/main/scala/Generator.scala b/generators/chipyard/src/main/scala/Generator.scala index 4baba35723..d5a53a06fc 100644 --- a/generators/chipyard/src/main/scala/Generator.scala +++ b/generators/chipyard/src/main/scala/Generator.scala @@ -1,40 +1,6 @@ package chipyard -import scala.util.Try +import firrtl.options.{StageMain} +import chipyard.stage.ChipyardStage -import chisel3._ - -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.util.{GeneratorApp} -import freechips.rocketchip.system.{TestGeneration} - -object Generator extends GeneratorApp { - // add unique test suites - override def addTestSuites { - implicit val p: Parameters = params - TestSuiteHelper.addRocketTestSuites - TestSuiteHelper.addBoomTestSuites - TestSuiteHelper.addArianeTestSuites - - // if hwacha parameter exists then generate its tests - // TODO: find a more elegant way to do this. either through - // trying to disambiguate BuildRoCC, having a AccelParamsKey, - // or having the Accelerator/Tile add its own tests - import hwacha.HwachaTestSuites._ - if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) { - TestGeneration.addSuites(rv64uv.map(_("p"))) - TestGeneration.addSuites(rv64uv.map(_("vp"))) - TestGeneration.addSuite(rv64sv("p")) - TestGeneration.addSuite(hwachaBmarks) - } - } - - // specify the name that the generator outputs files as - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - - // generate files - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts -} +object Generator extends StageMain(new ChipyardStage) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 6388c3db5d..e3c79f3a7e 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -8,6 +8,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ @@ -117,17 +118,28 @@ object AddIOCells { /** * Add IO cells to a debug module and name the IO ports. * @param gpios A PSDIO bundle + * @param resetctrlOpt An optional ResetCtrlIO bundle * @param debugOpt An optional DebugIO bundle * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references) */ - def debug(psd: PSDIO, debugOpt: Option[DebugIO]): (PSDIO, Option[DebugIO], Seq[IOCell]) = { - val (psdPort, psdIOs) = IOCell.generateIOFromSignal(psd, Some("iocell_psd")) - val optTuple = debugOpt.map(d => IOCell.generateIOFromSignal(d, Some("iocell_debug"))) - val debugPortOpt: Option[DebugIO] = optTuple.map(_._1) - val debugIOs: Seq[IOCell] = optTuple.map(_._2).toSeq.flatten + def debug(psd: PSDIO, resetctrlOpt: Option[ResetCtrlIO], debugOpt: Option[DebugIO])(implicit p: Parameters): + (PSDIO, Option[ResetCtrlIO], Option[DebugIO], Seq[IOCell]) = { + val (psdPort, psdIOs) = IOCell.generateIOFromSignal( + psd, Some("iocell_psd"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + val debugTuple = debugOpt.map(d => + IOCell.generateIOFromSignal(d, Some("iocell_debug"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)) + val debugPortOpt: Option[DebugIO] = debugTuple.map(_._1) + val debugIOs: Seq[IOCell] = debugTuple.map(_._2).toSeq.flatten debugPortOpt.foreach(_.suggestName("debug")) + + val resetctrlTuple = resetctrlOpt.map(d => + IOCell.generateIOFromSignal(d, Some("iocell_resetctrl"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)) + val resetctrlPortOpt: Option[ResetCtrlIO] = resetctrlTuple.map(_._1) + val resetctrlIOs: Seq[IOCell] = resetctrlTuple.map(_._2).toSeq.flatten + resetctrlPortOpt.foreach(_.suggestName("resetctrl")) + psdPort.suggestName("psd") - (psdPort, debugPortOpt, psdIOs ++ debugIOs) + (psdPort, resetctrlPortOpt, debugPortOpt, psdIOs ++ debugIOs ++ resetctrlIOs) } /** @@ -176,29 +188,32 @@ class WithSimNIC extends OverrideIOBinder({ (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil }) +// Note: The parameters instance is accessible only through the BaseSubsystem +// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The +// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it +// accessible to the IOBinder // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPortModuleImp) => system.connectSimAXIMem(); Nil + (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => SimAXIMem.connectMem(system)(system.p); Nil }) // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPortModuleImp) => { - (system.mem_axi4 zip system.outer.memAXI4Node).foreach { case (io, node) => + (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { + (system.mem_axi4 zip system.memAXI4Node.in).foreach { case (io, (_, edge)) => val memSize = system.p(ExtMem).get.master.size val lineSize = system.p(CacheBlockBytes) - (io zip node.in).foreach { case (axi4, (_, edge)) => - val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) - mem.io.axi <> axi4 - mem.io.clock := system.clock - mem.io.reset := system.reset - } - }; Nil + val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) + mem.io.axi <> io + mem.io.clock := system.module.clock + mem.io.reset := system.module.reset + } + Nil } }) class WithSimAXIMMIO extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MMIOPortModuleImp) => system.connectSimAXIMMIO(); Nil + (system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil }) class WithDontTouchPorts extends OverrideIOBinder({ @@ -215,7 +230,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({ }) class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4PortModuleImp) => { + (system: CanHaveSlaveAXI4Port with BaseSubsystem) => { system.l2_frontend_bus_axi4.foreach(axi => { axi.tieoff() experimental.DataMirror.directionOf(axi.ar.ready) match { @@ -235,23 +250,28 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ class WithTiedOffDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { - val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug) + val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = + AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { - Debug.tieoffDebug(debugPortOpt, psdPort) + Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p) // tieoffDebug doesn't actually tie everything off :/ - debugPortOpt.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + debugPortOpt.foreach { d => + d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) + d.dmactiveAck := DontCare + } Nil } - Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn))) + Seq((Seq(psdPort) ++ resetctrlOpt ++ debugPortOpt.toSeq, Nil, Some(harnessFn))) } }) class WithSimDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { - val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug) + val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = + AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { val dtm_success = Wire(Bool()) - Debug.connectDebug(debugPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p) + Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p) when (dtm_success) { th.success := true.B } th.dutReset := th.harnessReset | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B) Nil diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 96443a9f85..8fe0871bcc 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -52,26 +52,20 @@ trait HasChipyardTiles extends HasTiles // TODO: investigate why val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { case (param, crossing) => { - val (tile, rocketLogicalTree) = param match { + + val tile = param match { case r: RocketTileParams => { - val t = LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - (t, t.rocketLogicalTree) + LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) } case b: BoomTileParams => { - val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) - (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately + LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) } case a: ArianeTileParams => { - val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) - (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately + LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) } } connectMasterPortsToSBus(tile, crossing) connectSlavePortsToCBus(tile, crossing) - - def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocketLogicalTree.getOMInterruptTargets) - LogicalModuleTree.add(logicalTreeNode, rocketLogicalTree) - connectInterrupts(tile, debugOpt, clintOpt, plicOpt) tile diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index f18a2068d2..6d99ca6a6a 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -38,8 +38,5 @@ class System(implicit p: Parameters) extends Subsystem class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer) with HasRTCModuleImp with HasExtInterruptsModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with CanHaveMasterAXI4MMIOPortModuleImp - with CanHaveSlaveAXI4PortModuleImp with HasPeripheryBootROMModuleImp with DontTouch diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 4aaef747c3..a82d3a3367 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -25,9 +25,8 @@ class TestHarness(implicit val p: Parameters) extends Module { val dut = p(BuildTop)(p) io.success := false.B - // dutReset can be overridden via a harnessFunction, but by default it is just reset - val dutReset = Wire(Bool()) - dutReset := reset + // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset + val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset) dut.harnessFunctions.foreach(_(this)) diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 7d901c62f4..9fdef05a3f 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -5,8 +5,7 @@ import scala.collection.mutable.{LinkedHashSet} import freechips.rocketchip.subsystem.{RocketTilesKey} import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.util.{GeneratorApp} -import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} +import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} import boom.common.{BoomTilesKey} import ariane.{ArianeTilesKey} @@ -56,10 +55,13 @@ object RegressionTestSuites /** * Helper functions to add BOOM or Rocket tests */ -object TestSuiteHelper +class TestSuiteHelper { import freechips.rocketchip.system.DefaultTestSuites._ import RegressionTestSuites._ + val suites = collection.mutable.ListMap[String, RocketTestSuite]() + def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) } + def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) } /** * Add BOOM tests (asm, bmark, regression) @@ -72,33 +74,33 @@ object TestSuiteHelper val env = if (vm) List("p","v") else List("p") coreParams.fpu foreach { case cfg => if (xlen == 32) { - TestGeneration.addSuites(env.map(rv32uf)) + addSuites(env.map(rv32uf)) if (cfg.fLen >= 64) { - TestGeneration.addSuites(env.map(rv32ud)) + addSuites(env.map(rv32ud)) } } else if (cfg.fLen >= 64) { - TestGeneration.addSuites(env.map(rv64ud)) - TestGeneration.addSuites(env.map(rv64uf)) - TestGeneration.addSuite(rv32udBenchmarks) + addSuites(env.map(rv64ud)) + addSuites(env.map(rv64uf)) + addSuite(rv32udBenchmarks) } } if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty) { - TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) } else { - TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) } } - if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u) - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites(rvu.map(_("p"))) - TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) - TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites(rvu.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) } } @@ -113,31 +115,31 @@ object TestSuiteHelper val env = if (vm) List("p","v") else List("p") coreParams.fpu foreach { case cfg => if (xlen == 32) { - TestGeneration.addSuites(env.map(rv32uf)) + addSuites(env.map(rv32uf)) if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv32ud)) + addSuites(env.map(rv32ud)) } else { - TestGeneration.addSuite(rv32udBenchmarks) - TestGeneration.addSuites(env.map(rv64uf)) + addSuite(rv32udBenchmarks) + addSuites(env.map(rv64uf)) if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv64ud)) + addSuites(env.map(rv64ud)) } } if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty) - TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) else - TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) } - if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u) - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) - TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) } } @@ -152,32 +154,31 @@ object TestSuiteHelper val env = if (vm) List("p","v") else List("p") coreParams.fpu foreach { case cfg => if (xlen == 32) { - TestGeneration.addSuites(env.map(rv32uf)) + addSuites(env.map(rv32uf)) if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv32ud)) + addSuites(env.map(rv32ud)) } else { - TestGeneration.addSuite(rv32udBenchmarks) - TestGeneration.addSuites(env.map(rv64uf)) + addSuite(rv32udBenchmarks) + addSuites(env.map(rv64uf)) if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv64ud)) + addSuites(env.map(rv64ud)) } } if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty) - TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) else - TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) } - if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u) - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) - TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) } } - } diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala new file mode 100644 index 0000000000..dfee15961c --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -0,0 +1,20 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import freechips.rocketchip.stage.ConfigsAnnotation +import firrtl.options.{HasShellOptions, ShellOption} + +/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format */ +private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[String]( + longOption = "legacy-configs", + toAnnotationSeq = a => Seq(new ConfigsAnnotation(a.split("_"))), + helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).", + shortOption = Some("LC") + ) + ) +} + diff --git a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala new file mode 100644 index 0000000000..7d293c36e8 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala @@ -0,0 +1,15 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import firrtl.options.Shell + +trait ChipyardCli { this: Shell => + + parser.note("Chipyard Generator Options") + Seq( + UnderscoreDelimitedConfigsAnnotation + ) + .foreach(_.addOptions(parser)) +} diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala new file mode 100644 index 0000000000..a24afd43bf --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -0,0 +1,36 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import chisel3.stage.{ChiselCli, ChiselStage} +import firrtl.options.PhaseManager.PhaseDependency +import firrtl.options.{Phase, PreservesAll, Shell} +import firrtl.stage.FirrtlCli +import freechips.rocketchip.stage.RocketChipCli +import freechips.rocketchip.system.RocketChipStage + +import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain} +import firrtl.options.phases.DeletedWrapper + +class ChipyardStage extends ChiselStage with PreservesAll[Phase] { + override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli + override val targets: Seq[PhaseDependency] = Seq( + classOf[freechips.rocketchip.stage.phases.Checks], + classOf[freechips.rocketchip.stage.phases.TransformAnnotations], + classOf[freechips.rocketchip.stage.phases.PreElaboration], + classOf[chisel3.stage.phases.Checks], + classOf[chisel3.stage.phases.Elaborate], + classOf[freechips.rocketchip.stage.phases.GenerateROMs], + classOf[chisel3.stage.phases.AddImplicitOutputFile], + classOf[chisel3.stage.phases.AddImplicitOutputAnnotationFile], + classOf[chisel3.stage.phases.MaybeAspectPhase], + classOf[chisel3.stage.phases.Emitter], + classOf[chisel3.stage.phases.Convert], + classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + classOf[freechips.rocketchip.stage.phases.AddDefaultTests], + classOf[chipyard.stage.phases.AddDefaultTests], + classOf[chipyard.stage.phases.GenerateTestSuiteMakefrags], + classOf[freechips.rocketchip.stage.phases.GenerateArtefacts], + ) +} diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala new file mode 100644 index 0000000000..277d04b532 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -0,0 +1,62 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage.phases + +import scala.util.Try +import scala.collection.mutable + +import chipsalliance.rocketchip.config.Parameters +import chisel3.stage.phases.Elaborate +import firrtl.AnnotationSeq +import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options.{Phase, PreservesAll} +import firrtl.options.Viewer.view +import freechips.rocketchip.stage.RocketChipOptions +import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} +import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} +import freechips.rocketchip.util.HasRocketChipStageUtils + +import chipyard.TestSuiteHelper + +class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { + // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase + // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). + override val prerequisites = Seq( + classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + classOf[freechips.rocketchip.stage.phases.AddDefaultTests]) + override val dependents = Seq(classOf[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) + + private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { + val annotations = mutable.ArrayBuffer[Annotation]() + val suiteHelper = new TestSuiteHelper + suiteHelper.addRocketTestSuites + suiteHelper.addBoomTestSuites + suiteHelper.addArianeTestSuites + + // if hwacha parameter exists then generate its tests + // TODO: find a more elegant way to do this. either through + // trying to disambiguate BuildRoCC, having a AccelParamsKey, + // or having the Accelerator/Tile add its own tests + import hwacha.HwachaTestSuites._ + if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) { + suiteHelper.addSuites(rv64uv.map(_("p"))) + suiteHelper.addSuites(rv64uv.map(_("vp"))) + suiteHelper.addSuite(rv64sv("p")) + suiteHelper.addSuite(hwachaBmarks) + annotations += CustomMakefragSnippet( + "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha") + } + RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations + } + + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val (testSuiteAnnos, oAnnos) = annotations.partition { + case RocketTestSuiteAnnotation(_) => true + case o => false + } + implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance + addTestSuiteAnnotations ++ oAnnos + } +} diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala new file mode 100644 index 0000000000..76f99ab774 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -0,0 +1,49 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage.phases + +import scala.collection.mutable + +import firrtl.AnnotationSeq +import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable} +import firrtl.options.Viewer.view +import freechips.rocketchip.stage.RocketChipOptions +import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} +import freechips.rocketchip.system.TestGeneration +import freechips.rocketchip.util.HasRocketChipStageUtils + +trait MakefragSnippet { self: Annotation => + def toMakefrag: String +} + +case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable + +/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */ +class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { + + // Our annotations tend not to be serializable, but are not marked as such. + override val prerequisites = Seq(classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + classOf[chipyard.stage.phases.AddDefaultTests]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir = view[StageOptions](annotations).targetDir + val fileName = s"${view[RocketChipOptions](annotations).longName.get}.d" + + val makefragBuilder = new mutable.StringBuilder() + val outputAnnotations = annotations.flatMap { + case RocketTestSuiteAnnotation(tests) => + // Unfortunately the gen method of TestGeneration is rocketchip package + // private, so we either have to copy code in or use the stateful form + TestGeneration.addSuites(tests) + None + case a: MakefragSnippet => + makefragBuilder :+ ("\n" + a.toMakefrag) + None + case a => Some(a) + } + writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString) + outputAnnotations + } +} diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index bd19ee980b..043f1f4ebf 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -8,7 +8,7 @@ import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp} +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} @@ -56,19 +56,17 @@ class WithBlockDeviceBridge extends OverrideIOBinder({ class WithFASEDBridge extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPortModuleImp) => { + (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { implicit val p = system.p - (system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) => - (io zip node.in).map({ case (axi4Bundle, (_, edge)) => - val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, - axi4Bundle.ar.bits.addr.getWidth, - axi4Bundle.ar.bits.id.getWidth) - FASEDBridge(system.clock, axi4Bundle, system.reset.toBool, - CompleteConfig(p(firesim.configs.MemModelKey), - nastiKey, - Some(AXI4EdgeSummary(edge)), - Some(MainMemoryConsts.globalName))) - }) + (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) => + val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, + axi4.ar.bits.addr.getWidth, + axi4.ar.bits.id.getWidth) + FASEDBridge(system.module.clock, axi4, system.module.reset.toBool, + CompleteConfig(p(firesim.configs.MemModelKey), + nastiKey, + Some(AXI4EdgeSummary(edge)), + Some(MainMemoryConsts.globalName))) }) Nil } @@ -116,9 +114,12 @@ class WithTiedOffSystemGPIO extends OverrideIOBinder({ class WithTiedOffSystemDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { - Debug.tieoffDebug(system.debug, system.psd) + Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) // tieoffDebug doesn't actually tie everything off :/ - system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + system.debug.foreach { d => + d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) + d.dmactiveAck := DontCare + } Nil } }) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index fc65f136cf..923e1cd128 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -34,14 +34,24 @@ class FireSim(implicit val p: Parameters) extends RawModule { val reset = WireInit(false.B) withClockAndReset(clock, reset) { // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p)) + val targets = Seq.fill(p(NumNodes)) { + // It's not a RC bump without some hacks... + // Copy the AsyncClockGroupsKey to generate a fresh node on each + // instantiation of the dut, otherwise the initial instance will be + // reused across each node + import freechips.rocketchip.subsystem.AsyncClockGroupsKey + val lazyModule = p(BuildSystem)(p.alterPartial({ + case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy + })) + (lazyModule, Module(lazyModule.module)) + } val peekPokeBridge = PeekPokeBridge(clock, reset) // A Seq of partial functions that will instantiate the right bridge only - // if that Mixin trait is present in the target's class instance + // if that Mixin trait is present in the target's LazyModule class instance // // Apply each partial function to each DUT instance - for ((target) <- targets) { - p(IOBinders).values.map(_(target)) + for ((lazyModule, module) <- targets) { + p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module)) NodeIdx.increment() } } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index b16f99c78b..fdc2939faa 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -64,7 +64,7 @@ class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config class HalfRateUncore extends WithSingleRationalTileDomain(2,1) class WithFiresimMulticlockTop extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module) + case BuildSystem => (p: Parameters) => LazyModule(new FiresimMulticlockTop()(p)).suggestName("system") }) // Complete Config @@ -88,16 +88,19 @@ class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { val reset = WireInit(false.B) withClockAndReset(refClock, reset) { // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p)) + val targets = Seq.fill(p(NumNodes)) { + val lazyModule = p(BuildSystem)(p) + (lazyModule, Module(lazyModule.module)) + } val peekPokeBridge = PeekPokeBridge(refClock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance - for ((target) <- targets) { - p(IOBinders).values.map(_(target)) + for ((lazyModule, module) <- targets) { + p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module)) } - targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks }) + targets.collect({ case (_, t: HasAdditionalClocks) => t.clocks := clockBridge.io.clocks }) } } diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 18aeefc8a0..852b9fbd24 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -9,7 +9,7 @@ import chisel3.internal.firrtl.{Circuit, Port} import freechips.rocketchip.diplomacy.{ValName, AutoBundle} import freechips.rocketchip.devices.debug.DebugIO -import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts} +import midas.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts} import freechips.rocketchip.system.DefaultTestSuites._ import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} import freechips.rocketchip.config.Parameters @@ -24,9 +24,11 @@ import chipyard.TestSuiteHelper trait HasTestSuites { def addTestSuites(targetName: String, params: Parameters) { - TestSuiteHelper.addRocketTestSuites(params) - TestSuiteHelper.addBoomTestSuites(params) - TestSuiteHelper.addArianeTestSuites(params) + val suiteHelper = new TestSuiteHelper + suiteHelper.addRocketTestSuites(params) + suiteHelper.addBoomTestSuites(params) + suiteHelper.addArianeTestSuites(params) + TestGeneration.addSuites(suiteHelper.suites.values.toSeq) TestGeneration.addSuite(FastBlockdevTests) TestGeneration.addSuite(SlowBlockdevTests) if (!targetName.contains("NoNIC")) @@ -47,7 +49,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu /** Output software test Makefrags, which provide targets for integration testing. */ def generateTestSuiteMakefrags { addTestSuites(names.topModuleClass, targetParams) - writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites + writeOutputFile(s"$longName.d", TestGeneration.generateMakeFrag) // Subsystem-specific test suites } // Output miscellaneous files produced as a side-effect of elaboration @@ -68,12 +70,3 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike { generateTestSuiteMakefrags generateArtefacts } - -// For now, provide a separate generator app when not specifically building for FireSim -object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites { - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 04d9a8f675..63199c0efa 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -41,7 +41,7 @@ class WithBootROM extends Config((site, here, up) => { }) class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq) + case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) }) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 83d57e24f4..68797432b7 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -137,7 +137,7 @@ abstract class FireSimTestSuite( } class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") -class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config") +class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } diff --git a/generators/hwacha b/generators/hwacha index ef5e5196b6..2706502daf 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit ef5e5196b685536890396a08a9f5024eb8b7928e +Subproject commit 2706502daf862c9a7a39126eb7e7209eaf984f76 diff --git a/generators/icenet b/generators/icenet index b1f957e6eb..4522a3979b 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit b1f957e6eb022c662f0fb33c7ddfbddc686bfde5 +Subproject commit 4522a3979be092c4221f186bdd93bf330fdca134 diff --git a/generators/rocket-chip b/generators/rocket-chip index 4f0cdea85c..9b1907eacb 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 4f0cdea85c8a2b849fd582ccc8497892001d06b0 +Subproject commit 9b1907eacbeb268d47e204e3de1818823d605ba4 diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 1bc0ef18d6..3e35a94d46 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 1bc0ef18d6653f1133cb9293e8ee8620f9417c78 +Subproject commit 3e35a94d46d88506d5b14b2c34f05b8651844452 diff --git a/generators/testchipip b/generators/testchipip index d06d7c7dc2..b8d6f21019 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit d06d7c7dc274420a5fc5600ba8bdb2003cc9b0cd +Subproject commit b8d6f2101947e9f80f896dbaa5802946e2a3b9f0 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 1830767874..cb5d0af8c5 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -49,4 +49,3 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem class TraceGenSystemModuleImp(outer: TraceGenSystem) extends BaseSubsystemModuleImp(outer) with HasTraceGenTilesModuleImp - with CanHaveMasterAXI4MemPortModuleImp diff --git a/project/build.properties b/project/build.properties index c0bab04941..8522443ded 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.2.8 +sbt.version=1.3.2 diff --git a/project/plugins.sbt b/project/plugins.sbt index 3321d801f2..a30249c996 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -14,5 +14,6 @@ addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6") addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") +addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" diff --git a/sims/firesim b/sims/firesim index 7c121894e9..f82e115c66 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7c121894e97f32b2fdaf719673c2a2f2ecbe5312 +Subproject commit f82e115c6641c5fe33f756abeb8093f64b0d0a80 diff --git a/tools/barstools b/tools/barstools index db6776367c..e230e8cf3f 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit db6776367c7a8f4850266d72f81cd4c90561731a +Subproject commit e230e8cf3f7c0bc3c958cab22c5d90d195ca6b01 diff --git a/tools/chisel3 b/tools/chisel3 index d1a6126263..7a343dce95 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit d1a61262630b5ea77ebe21a453df9645cb7e4185 +Subproject commit 7a343dce95a370f6cb7b9cf80e0694ac82dc94f8 diff --git a/tools/firrtl b/tools/firrtl index f738fbe866..eb637777e3 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit f738fbe8667ed6b76ec00a15960b9c3a42b8654a +Subproject commit eb637777e3c4d77435cfd13358c521ed1b766ba8 diff --git a/variables.mk b/variables.mk index 4953c96800..c851cccf89 100644 --- a/variables.mk +++ b/variables.mk @@ -38,43 +38,18 @@ ifeq ($(SUB_PROJECT),chipyard) TB ?= TestDriver TOP ?= ChipTop endif -# for Rocket-chip developers -ifeq ($(SUB_PROJECT),rocketchip) - SBT_PROJECT ?= rocketchip - MODEL ?= TestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= freechips.rocketchip.system - CONFIG ?= DefaultConfig - CONFIG_PACKAGE ?= freechips.rocketchip.system - GENERATOR_PACKAGE ?= freechips.rocketchip.system - TB ?= TestDriver - TOP ?= ExampleRocketSystem -endif # for Hwacha developers ifeq ($(SUB_PROJECT),hwacha) - SBT_PROJECT ?= hwacha + SBT_PROJECT ?= chipyard MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= freechips.rocketchip.system CONFIG ?= HwachaConfig CONFIG_PACKAGE ?= hwacha - GENERATOR_PACKAGE ?= hwacha + GENERATOR_PACKAGE ?= chipyard TB ?= TestDriver TOP ?= ExampleRocketSystem endif -# Stand-in firechip variables: -# TODO: need a seperate generator and test harnesses for each target -#ifeq ($(SUB_PROJECT),firechip) -# SBT_PROJECT ?= $(SUB_PROJECT) -# MODEL ?= TestHarness -# VLOG_MODEL ?= TestHarness -# MODEL_PACKAGE ?= freechips.rocketchip.system -# CONFIG ?= FireSimRocketChipConfig -# CONFIG_PACKAGE ?= firesim.firesim -# GENERATOR_PACKAGE ?= firesim.firesim -# TB ?= TestDriver -# TOP ?= FireSimNoNIC -#endif ######################################################################################### # path to rocket-chip and testchipip @@ -87,11 +62,6 @@ CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl # names of various files needed to compile and run things ######################################################################################### long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG) - -# match the long_name to what the specific generator will output -ifeq ($(GENERATOR_PACKAGE),freechips.rocketchip.system) - long_name=$(CONFIG_PACKAGE).$(CONFIG) -endif ifeq ($(GENERATOR_PACKAGE),hwacha) long_name=$(MODEL_PACKAGE).$(CONFIG) endif From 0035154168816b4f8d29a87096e740792cfe4175 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 18 Apr 2020 17:09:31 -0700 Subject: [PATCH 040/153] [ci] bypass approval button on dev/master (#519) --- .circleci/config.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index f7bcb507d3..74a864055d 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -358,6 +358,11 @@ workflows: build-and-test-chipyard-integration: jobs: - ci-approval: + filters: + branches: + ignore: + - master + - dev type: approval # Make the toolchains From 8469ce62e1706db102a18b7fa22656a0c506128e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 18 Apr 2020 17:11:13 -0700 Subject: [PATCH 041/153] Revert "[ci] bypass approval button on dev/master (#519)" (#520) This reverts commit 0035154168816b4f8d29a87096e740792cfe4175. --- .circleci/config.yml | 5 ----- 1 file changed, 5 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 74a864055d..f7bcb507d3 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -358,11 +358,6 @@ workflows: build-and-test-chipyard-integration: jobs: - ci-approval: - filters: - branches: - ignore: - - master - - dev type: approval # Make the toolchains From 35cba5dfaef0486a10b7b8b683200bff25952b72 Mon Sep 17 00:00:00 2001 From: Ryan Lund Date: Mon, 20 Apr 2020 10:33:03 -0700 Subject: [PATCH 042/153] Dsptools examples (#457) * Add c test files for DSPTools example * Update tests Makefile to build DSPTools c tests * Add DSPTools example configs to ConfigMixins and RocketConfigs * Add dsptools and rocket-dsptools as dependancies for example * Add Scala implementations of DSPTools test blocks * Clean up GenericFIR scala * Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial * Update documentation, will need reworking once FIR is characterized as fixed point * Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain * Fix capitalization in docs (#419) * Add c test files for DSPTools example * Update tests Makefile to build DSPTools c tests * Add DSPTools example configs to ConfigMixins and RocketConfigs * Add dsptools and rocket-dsptools as dependancies for example * Add Scala implementations of DSPTools test blocks * Clean up GenericFIR scala * Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial * Update documentation, will need reworking once FIR is characterized as fixed point * Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain * Update docs/Customization/Dsptools-Blocks.rst Co-Authored-By: alonamid * Docummentation update for clarity and to explain how this can be applied to a generalized block * Some refactoring to get dsptools working with these examples * Oops, old files crept in Co-authored-by: Ryan Lund Co-authored-by: Sagar Karandikar Co-authored-by: alonamid Co-authored-by: Paul Rigge --- build.sbt | 15 +- docs/Customization/Dsptools-Blocks.rst | 105 ++++++++ docs/Customization/index.rst | 5 +- .../src/main/scala/config/RocketConfigs.scala | 12 + .../scala/example/dsptools/DspBlocks.scala | 146 ++++++++++++ .../scala/example/dsptools/GenericFIR.scala | 224 ++++++++++++++++++ .../scala/example/dsptools/Passthrough.scala | 156 ++++++++++++ tests/Makefile | 2 +- tests/fir.c | 51 ++++ tests/passthrough.c | 49 ++++ tools/chisel-testers | 2 +- tools/dsptools | 2 +- 12 files changed, 758 insertions(+), 11 deletions(-) create mode 100644 docs/Customization/Dsptools-Blocks.rst create mode 100644 generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala create mode 100644 generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala create mode 100644 generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala create mode 100644 tests/fir.c create mode 100644 tests/passthrough.c diff --git a/build.sbt b/build.sbt index 05f05d7b45..fdeed5a79f 100644 --- a/build.sbt +++ b/build.sbt @@ -20,6 +20,8 @@ lazy val commonSettings = Seq( libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", + libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", + libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), @@ -129,6 +131,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches + dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, ariane) .settings(commonSettings) @@ -175,19 +178,17 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) -lazy val dsptools = (project in file("./tools/dsptools")) +lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel, chisel_testers) .settings( commonSettings, libraryDependencies ++= Seq( - "org.typelevel" %% "spire" % "0.14.1", - "org.scalanlp" %% "breeze" % "0.13.2", - "junit" % "junit" % "4.12" % "test", - "org.scalatest" %% "scalatest" % "3.0.5" % "test", - "org.scalacheck" %% "scalacheck" % "1.14.0" % "test" + "junit" % "junit" % "4.13" % "test", + "org.scalatest" %% "scalatest" % "3.0.8", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" )) -lazy val `rocket-dsptools` = (project in file("./tools/dsptools/rocket")) +lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) .settings(commonSettings) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst new file mode 100644 index 0000000000..228f5f91b4 --- /dev/null +++ b/docs/Customization/Dsptools-Blocks.rst @@ -0,0 +1,105 @@ +.. _dsptools-blocks: + +Dsptools Blocks +=============== + +Another way to create a MMIO peripheral is to use the Dsptools library for Chisel. In this method, a memory interface is created by creating a "chain". This chain consists of a custom module placed inside a ``DspBlock``, which is then sandwiched between a ``ReadQueue`` and ``WriteQueue``. Those queues then act as memory mapped interfaces to the Rocket Chip SoCs. This section will again primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. + +For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/example/src/main/scala/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO + +The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type generic, which means that they can be instantiated for any datatype that implements ``Ring`` operations per the specifications on ``T``. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: GenericFIR chisel + :end-before: DOC include end: GenericFIR chisel + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: GenericFIRDirectCell chisel + :end-before: DOC include end: GenericFIRDirectCell chisel + +Creating a DspBlock Extension +----------------------------- + +The first step in attaching the FIR filter as a MMIO peripheral is to create an abstract extension of ``DspBlock`` the wraps around the ``GenericFIR`` module. The main steps of this process are as follows. + +1. Instantiate a ``GenericFIR`` within ``GenericFIRBlock``. +2. Attach the ready and valid signals from the in and out connections. +3. Cast the module input data to the input type of ``GenericFIR`` (``GenericFIRBundle``) and attach. +4. Cast the output of ``GenericFIR`` to ``UInt`` and attach to the module output. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: GenericFIRBlock chisel + :end-before: DOC include end: GenericFIRBlock chisel + +Connecting by TileLink +---------------------- +With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: TLGenericFIRBlock chisel + :end-before: DOC include end: TLGenericFIRBlock chisel + +We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/example/src/main/scala/dsptools/DspBlocks.scala``. Inside our chain, we construct an instance of each queue as well as our ``TLGenericFIRBlock``. We then take the ``steamnode`` from each module and wire them all together to link the chain. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: TLGenericFIRChain chisel + :end-before: DOC include end: TLGenericFIRChain chisel + +Top Level Traits +---------------- +As in the previous MMIO example, we use a cake pattern to hook up our module to our SoC. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: CanHavePeripheryUIntTestFIR chisel + :end-before: DOC include end: CanHavePeripheryUIntTestFIR chisel + +Note that this is the point at which we decide the datatype for our FIR. It is also possible with some reworking to push the datatype selection out to the top level. + +Our module does not need to be connected to concrete IOs or wires, so we do not need to create a concrete trait. + +Constructing the Top and Config +------------------------------- + +Once again following the path of the previous MMIO example, we now want to mix our traits into the system as a whole. The code is from ``generators/example/src/main/scala/Top.scala`` + +.. literalinclude:: ../../generators/example/src/main/scala/Top.scala + :language: scala + :start-after: DOC include start: Top + :end-before: DOC include end: Top + +Finally, we create the configuration class in ``generators/example/src/main/scala/RocketConfigs.scala`` that uses the ``WithUIntTestFIR`` mixin defined in ``generators/example/src/main/scala/ConfigMixins.scala``. + +.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala + :language: scala + :start-after: DOC include start: WithTestFIR + :end-before: DOC include end: WithTestFIR + +.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala + :language: scala + :start-after: DOC include start: FIRRocketConfig + :end-before: DOC include end: FIRRocketConfig + +Testing +------- + +We can now test that the FIR is working. The test program is found in ``tests/gcd.c``. + +.. literalinclude:: ../../tests/fir.c + :language: c + +The test feed a series of values into the fir and compares the output to a golden model of computation. The base of the module's MMIO write region is at 0x2000 and the base of the read region is at 0x2100 by default. + +Compiling this program with ``make`` produces a ``fir.riscv`` executable. + +Now we can run our simulation. + +.. code-block:: shell + + cd sims/verilator + make CONFIG=GCDTLRocketConfig BINARY=../../tests/fir.riscv run-binary diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index 90d36fdaa7..9421b79a5a 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -11,7 +11,9 @@ These guides will walk you through customization of your system-on-chip: - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs -- Standard practices for using keys, traits, and configs to parameterize your design +- Adding custom Dsptools based blocks as MMIO widgets. + +- Standard practices for using Keys, Traits, and Configs to parameterize your design - Customizing the memory hierarchy @@ -36,6 +38,7 @@ We recommend reading all these pages in order. Hit next to get started! RoCC-or-MMIO RoCC-Accelerators MMIO-Peripherals + Dsptools-Blocks Keys-Traits-Configs DMA-Devices Incorporating-Verilog-Blocks diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e25680ca28..c72fb1f55b 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -384,3 +384,15 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket + +class UIntStreamingPassthroughRocketConfig extends Config( + new chipyard.example.WithUIntStreamingPassthrough ++ // use top with tilelink-controlled passthrough + new RocketConfig +) + +// DOC include start: FIRRocketConfig +class UIntTestFIRRocketConfig extends Config ( + new chipyard.example.WithUIntTestFIR ++ // use top with tilelink-controlled FIR + new RocketConfig +) +// DOC include end: FIRRocketConfig diff --git a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala new file mode 100644 index 0000000000..ad4c585ebf --- /dev/null +++ b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala @@ -0,0 +1,146 @@ +package chipyard.example + +import chisel3._ +import chisel3.util._ +import dspblocks._ +import dsptools.numbers._ +import freechips.rocketchip.amba.axi4stream._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.subsystem._ + +/** + * The memory interface writes entries into the queue. + * They stream out the streaming interface + * @param depth number of entries in the queue + * @param streamParameters parameters for the stream node + * @param p + */ +abstract class WriteQueue +( + val depth: Int = 8, + val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters() +)(implicit p: Parameters) extends LazyModule with HasCSR { + // stream node, output only + val streamNode = AXI4StreamMasterNode(streamParameters) + + lazy val module = new LazyModuleImp(this) { + require(streamNode.out.length == 1) + + // get the output bundle associated with the AXI4Stream node + val out = streamNode.out.head._1 + // width (in bits) of the output interface + val width = out.params.n * 8 + // instantiate a queue + val queue = Module(new Queue(UInt(out.params.dataBits.W), depth)) + // connect queue output to streaming output + out.valid := queue.io.deq.valid + out.bits.data := queue.io.deq.bits + // don't use last + out.bits.last := false.B + queue.io.deq.ready := out.ready + + regmap( + // each write adds an entry to the queue + 0x0 -> Seq(RegField.w(width, queue.io.enq)), + // read the number of entries in the queue + (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), + ) + } +} + +/** + * TLDspBlock specialization of WriteQueue + * @param depth number of entries in the queue + * @param csrAddress address range for peripheral + * @param beatBytes beatBytes of TL interface + * @param p + */ +class TLWriteQueue +( + depth: Int = 8, + csrAddress: AddressSet = AddressSet(0x2000, 0xff), + beatBytes: Int = 8, +)(implicit p: Parameters) extends WriteQueue(depth) with TLHasCSR { + val devname = "tlQueueIn" + val devcompat = Seq("ucb-art", "dsptools") + val device = new SimpleDevice(devname, devcompat) { + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + Description(name, mapping) + } + } + // make diplomatic TL node for regmap + override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) +} + +/** + * The streaming interface adds elements into the queue. + * The memory interface can read elements out of the queue. + * @param depth number of entries in the queue + * @param streamParameters parameters for the stream node + * @param p + */ +abstract class ReadQueue +( + val depth: Int = 8, + val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters() +)(implicit p: Parameters) extends LazyModule with HasCSR { + val streamNode = AXI4StreamSlaveNode(streamParameters) + + lazy val module = new LazyModuleImp(this) { + require(streamNode.in.length == 1) + + // get the input associated with the stream node + val in = streamNode.in.head._1 + // make a Decoupled[UInt] that RegReadFn can do something with + val out = Wire(Decoupled(UInt())) + // get width of streaming input interface + val width = in.params.n * 8 + // instantiate a queue + val queue = Module(new Queue(UInt(in.params.dataBits.W), depth)) + // connect input to the streaming interface + queue.io.enq.valid := in.valid + queue.io.enq.bits := in.bits.data + in.ready := queue.io.enq.ready + // connect output to wire + out.valid := queue.io.deq.valid + out.bits := queue.io.deq.bits + queue.io.deq.ready := out.ready + + regmap( + // map the output of the queue + 0x0 -> Seq(RegField.r(width, RegReadFn(out))), + // read the number of elements in the queue + (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), + ) + } +} + +/** + * TLDspBlock specialization of ReadQueue + * @param depth number of entries in the queue + * @param csrAddress address range + * @param beatBytes beatBytes of TL interface + * @param p + */ +class TLReadQueue +( + depth: Int = 8, + csrAddress: AddressSet = AddressSet(0x2100, 0xff), + beatBytes: Int = 8 +)(implicit p: Parameters) extends ReadQueue(depth) with TLHasCSR { + val devname = "tlQueueOut" + val devcompat = Seq("ucb-art", "dsptools") + val device = new SimpleDevice(devname, devcompat) { + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + Description(name, mapping) + } + } + // make diplomatic TL node for regmap + override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) + +} diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala new file mode 100644 index 0000000000..5335eb422d --- /dev/null +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -0,0 +1,224 @@ +//// See LICENSE for license details. +// +package chipyard.example + +import chisel3._ +import chisel3.{Bundle, Module} +import chisel3.util._ +import dspblocks._ +import dsptools.numbers._ +import freechips.rocketchip.amba.axi4stream._ +import freechips.rocketchip.config.{Parameters, Field, Config} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.subsystem._ + +// FIR params +case class GenericFIRParams( + writeAddress: BigInt = 0x2000, + readAddress: BigInt = 0x2100, + depth: Int +) + +case object GenericFIRKey extends Field[Option[GenericFIRParams]](None) + +class GenericFIRCellBundle[T<:Data:Ring](genIn:T, genOut:T) extends Bundle { + val data: T = genIn.cloneType + val carry: T = genOut.cloneType + + override def cloneType: this.type = GenericFIRCellBundle(genIn, genOut).asInstanceOf[this.type] +} +object GenericFIRCellBundle { + def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellBundle[T] = new GenericFIRCellBundle(genIn, genOut) +} + +class GenericFIRCellIO[T<:Data:Ring](genIn:T, genOut:T) extends Bundle { + val coeff = Input(genIn.cloneType) + val in = Flipped(Decoupled(GenericFIRCellBundle(genIn, genOut))) + val out = Decoupled(GenericFIRCellBundle(genIn, genOut)) +} +object GenericFIRCellIO { + def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellIO[T] = new GenericFIRCellIO(genIn, genOut) +} + +class GenericFIRBundle[T<:Data:Ring](proto: T) extends Bundle { + val data: T = proto.cloneType + + override def cloneType: this.type = GenericFIRBundle(proto).asInstanceOf[this.type] +} +object GenericFIRBundle { + def apply[T<:Data:Ring](proto: T): GenericFIRBundle[T] = new GenericFIRBundle(proto) +} + +class GenericFIRIO[T<:Data:Ring](genIn:T, genOut:T) extends Bundle { + val in = Flipped(Decoupled(GenericFIRBundle(genIn))) + val out = Decoupled(GenericFIRBundle(genOut)) +} +object GenericFIRIO { + def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRIO[T] = new GenericFIRIO(genIn, genOut) +} + +// A generic FIR filter +// DOC include start: GenericFIR chisel +class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module { + val io = IO(GenericFIRIO(genIn, genOut)) + + // Construct a vector of genericFIRDirectCells + val directCells = Seq.fill(coeffs.length){ Module(new GenericFIRDirectCell(genIn, genOut)).io } + + // Construct the direct FIR chain + for ((cell, coeff) <- directCells.zip(coeffs)) { + cell.coeff := coeff + } + + // Connect input to first cell + directCells.head.in.bits.data := io.in.bits.data + directCells.head.in.bits.carry := Ring[T].zero + directCells.head.in.valid := io.in.valid + io.in.ready := directCells.head.in.ready + + // Connect adjacent cells + // Note that .tail() returns a collection that consists of all + // elements in the inital collection minus the first one. + // This means that we zip together directCells[0, n] and + // directCells[1, n]. However, since zip ignores unmatched elements, + // the resulting zip is (directCells[0], directCells[1]) ... + // (directCells[n-1], directCells[n]) + for ((current, next) <- directCells.zip(directCells.tail)) { + next.in.bits := current.out.bits + next.in.valid := current.out.valid + current.out.ready := next.in.ready + } + + // Connect output to last cell + io.out.bits.data := directCells.last.out.bits.carry + directCells.last.out.ready := io.out.ready + io.out.valid := directCells.last.out.valid + +} +// DOC include end: GenericFIR chisel + +// A generic FIR direct cell used to construct a larger direct FIR chain +// +// in ----- [z^-1]-- out +// | +// coeff ----[*] +// | +// carryIn --[+]-- carryOut +// +// DOC include start: GenericFIRDirectCell chisel +class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { + val io = IO(GenericFIRCellIO(genIn, genOut)) + + // Registers to delay the input and the valid to propagate with calculations + val hasNewData = RegInit(0.U) + val inputReg = Reg(genIn.cloneType) + + // Passthrough ready + io.in.ready := io.out.ready + + // When a new transaction is ready on the input, we will have new data to output + // next cycle. Take this data in + when (io.in.fire()) { + hasNewData := 1.U + inputReg := io.in.bits.data + } + + // We should output data when our cell has new data to output and is ready to + // recieve new data. This insures that every cell in the chain passes its data + // on at the same time + io.out.valid := hasNewData & io.in.fire() + io.out.bits.data := inputReg + + // Compute carry + // This uses the ring implementation for + and *, i.e. + // (a * b) maps to (Ring[T].prod(a, b)) for whicever T you use + io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry +} +// DOC include end: GenericFIRDirectCell chisel + + +// DOC include start: GenericFIRBlock chisel +abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] +( + genIn: T, + genOut: T, + coeffs: Seq[T] +)(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] { + val streamNode = AXI4StreamIdentityNode() + val mem = None + + lazy val module = new LazyModuleImp(this) { + require(streamNode.in.length == 1) + require(streamNode.out.length == 1) + + val in = streamNode.in.head._1 + val out = streamNode.out.head._1 + + // instantiate generic fir + val fir = Module(new GenericFIR(genIn, genOut, coeffs)) + + // Attach ready and valid to outside interface + in.ready := fir.io.in.ready + fir.io.in.valid := in.valid + + fir.io.out.ready := out.ready + out.valid := fir.io.out.valid + + // cast UInt to T + fir.io.in.bits := in.bits.data.asTypeOf(GenericFIRBundle(genIn)) + + // cast T to UInt + out.bits.data := fir.io.out.bits.asUInt + } +} +// DOC include end: GenericFIRBlock chisel + +// DOC include start: TLGenericFIRBLock chisel +class TLGenericFIRBlock[T<:Data:Ring] +( + val genIn: T, + val genOut: T, + coeffs: Seq[T] +)(implicit p: Parameters) extends +GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T]( + genIn, genOut, coeffs +) with TLDspBlock +// DOC include end: TLGenericFIRBlock chisel + +// DOC include start: TLGenericFIRChain chisel +class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters) + extends LazyModule { + val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))) + val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs)) + val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))) + + // connect streamNodes of queues and FIR + readQueue.streamNode := fir.streamNode := writeQueue.streamNode + + lazy val module = new LazyModuleImp(this) +} +// DOC include end: TLGenericFIRChain chisel + +// DOC include start: CanHavePeripheryUIntTestFIR chisel +trait CanHavePeripheryUIntTestFIR extends BaseSubsystem { + val fir = p(GenericFIRKey) match { + case Some(params) => { + val fir = LazyModule(new TLGenericFIRChain(UInt(8.W), UInt(12.W), Seq(1.U, 2.U, 3.U), params)) + + pbus.toVariableWidthSlave(Some("firWrite")) { fir.writeQueue.mem.get } + pbus.toVariableWidthSlave(Some("firRead")) { fir.readQueue.mem.get } + } + case None => None + } +} +// DOC include end: CanHavePeripheryUIntTestFIR chisel + +/** + * Mixin to add FIR to rocket config + */ +// DOC include start: WithTestFIR +class WithUIntTestFIR extends Config((site, here, up) => { + case GenericFIRKey => Some(GenericFIRParams(depth = 8)) +}) +// DOC include end: WithTestFIR diff --git a/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala new file mode 100644 index 0000000000..1d953b83bd --- /dev/null +++ b/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala @@ -0,0 +1,156 @@ +//// See LICENSE for license details. +// +package chipyard.example + +import chisel3._ +import chisel3.{Bundle, Module} +import chisel3.util._ +import dspblocks._ +import dsptools.numbers._ +import freechips.rocketchip.amba.axi4stream._ +import freechips.rocketchip.config.{Parameters, Field, Config} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.subsystem._ + +// Simple passthrough to use as testbed sanity check +// StreamingPassthrough params +case class StreamingPassthroughParams( + writeAddress: BigInt = 0x2000, + readAddress: BigInt = 0x2100, + depth: Int +) + +// StreamingPassthrough key +case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughParams]](None) + +class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle { + val data: T = proto.cloneType + + override def cloneType: this.type = StreamingPassthroughBundle(proto).asInstanceOf[this.type] +} +object StreamingPassthroughBundle { + def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto) +} + +class StreamingPassthroughIO[T<:Data:Ring](proto: T) extends Bundle { + val in = Flipped(Decoupled(StreamingPassthroughBundle(proto))) + val out = Decoupled(StreamingPassthroughBundle(proto)) +} +object StreamingPassthroughIO { + def apply[T<:Data:Ring](proto: T): StreamingPassthroughIO[T] = new StreamingPassthroughIO(proto) +} + +class StreamingPassthrough[T<:Data:Ring](proto: T) extends Module { + val io = IO(StreamingPassthroughIO(proto)) + + io.in.ready := io.out.ready + io.out.bits.data := io.in.bits.data + io.out.valid := io.in.valid +} + +/** + * Make DspBlock wrapper for StreamingPassthrough + * @param cordicParams parameters for cordic + * @param ev$1 + * @param ev$2 + * @param ev$3 + * @param p + * @tparam D + * @tparam U + * @tparam EO + * @tparam EI + * @tparam B + * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal + */ +abstract class StreamingPassthroughBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] +( + proto: T +)(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] { + val streamNode = AXI4StreamIdentityNode() + val mem = None + + lazy val module = new LazyModuleImp(this) { + require(streamNode.in.length == 1) + require(streamNode.out.length == 1) + + val in = streamNode.in.head._1 + val out = streamNode.out.head._1 + + // instantiate passthrough + val passthrough = Module(new StreamingPassthrough(proto)) + + // Pass ready and valid from read queue to write queue + in.ready := passthrough.io.in.ready + passthrough.io.in.valid := in.valid + + // cast UInt to T + passthrough.io.in.bits := in.bits.data.asTypeOf(StreamingPassthroughBundle(proto)) + + passthrough.io.out.ready := out.ready + out.valid := passthrough.io.out.valid + + // cast T to UInt + out.bits.data := passthrough.io.out.bits.asUInt + } +} + +/** + * TLDspBlock specialization of StreamingPassthrough + * @param cordicParams parameters for passthrough + * @param ev$1 + * @param ev$2 + * @param ev$3 + * @param p + * @tparam T Type parameter for passthrough data type + */ +class TLStreamingPassthroughBlock[T<:Data:Ring] +( + val proto: T +)(implicit p: Parameters) extends +StreamingPassthroughBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T](proto) +with TLDspBlock + +/** + * A chain of queues acting as our MMIOs with the passthrough module in between them. + * @param depth depth of queues + * @param ev$1 + * @param ev$2 + * @param ev$3 + * @param p + * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal + */ +class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughParams, proto: T)(implicit p: Parameters) + extends LazyModule { + // instantiate lazy modules + val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))) + val passthrough = LazyModule(new TLStreamingPassthroughBlock(proto)) + val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))) + + // connect streamNodes of queues and passthrough + readQueue.streamNode := passthrough.streamNode := writeQueue.streamNode + + lazy val module = new LazyModuleImp(this) +} + +trait CanHavePeripheryUIntStreamingPassthrough { this: BaseSubsystem => + val passthrough = p(StreamingPassthroughKey) match { + case Some(params) => { + val passthrough = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) + + pbus.toVariableWidthSlave(Some("passthroughWrite")) { passthrough.writeQueue.mem.get } + pbus.toVariableWidthSlave(Some("passthroughRead")) { passthrough.readQueue.mem.get } + + Some(passthrough) + } + case None => None + } +} + +/** + * Mixin to add passthrough to rocket config + */ +class WithUIntStreamingPassthrough extends Config((site, here, up) => { + case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8)) +}) + diff --git a/tests/Makefile b/tests/Makefile index 6f247e7028..6fff62ceda 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -5,7 +5,7 @@ LDFLAGS= -static include libgloss.mk -PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd +PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd passthrough fir .DEFAULT_GOAL := default diff --git a/tests/fir.c b/tests/fir.c new file mode 100644 index 0000000000..46313a3598 --- /dev/null +++ b/tests/fir.c @@ -0,0 +1,51 @@ +#define PASSTHROUGH_WRITE 0x2000 +#define PASSTHROUGH_WRITE_COUNT 0x2008 +#define PASSTHROUGH_READ 0x2100 +#define PASSTHROUGH_READ_COUNT 0x2108 + +#include "mmio.h" + +#include +#include +#include +#include + +int main(void) +{ + printf("Starting writing\n"); + uint32_t num_tests = 15; + uint32_t test_vector[15] = {1, 2, 3, 4, 5, 4, 3, 2, 1, 5, 4, 3, 2, 1, 2}; + + for (int i = 0; i < num_tests; i++) { + reg_write64(PASSTHROUGH_WRITE, test_vector[i]); + } + + printf("Done writing\n"); + uint32_t rcnt = reg_read32(PASSTHROUGH_READ_COUNT); + printf("Write count: %d\n", reg_read32(PASSTHROUGH_WRITE_COUNT)); + printf("Read count: %d\n", rcnt); + + int failed = 0; + if (rcnt != 0) { + for (int i = 0; i < num_tests - 3; i++) { + uint32_t res = reg_read32(PASSTHROUGH_READ); + uint32_t expected = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2]; + if (res == expected) { + printf("\n\nPass: Got %d Expected %d\n\n", res, expected); + } else { + failed = 1; + printf("\n\nFail: Got %d Expected %d\n\n", res, expected); + } + } + } else { + failed = 1; + } + + if (failed) { + printf("\n\nSome tests failed\n\n"); + } else { + printf("\n\nAll tests passed\n\n"); + } + + return 0; +} diff --git a/tests/passthrough.c b/tests/passthrough.c new file mode 100644 index 0000000000..a25e367b6e --- /dev/null +++ b/tests/passthrough.c @@ -0,0 +1,49 @@ +#define PASSTHROUGH_WRITE 0x2000 +#define PASSTHROUGH_WRITE_COUNT 0x2008 +#define PASSTHROUGH_READ 0x2100 +#define PASSTHROUGH_READ_COUNT 0x2108 + +#include "mmio.h" + +#include +#include +#include +#include + +int main(void) +{ + printf("Starting writing\n"); + uint32_t test_vector[7] = {3, 2, 1, 0, -1, -2, -3} ; + for (int i = 0; i < 7; i++) { + reg_write64(PASSTHROUGH_WRITE, test_vector[i]); + } + + printf("Done writing\n"); + uint32_t rcnt = reg_read32(PASSTHROUGH_READ_COUNT); + printf("Write count: %d\n", reg_read32(PASSTHROUGH_WRITE_COUNT)); + printf("Read count: %d\n", rcnt); + + int failed = 0; + if (rcnt != 0) { + for (int i = 0; i < 7; i++) { + uint32_t res = reg_read32(PASSTHROUGH_READ); + uint32_t expected = test_vector[i]; + if (res == expected) { + printf("\n\nPass: Got %d Expected %d\n\n", res, test_vector[i]); + } else { + failed = 1; + printf("\n\nFail: Got %d Expected %d\n\n", res, test_vector[i]); + } + } + } else { + failed = 1; + } + + if (failed) { + printf("\n\nSome tests failed\n\n"); + } else { + printf("\n\nAll tests passed\n\n"); + } + + return 0; +} diff --git a/tools/chisel-testers b/tools/chisel-testers index f410c59316..1aa906fe16 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit f410c59316e5c43bac96411889aba8c5ab9a8fc0 +Subproject commit 1aa906fe168eb5ddca705ec955b27cf5c8856e4d diff --git a/tools/dsptools b/tools/dsptools index 15145ab623..63ac4b941b 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 15145ab6230f869676de7eb730b4267fff7b11e8 +Subproject commit 63ac4b941bc711a0c7efd48b6418c86756b403ad From e98ebec30dceec690e13cbb27ee28e217558016f Mon Sep 17 00:00:00 2001 From: KlepD-SAL <61977269+KlepD-SAL@users.noreply.github.com> Date: Mon, 20 Apr 2020 20:47:59 +0200 Subject: [PATCH 043/153] Added note about resource usage during elaboration to docs (#517) On computers with limited resources (like main memory) the elaboration will fail with the message 'make: *** [firrtl_temp] Error 137'. Since no further explaination of the error is given, its meaning should be mentioned in the docs. --- docs/Simulation/Software-RTL-Simulation.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 957913e957..bdafd60f8a 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -49,6 +49,8 @@ Simulating The Default Example To compile the example design, run ``make`` in the selected verilator or VCS directory. This will elaborate the ``RocketConfig`` in the example project. +.. Note:: The elaboration of ``RocketConfig`` requires about 6.5 GB of main memory. Otherwise the process will fail with ``make: *** [firrtl_temp] Error 137`` which is most likely related to limited resources. Other configurations might require even more main memory. + An executable called ``simulator-chipyard-RocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. You can then use this executable to run any compatible RV64 code. From 7b6a45a6a8aaa88faf08f4f8e18ad9bbd7743d7f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 20 Apr 2020 17:08:15 -0700 Subject: [PATCH 044/153] [ci] remove approval button for ci jobs (#521) --- .circleci/config.yml | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index f7bcb507d3..d91e711507 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -357,35 +357,20 @@ workflows: build-and-test-chipyard-integration: jobs: - - ci-approval: - type: approval - # Make the toolchains - - install-riscv-toolchain: - requires: - - ci-approval + - install-riscv-toolchain - - install-esp-toolchain: - requires: - - ci-approval + - install-esp-toolchain - - install-verilator: - requires: - - ci-approval + - install-verilator - - commit-on-master-check: - requires: - - ci-approval + - commit-on-master-check # Attempt to apply the tutorial patches - - tutorial-setup-check: - requires: - - ci-approval + - tutorial-setup-check # Check that documentation builds - - documentation-check: - requires: - - ci-approval + - documentation-check # Build extra tests - build-extra-tests: From a67461df7a37354e37d973f2738c797039123916 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 23 Apr 2020 16:29:36 -0700 Subject: [PATCH 045/153] [SBT] Quiet down jgit http warnings --- project/plugins.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/plugins.sbt b/project/plugins.sbt index a30249c996..d8d00e3513 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,6 +1,6 @@ resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) resolvers += Classpaths.sbtPluginReleases -resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven" +resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") From eeafc82d12c98111a2409f6f8d13fdd81e1a18e4 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 23 Apr 2020 16:28:56 -0700 Subject: [PATCH 046/153] Remove ++ per Jack's recommendation --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index c851cccf89..80e10a0ce1 100644 --- a/variables.mk +++ b/variables.mk @@ -102,7 +102,7 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M SCALA_VERSION=2.12.10 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) +SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ######################################################################################### # output directory for tests From 9d15f2e4e988be3fa18d9af13b5899070583b28f Mon Sep 17 00:00:00 2001 From: Matthias-Raudonis <33962683+Matthias-Raudonis@users.noreply.github.com> Date: Fri, 24 Apr 2020 19:10:31 +0200 Subject: [PATCH 047/153] Include scripts for dependencies in documentation (#518) --- docs/index.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/docs/index.rst b/docs/index.rst index debfaf99e3..855929cd33 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -37,6 +37,20 @@ Start by fetching Chipyard's sources. Run: This will initialize and checkout all of the necessary git submodules. +Installing Dependencies +------------------------------------------- +Installing the recommended dependencies on Ubuntu/Debian-based platforms: + +.. code-block:: shell + + ./scripts/ubuntu-req.sh + +Installing the recommended dependencies on CentOS-based platforms: + +.. code-block:: shell + + ./scripts/centos-req.sh + Installing the RISC-V Tools ------------------------------------------- From f30daa406319d1761b1c5bb8cb6428c49fefd2b2 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 24 Apr 2020 13:33:30 -0700 Subject: [PATCH 048/153] [ci] Lengthen hetero tests timeout --- .circleci/config.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index d91e711507..97a27e7adf 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -279,6 +279,7 @@ jobs: steps: - run-tests: project-key: "chipyard-hetero" + timeout: "15m" chipyard-boom-run-tests: executor: main-env steps: From b26ed91b7364d79c903f84832539fcda001e371b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 24 Apr 2020 13:35:23 -0700 Subject: [PATCH 049/153] [CI] Convert FireSim tests to use ScalaTest --- .circleci/config.yml | 49 ++++++++----------- .circleci/defaults.sh | 8 +-- ...im-build.sh => run-firesim-scala-tests.sh} | 29 ++--------- .circleci/run-firesim-tests.sh | 29 ----------- generators/ariane | 2 +- .../src/test/scala/ScalaTestSuite.scala | 3 ++ sims/firesim | 2 +- 7 files changed, 35 insertions(+), 87 deletions(-) rename .circleci/{do-firesim-build.sh => run-firesim-scala-tests.sh} (60%) delete mode 100755 .circleci/run-firesim-tests.sh diff --git a/.circleci/config.yml b/.circleci/config.yml index 97a27e7adf..801c3b852e 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -247,18 +247,6 @@ jobs: steps: - prepare-rtl: project-key: "tracegen-boom" - prepare-firesim: - executor: main-env - steps: - - prepare-rtl: - project-key: "firesim" - build-script: "do-firesim-build.sh" - prepare-fireboom: - executor: main-env - steps: - - prepare-rtl: - project-key: "fireboom" - build-script: "do-firesim-build.sh" prepare-chipyard-ariane: executor: main-env steps: @@ -318,15 +306,24 @@ jobs: - run-tests: extra-cache-restore: "extra-tests" project-key: "firesim" - run-script: "run-firesim-tests.sh" + run-script: "run-firesim-scala-tests.sh" + timeout: "20m" fireboom-run-tests: executor: main-env steps: - run-tests: extra-cache-restore: "extra-tests" project-key: "fireboom" - run-script: "run-firesim-tests.sh" - timeout: "30m" + run-script: "run-firesim-scala-tests.sh" + timeout: "45m" + firesim-multiclock-run-tests: + executor: main-env + steps: + - run-tests: + extra-cache-restore: "extra-tests" + project-key: "firesim-multiclock" + run-script: "run-firesim-scala-tests.sh" + timeout: "20m" midasexamples-run-tests: executor: main-env steps: @@ -429,16 +426,6 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-firesim: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-fireboom: - requires: - - install-riscv-toolchain - - install-verilator - - prepare-chipyard-ariane: requires: - install-riscv-toolchain @@ -491,12 +478,18 @@ workflows: # Run the firesim tests - firesim-run-tests: requires: - - prepare-firesim + - install-riscv-toolchain + - install-verilator + - build-extra-tests + - firesim-multiclock-run-tests: + requires: + - install-riscv-toolchain + - install-verilator - build-extra-tests - - fireboom-run-tests: requires: - - prepare-fireboom + - install-riscv-toolchain + - install-verilator - build-extra-tests - chipyard-ariane-run-tests: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 7d4fdaa3b8..f1be9e0576 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -50,9 +50,9 @@ mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" +mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" -mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config" -mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config" -mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" -mapping["fireariane"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig PLATFORM_CONFIG=BaseF1Config" +mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" +mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" +mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" diff --git a/.circleci/do-firesim-build.sh b/.circleci/run-firesim-scala-tests.sh similarity index 60% rename from .circleci/do-firesim-build.sh rename to .circleci/run-firesim-scala-tests.sh index 7d86c7799f..93c4561db5 100755 --- a/.circleci/do-firesim-build.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -22,7 +22,6 @@ cd $LOCAL_CHIPYARD_DIR/sims/firesim ./scripts/build-libdwarf.sh cd $LOCAL_CHIPYARD_DIR - # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" @@ -30,7 +29,9 @@ clean # copy over riscv/esp-tools, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" +run "mkdir -p $REMOTE_RISCV_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR +copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" run "cp -r ~/.sbt $REMOTE_WORK_DIR" @@ -38,31 +39,11 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then - TOOLS_DIR=$REMOTE_ESP_DIR - LD_LIB_DIR=$REMOTE_ESP_DIR/lib - run "mkdir -p $REMOTE_ESP_DIR" - copy $LOCAL_ESP_DIR/ $SERVER:$REMOTE_ESP_DIR -else - run "mkdir -p $REMOTE_RISCV_DIR" - copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR -fi -# Build MIDAS-level verilator sim -FIRESIM_VARS="${mapping[$1]}" -run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" +# Run Firesim Scala Tests run "export RISCV=\"$TOOLS_DIR\"; \ export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export FIRESIM_ENV_SOURCED=1; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - export FIRESIM_ENV_SOURCED=1; \ - make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" $FIRESIM_VARS verilator" -run "rm -rf $REMOTE_CHIPYARD_DIR/project" - -# copy back the final build -mkdir -p $LOCAL_CHIPYARD_DIR -copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR - -# Fix dramsim2_ini symlink -export $FIRESIM_VARS -ln -sf $LOCAL_FIRESIM_DIR/midas/src/main/resources/dramsim2_ini $LOCAL_FIRESIM_DIR/generated-src/f1/${DESIGN}-${TARGET_CONFIG}-${PLATFORM_CONFIG}/dramsim2_ini + make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}" diff --git a/.circleci/run-firesim-tests.sh b/.circleci/run-firesim-tests.sh deleted file mode 100755 index d1111e60d6..0000000000 --- a/.circleci/run-firesim-tests.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/bash - -# turn echo on and error on earliest command -set -ex - -# get remote exec variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -export FIRESIM_ENV_SOURCED=1 - -SIMULATION_ARGS="${mapping[$1]}" - -cd $LOCAL_CHIPYARD_DIR/sims/firesim -./scripts/build-libelf.sh -./scripts/build-libdwarf.sh -cd $LOCAL_CHIPYARD_DIR - - -run_test_suite () { - export RISCV=$LOCAL_RISCV_DIR - export LD_LIBRARY_PATH=$LOCAL_RISCV_DIR/lib - make -C $LOCAL_FIRESIM_DIR $SIMULATION_ARGS run-${1}-tests-fast -} - - -run_test_suite bmark -run_test_suite nic -run_test_suite blockdev diff --git a/generators/ariane b/generators/ariane index 621201b1d5..f4ba64a624 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 621201b1d5a929ab0e89f1a857b76a33e7e2e8a8 +Subproject commit f4ba64a624091600e9d7d40c293b8d5c17f47c56 diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 68797432b7..c5af5cda7e 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -141,6 +141,9 @@ class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimL class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } +class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { + runSuite("verilator")(NICLoopbackTests) +} // Disabled until RAM optimizations re-enabled in multiclock //class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") //class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") diff --git a/sims/firesim b/sims/firesim index f82e115c66..d5d4f4d6f8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f82e115c6641c5fe33f756abeb8093f64b0d0a80 +Subproject commit d5d4f4d6f8cf5a499fee5365eec9eec794bbd08c From 462f4d0f315baca7c9a13b57381c35acb83e7482 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 25 Apr 2020 11:28:21 -0700 Subject: [PATCH 050/153] [CI] Disable SBT supershell --- .circleci/defaults.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index f1be9e0576..9dfff4d5b6 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -30,7 +30,8 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim -REMOTE_JAVA_ARGS="-Xmx8G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +# Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI +REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) From e22ff880e295eb43f6a4eebf1b3f52165216e22e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 27 Apr 2020 20:27:36 -0700 Subject: [PATCH 051/153] [firesim] generate rocket-chip based artefacts (#534) --- generators/firechip/src/main/scala/Generator.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 852b9fbd24..01747bb320 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -9,7 +9,7 @@ import chisel3.internal.firrtl.{Circuit, Port} import freechips.rocketchip.diplomacy.{ValName, AutoBundle} import freechips.rocketchip.devices.debug.DebugIO -import midas.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts} +import freechips.rocketchip.util.{ElaborationArtefacts} import freechips.rocketchip.system.DefaultTestSuites._ import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} import freechips.rocketchip.config.Parameters @@ -54,6 +54,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu // Output miscellaneous files produced as a side-effect of elaboration def generateArtefacts { + // generate RC's artefacts ElaborationArtefacts.files.foreach { case (extension, contents) => writeOutputFile(s"${longName}.${extension}", contents ()) } From b813caf6fd08d294dc73bd98a39097aebaaff5d4 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 22 Apr 2020 19:58:24 -0700 Subject: [PATCH 052/153] get icenet and testchipip unit tests working --- .../src/main/scala/unittest/TestHarness.scala | 9 +++++++ .../main/scala/unittest/UnitTestSuite.scala | 8 +++++++ generators/icenet | 2 +- generators/testchipip | 2 +- sims/vcs/Makefile | 2 +- variables.mk | 24 +++++++++++++++++++ 6 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 generators/chipyard/src/main/scala/unittest/TestHarness.scala create mode 100644 generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala diff --git a/generators/chipyard/src/main/scala/unittest/TestHarness.scala b/generators/chipyard/src/main/scala/unittest/TestHarness.scala new file mode 100644 index 0000000000..8bb4bbd9fb --- /dev/null +++ b/generators/chipyard/src/main/scala/unittest/TestHarness.scala @@ -0,0 +1,9 @@ +package chipyard.unittest + +import chisel3._ +import freechips.rocketchip.config.Parameters + +class TestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { val success = Output(Bool()) }) + io.success := Module(new UnitTestSuite).io.finished +} diff --git a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala new file mode 100644 index 0000000000..40e991a263 --- /dev/null +++ b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala @@ -0,0 +1,8 @@ +package chipyard.unittest + +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts} + +class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite { + ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader) +} diff --git a/generators/icenet b/generators/icenet index 4522a3979b..705ca50690 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 4522a3979be092c4221f186bdd93bf330fdca134 +Subproject commit 705ca50690383aa589dc560a5e7c152af04c46ad diff --git a/generators/testchipip b/generators/testchipip index b8d6f21019..ba705408fa 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b8d6f2101947e9f80f896dbaa5802946e2a3b9f0 +Subproject commit ba705408fa707d8e4e132fabd59dacb9eb12e985 diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 659d1fc03a..c00819c259 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -56,7 +56,7 @@ VCS_CC_OPTS = \ VCS_NONCC_OPTS = \ +lint=all,noVCDE,noONGS,noUI \ -error=PCWM-L \ - -timescale=1ns/10ps \ + -timescale=1ns/1ps \ -quiet \ -q \ +rad \ diff --git a/variables.mk b/variables.mk index 80e10a0ce1..ad981245f9 100644 --- a/variables.mk +++ b/variables.mk @@ -50,6 +50,30 @@ ifeq ($(SUB_PROJECT),hwacha) TB ?= TestDriver TOP ?= ExampleRocketSystem endif +# For TestChipIP developers +ifeq ($(SUB_PROJECT),testchipip) + SBT_PROJECT ?= chipyard + MODEL ?= TestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= chipyard.unittest + CONFIG ?= TestChipUnitTestConfig + CONFIG_PACKAGE ?= testchipip + GENERATOR_PACKAGE ?= chipyard + TB ?= TestDriver + TOP ?= UnitTestSuite +endif +# For IceNet developers +ifeq ($(SUB_PROJECT),icenet) + SBT_PROJECT ?= chipyard + MODEL ?= TestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= chipyard.unittest + CONFIG ?= IceNetUnitTestConfig + CONFIG_PACKAGE ?= icenet + GENERATOR_PACKAGE ?= chipyard + TB ?= TestDriver + TOP ?= UnitTestSuite +endif ######################################################################################### # path to rocket-chip and testchipip From a905dbedcc5d85bfec60c01c7ae934ef9f2f5e75 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 24 Apr 2020 17:08:58 -0700 Subject: [PATCH 053/153] add make rules for running simulator without executable --- common.mk | 14 ++++++++++++++ sims/vcs/Makefile | 4 ++++ sims/verilator/Makefile | 6 ++++++ 3 files changed, 24 insertions(+) diff --git a/common.mk b/common.mk index 696e0f8315..b5a5bb072c 100644 --- a/common.mk +++ b/common.mk @@ -136,6 +136,12 @@ run-binary-debug: $(sim_debug) run-fast: run-asm-tests-fast run-bmark-tests-fast +run-none: $(output_dir)/none.out + +run-none-fast: $(output_dir)/none.run + +run-none-debug: $(output_dir)/none.vpd + ######################################################################################### # run assembly/benchmarks rules ######################################################################################### @@ -149,6 +155,14 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) $(output_dir)/%.out: $(output_dir)/% $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) +$(output_dir)/none.run: $(sim) + mkdir -p $(output_dir) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $(output_dir)/none.log) + ######################################################################################### # include build/project specific makefrags made from the generator ######################################################################################### diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index c00819c259..f5b7e5dbae 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -102,6 +102,10 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) +$(output_dir)/none.vpd: $(sim_debug) + mkdir -p $(output_dir) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) + ######################################################################################### # general cleanup rule ######################################################################################### diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 0ab0016c90..432169d652 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -145,6 +145,12 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) vcd2vpd $@.vcd $@ > /dev/null & (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) +$(output_dir)/none.vpd: $(sim_debug) + mkdir -p $(output_dir) + rm -f $@.vcd && mkfifo $@.vcd + vcd2vpd $@.vcd $@ > /dev/null & + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) + ######################################################################################### # general cleanup rule ######################################################################################### From 8df43203a2bff518f0225507bfbe6fc73bad5bf4 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 24 Apr 2020 17:09:05 -0700 Subject: [PATCH 054/153] separate testchipip ClockUtilTests and TestChipUnitTests --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index ba705408fa..cec2c0b6d6 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ba705408fa707d8e4e132fabd59dacb9eb12e985 +Subproject commit cec2c0b6d66c3df05d08462167bb8a58c0912d06 From 94628e78b2b2bf7aaa296481d5a63809af065d9f Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 24 Apr 2020 17:15:15 -0700 Subject: [PATCH 055/153] add icenet and testchipip unit tests to CI --- .circleci/config.yml | 40 ++++++++++++++++++++++++++++++++++++++++ .circleci/defaults.sh | 2 ++ .circleci/run-tests.sh | 6 ++++++ 3 files changed, 48 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index 801c3b852e..ff691e41dd 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -252,6 +252,16 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-ariane" + prepare-icenet: + executor: main-env + steps: + - prepare-rtl: + project-key: "icenet" + prepare-testchipip: + executor: main-env + steps: + - prepare-rtl: + project-key: "testchipip" chipyard-rocket-run-tests: executor: main-env steps: @@ -337,6 +347,18 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" + icenet-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "icenet" + timeout: "30m" + testchipip-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "testchipip" + timeout: "30m" # Order and dependencies of jobs to run workflows: @@ -431,6 +453,16 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-icenet: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-testchipip: + requires: + - install-riscv-toolchain + - install-verilator + # Run the respective tests # Run midasexamples test @@ -495,3 +527,11 @@ workflows: - chipyard-ariane-run-tests: requires: - prepare-chipyard-ariane + + - icenet-run-tests: + requires: + - prepare-icenet + + - testchipip-run-tests: + requires: + - prepare-testchipip diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 9dfff4d5b6..38da902bdc 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -57,3 +57,5 @@ mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=Tra mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" +mapping["icenet"]="SUB_PROJECT=icenet" +mapping["testchipip"]="SUB_PROJECT=testchipip" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 480908c9dc..5f3056172a 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -71,6 +71,12 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; + icenet) + make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]} + ;; + testchipip) + make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]} + ;; *) echo "No set of tests for $1. Did you spell it right?" exit 1 From 24fada1d9ca4dc8cad7900676ab7b6ebf5c138b8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 29 Apr 2020 01:24:25 -0700 Subject: [PATCH 056/153] Add WithNoUART fragment (#536) --- generators/chipyard/src/main/scala/ConfigFragments.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index dee1a40aff..e1a047dcbb 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -53,7 +53,11 @@ class WithUART extends Config((site, here, up) => { }) class WithNoGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Seq() + case PeripheryGPIOKey => Nil +}) + +class WithNoUART extends Config((site, here, up) => { + case PeripheryUARTKey => Nil }) class WithL2TLBs(entries: Int) extends Config((site, here, up) => { From 02367022b048500128a3aaefb5c1d64ac7b61ad4 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 29 Apr 2020 16:25:02 -0700 Subject: [PATCH 057/153] Fix "WithHeterCoresSetup" in hetero. docs (#537) --- docs/Customization/Heterogeneous-SoCs.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index 765a1afeed..fd1a688019 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -40,13 +40,13 @@ The config fragment to add to your system would look something like the followin val boomTile1 = BoomTileParams(...) // params for boom core 1 val boomTile2 = BoomTileParams(...) // params for boom core 2 val boomTile3 = BoomTileParams(...) // params for boom core 3 - boomTile0 ++ boomTile1 ++ boomTile2 ++ boomTile3 + Seq(boomTile0, boomTile1, boomTile2, boomTile3) } case RocketTilesKey => { val rocketTile0 = RocketTileParams(...) // params for rocket core 0 val rocketTile1 = RocketTileParams(...) // params for rocket core 1 - rocketTile0 ++ rocketTile1 + Seq(rocketTile0, rocketTile1) } }) From 0cc643bfdbeef594e68bc7fb0c2a9e0f1cacf9e0 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Thu, 30 Apr 2020 10:51:32 -0700 Subject: [PATCH 058/153] Switch FIR from UInt -> FixedPoint --- .../chipyard/src/main/scala/DigitalTop.scala | 2 ++ .../scala/example/dsptools/GenericFIR.scala | 26 +++++++++-------- tests/fir.c | 28 ++++++++++++++----- 3 files changed, 38 insertions(+), 18 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index c7b3d49733..75262a99ef 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -22,6 +22,8 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget + with chipyard.example.CanHavePeripheryUIntTestFIR // Enables optionally adding the FIR example widget + with chipyard.example.CanHavePeripheryUIntStreamingPassthrough // Enables optionally adding the passthrough example widget { override lazy val module = new DigitalTopModule(this) } diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 5335eb422d..45093f9a6d 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -3,7 +3,7 @@ package chipyard.example import chisel3._ -import chisel3.{Bundle, Module} +import chisel3.experimental.FixedPoint import chisel3.util._ import dspblocks._ import dsptools.numbers._ @@ -80,9 +80,9 @@ class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module // Connect adjacent cells // Note that .tail() returns a collection that consists of all // elements in the inital collection minus the first one. - // This means that we zip together directCells[0, n] and + // This means that we zip together directCells[0, n] and // directCells[1, n]. However, since zip ignores unmatched elements, - // the resulting zip is (directCells[0], directCells[1]) ... + // the resulting zip is (directCells[0], directCells[1]) ... // (directCells[n-1], directCells[n]) for ((current, next) <- directCells.zip(directCells.tail)) { next.in.bits := current.out.bits @@ -108,22 +108,22 @@ class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module // // DOC include start: GenericFIRDirectCell chisel class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { - val io = IO(GenericFIRCellIO(genIn, genOut)) - + val io = IO(GenericFIRCellIO(genIn, genOut)) + // Registers to delay the input and the valid to propagate with calculations val hasNewData = RegInit(0.U) val inputReg = Reg(genIn.cloneType) // Passthrough ready io.in.ready := io.out.ready - + // When a new transaction is ready on the input, we will have new data to output // next cycle. Take this data in when (io.in.fire()) { hasNewData := 1.U - inputReg := io.in.bits.data + inputReg := io.in.bits.data } - + // We should output data when our cell has new data to output and is ready to // recieve new data. This insures that every cell in the chain passes its data // on at the same time @@ -133,7 +133,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { // Compute carry // This uses the ring implementation for + and *, i.e. // (a * b) maps to (Ring[T].prod(a, b)) for whicever T you use - io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry + io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry } // DOC include end: GenericFIRDirectCell chisel @@ -204,8 +204,12 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], para trait CanHavePeripheryUIntTestFIR extends BaseSubsystem { val fir = p(GenericFIRKey) match { case Some(params) => { - val fir = LazyModule(new TLGenericFIRChain(UInt(8.W), UInt(12.W), Seq(1.U, 2.U, 3.U), params)) - + val fir = LazyModule(new TLGenericFIRChain( + genIn = FixedPoint(8.W, 3.BP), + genOut = FixedPoint(8.W, 3.BP), + coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)), + params = params)) + pbus.toVariableWidthSlave(Some("firWrite")) { fir.writeQueue.mem.get } pbus.toVariableWidthSlave(Some("firRead")) { fir.readQueue.mem.get } } diff --git a/tests/fir.c b/tests/fir.c index 46313a3598..be61534ecb 100644 --- a/tests/fir.c +++ b/tests/fir.c @@ -3,6 +3,9 @@ #define PASSTHROUGH_READ 0x2100 #define PASSTHROUGH_READ_COUNT 0x2108 +#define BP 3 +#define BP_SCALE ((double)(1 << BP)) + #include "mmio.h" #include @@ -10,14 +13,23 @@ #include #include +uint64_t roundi(double x) +{ + if (x < 0.0) { + return (uint64_t)(x - 0.5); + } else { + return (uint64_t)(x + 0.5); + } +} + int main(void) { - printf("Starting writing\n"); - uint32_t num_tests = 15; - uint32_t test_vector[15] = {1, 2, 3, 4, 5, 4, 3, 2, 1, 5, 4, 3, 2, 1, 2}; + double test_vector[15] = {1.0, 2.0, 3.0, 4.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.5, 0.25, 0.125, 0.125}; + uint32_t num_tests = sizeof(test_vector) / sizeof(double); + printf("Starting writing %d inputs\n", num_tests); for (int i = 0; i < num_tests; i++) { - reg_write64(PASSTHROUGH_WRITE, test_vector[i]); + reg_write64(PASSTHROUGH_WRITE, roundi(test_vector[i] * BP_SCALE)); } printf("Done writing\n"); @@ -29,12 +41,14 @@ int main(void) if (rcnt != 0) { for (int i = 0; i < num_tests - 3; i++) { uint32_t res = reg_read32(PASSTHROUGH_READ); - uint32_t expected = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2]; + // double res = ((double)reg_read32(PASSTHROUGH_READ)) / BP_SCALE; + double expected_double = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2]; + uint32_t expected = ((uint32_t)(expected_double * BP_SCALE + 0.5)) & 0xFF; if (res == expected) { - printf("\n\nPass: Got %d Expected %d\n\n", res, expected); + printf("\n\nPass: Got %u Expected %u\n\n", res, expected); } else { failed = 1; - printf("\n\nFail: Got %d Expected %d\n\n", res, expected); + printf("\n\nFail: Got %u Expected %u\n\n", res, expected); } } } else { From 658e92e951d2368d60c1ed5a2a4f61e7e3b6cf56 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 1 May 2020 14:23:16 -0700 Subject: [PATCH 059/153] [docs] Make the link to initial setup stand out. (#533) * [docs] Make the link to initial setup stand out. * [docs] Merge the two quick starts * More descriptive text about the setup link Co-authored-by: alonamid --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 42 +++++++++-- docs/_static/css/custom.css | 6 ++ docs/conf.py | 3 + docs/index.rst | 82 +-------------------- docs/requirements.txt | 2 +- 5 files changed, 46 insertions(+), 89 deletions(-) create mode 100644 docs/_static/css/custom.css diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index c4732e8a5f..08930f503d 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -23,10 +23,10 @@ In Ubuntu/Debian-based platforms (Ubuntu), we recommend installing the following .. Note:: When running on an Amazon Web Services EC2 FPGA-development instance (for FireSim), FireSim includes a machine setup script that will install all of the aforementioned dependencies (and some additional ones). -Checking out the sources ------------------------- +Setting up the Chipyard Repo +------------------------------------------- -After cloning this repo, you will need to initialize all of the submodules. +Start by fetching Chipyard's sources. Run: .. code-block:: shell @@ -34,6 +34,8 @@ After cloning this repo, you will need to initialize all of the submodules. cd chipyard ./scripts/init-submodules-no-riscv-tools.sh +This will initialize and checkout all of the necessary git submodules. + When updating Chipyard to a new version, you will also want to rerun this script to update the submodules. Using git directly will try to initialize all submodules; this is not recommended unless you expressly desire this behavior. @@ -46,15 +48,41 @@ The `toolchains` directory contains toolchains that include a cross-compiler too Currently there are two toolchains, one for normal RISC-V programs, and another for Hwacha (``esp-tools``). For custom installations, Each tool within the toolchains contains individual installation procedures within its README file. To get a basic installation (which is the only thing needed for most Chipyard use-cases), just the following steps are necessary. +This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. .. code-block:: shell ./scripts/build-toolchains.sh riscv-tools # for a normal risc-v toolchain - # OR - - ./scripts/build-toolchains.sh esp-tools # for a modified risc-v toolchain with Hwacha vector instructions +.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. + If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. Once the script is run, a ``env.sh`` file is emitted that sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables. -You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables. +You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables, or directly include it in your current environment: + +.. code-block:: shell + + source ./env.sh + These variables need to be set for the ``make`` system to work properly. + +What's Next? +------------------------------------------- + +This depends on what you are planning to do with Chipyard. + +* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. + +* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. + +* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. + +* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions. + +* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. + +* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`. + +* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. + +* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. diff --git a/docs/_static/css/custom.css b/docs/_static/css/custom.css new file mode 100644 index 0000000000..3fa65d52e5 --- /dev/null +++ b/docs/_static/css/custom.css @@ -0,0 +1,6 @@ +.important { + font-size: 175%; +} +.important p{ + font-size: 100%; +} diff --git a/docs/conf.py b/docs/conf.py index f4a3272b1a..e0accb5e59 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -106,6 +106,9 @@ # relative to this directory. They are copied after the builtin static files, # so a file named "default.css" will overwrite the builtin "default.css". html_static_path = ['_static'] +html_css_files = [ + 'css/custom.css', +] # Custom sidebar templates, must be a dictionary that maps document names # to template names. diff --git a/docs/index.rst b/docs/index.rst index 855929cd33..d776b3534d 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -10,89 +10,9 @@ Welcome to Chipyard's documentation! Chipyard is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. -New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. -Quick Start -=============================== +.. IMPORTANT:: **New to Chipyard?** Jump to the :ref:`Initial Repository Setup` page for setup instructions. -System Requirements -------------------------------------------- - -Chipyard is developed and tested on Linux-based systems. - -.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. - -.. Warning:: Working under Windows is not recommended. - -Setting up the Chipyard Repo -------------------------------------------- - -Start by fetching Chipyard's sources. Run: - -.. code-block:: shell - - git clone https://github.com/ucb-bar/chipyard.git - cd chipyard - ./scripts/init-submodules-no-riscv-tools.sh - -This will initialize and checkout all of the necessary git submodules. - -Installing Dependencies -------------------------------------------- -Installing the recommended dependencies on Ubuntu/Debian-based platforms: - -.. code-block:: shell - - ./scripts/ubuntu-req.sh - -Installing the recommended dependencies on CentOS-based platforms: - -.. code-block:: shell - - ./scripts/centos-req.sh - -Installing the RISC-V Tools -------------------------------------------- - -We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure. -This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. -To build the toolchains, you should run: - -.. code-block:: shell - - ./scripts/build-toolchains.sh - -.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. - If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. - -Finally, set up Chipyard's environment variables and put the newly built toolchain on your path: - -.. code-block:: shell - - source ./env.sh - -What's Next? -------------------------------------------- - -This depends on what you are planning to do with Chipyard. - -* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. - -* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. - -* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. - -* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions. - -* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. - -* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`. - -* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. - -* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. - - Getting Help ------------ diff --git a/docs/requirements.txt b/docs/requirements.txt index 2abac52d7a..4b1565b36b 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,4 +1,4 @@ -Sphinx==1.7.4 +Sphinx==1.8.5 Pygments==2.2.0 sphinx-autobuild sphinx_rtd_theme==0.2.5b1 From 356de57580f336d4fc6ee533c3d3f24068485655 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 3 May 2020 14:25:12 -0700 Subject: [PATCH 060/153] Bump FireMarshal to disable SiFive uart driver --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index d660c45ac1..c8e89bbeb5 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit d660c45ac12df4624d1784c19dab03b92347f878 +Subproject commit c8e89bbeb575be027670afa21c761319c2fd7e33 From 794509aba9ee543d23911d9d4ce6272a50edbed6 Mon Sep 17 00:00:00 2001 From: John Wright Date: Mon, 4 May 2020 14:39:05 -0700 Subject: [PATCH 061/153] [ci skip] Scaladoc and comment fixes (#542) --- generators/chipyard/src/main/scala/IOBinders.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index e3c79f3a7e..281c5917ba 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -104,7 +104,7 @@ object AddIOCells { /** * Add IO cells to a SiFive UART devices and name the IO ports. - * @param gpios A Seq of UART port bundles + * @param uartPins A Seq of UART port bundles * @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references) */ def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = { @@ -117,7 +117,7 @@ object AddIOCells { /** * Add IO cells to a debug module and name the IO ports. - * @param gpios A PSDIO bundle + * @param psd A PSDIO bundle * @param resetctrlOpt An optional ResetCtrlIO bundle * @param debugOpt An optional DebugIO bundle * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references) @@ -312,4 +312,4 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ } }) -} +} /* end package object */ From 9b945706484647a7d21ec549df04c38ac088e226 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 5 May 2020 11:02:28 -0700 Subject: [PATCH 062/153] bump rocket chisel (3.3) and firrtl (1.3) --- generators/rocket-chip | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 9b1907eacb..1872f5d501 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 9b1907eacbeb268d47e204e3de1818823d605ba4 +Subproject commit 1872f5d501221f13950aa2293939634a1e0d1735 diff --git a/tools/chisel3 b/tools/chisel3 index 7a343dce95..21ea734d80 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit 7a343dce95a370f6cb7b9cf80e0694ac82dc94f8 +Subproject commit 21ea734d809395962a8d3195a76377f6e44308f3 diff --git a/tools/firrtl b/tools/firrtl index eb637777e3..7c6f58d986 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit eb637777e3c4d77435cfd13358c521ed1b766ba8 +Subproject commit 7c6f58d986e67b3d0662a4cd6654a68f9cc52cf9 From 63c46d89c1184d7415e83a32c27608345a25f160 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 5 May 2020 13:58:01 -0700 Subject: [PATCH 063/153] Bump sifive-blocks --- docs/Customization/Heterogeneous-SoCs.rst | 1 - .../src/main/scala/ConfigFragments.scala | 8 -------- .../src/main/scala/config/ArianeConfigs.scala | 2 -- .../src/main/scala/config/BoomConfigs.scala | 8 -------- .../src/main/scala/config/HeteroConfigs.scala | 7 ------- .../src/main/scala/config/RocketConfigs.scala | 18 ------------------ .../main/scala/config/TutorialConfigs.scala | 4 ---- generators/sifive-blocks | 2 +- 8 files changed, 1 insertion(+), 49 deletions(-) diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index fd1a688019..c640e31c75 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -56,7 +56,6 @@ Then you could use this new config fragment like the following. class SixCoreConfig extends Config( new WithTSI ++ - new WithNoGPIO ++ new WithBootROM ++ new WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index e1a047dcbb..2db12ff799 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -52,14 +52,6 @@ class WithUART extends Config((site, here, up) => { UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) }) -class WithNoGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Nil -}) - -class WithNoUART extends Config((site, here, up) => { - case PeripheryUARTKey => Nil -}) - class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( core = tile.core.copy(nL2TLBEntries = entries) diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index e0cb771eec..6dfb4c74a9 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -15,7 +15,6 @@ class ArianeConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) @@ -31,7 +30,6 @@ class dmiArianeConfig extends Config( new chipyard.iobinders.WithSimAXIMem ++ new chipyard.iobinders.WithTiedOffSerial ++ new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 35934eabd7..4c1943682e 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -13,7 +13,6 @@ class SmallBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -32,7 +31,6 @@ class MediumBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -51,7 +49,6 @@ class LargeBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -70,7 +67,6 @@ class MegaBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -89,7 +85,6 @@ class DualSmallBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -108,7 +103,6 @@ class SmallRV32BoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -129,7 +123,6 @@ class HwachaLargeBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -151,7 +144,6 @@ class LoopbackNICLargeBoomConfig extends Config( new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback new testchipip.WithTSI ++ new icenet.WithIceNIC ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index af2145e7b4..11835aa4d8 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -13,7 +13,6 @@ class LargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -35,7 +34,6 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -58,7 +56,6 @@ class DualLargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -81,7 +78,6 @@ class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc @@ -107,7 +103,6 @@ class LargeBoomAndRV32RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -131,7 +126,6 @@ class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -153,7 +147,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithControlCore ++ // add small control core to last hartid diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e25680ca28..4058fcf4f1 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -13,7 +13,6 @@ class RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -31,7 +30,6 @@ class HwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -51,7 +49,6 @@ class GemminiRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -71,7 +68,6 @@ class RoccRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -91,7 +87,6 @@ class jtagRocketConfig extends Config( new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -111,7 +106,6 @@ class dmiRocketConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffSerial ++ new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -131,7 +125,6 @@ class GCDTLRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithUART ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -153,7 +146,6 @@ class GCDAXI4BlackBoxRocketConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ new chipyard.config.WithUART ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink @@ -174,7 +166,6 @@ class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -194,7 +185,6 @@ class BlockDeviceModelRocketConfig extends Config( new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to periphery bus - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -235,7 +225,6 @@ class QuadRocketConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ @@ -251,7 +240,6 @@ class RV32RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -269,7 +257,6 @@ class GB1MemoryRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -289,7 +276,6 @@ class Sha3RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -310,7 +296,6 @@ class InitZeroRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -332,7 +317,6 @@ class LoopbackNICRocketConfig extends Config( new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback new testchipip.WithTSI ++ new icenet.WithIceNIC ++ // add an IceNIC - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -351,7 +335,6 @@ class ScratchpadRocketConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ new testchipip.WithBackingScratchpad ++ // add backing scratchpad - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -372,7 +355,6 @@ class RingSystemBusRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index 0c74b5819a..e149bd230c 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -29,7 +29,6 @@ class TutorialStarterConfig extends Config( // Config fragments below this line affect hardware generation // of the Top new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core - new chipyard.config.WithNoGPIO ++ // Disable GPIOs. new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op new chipyard.config.WithUART ++ // Add a UART @@ -65,7 +64,6 @@ class TutorialMMIOConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ @@ -93,7 +91,6 @@ class TutorialSha3Config extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ @@ -119,7 +116,6 @@ class TutorialSha3BlackBoxConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 3e35a94d46..c1dee8234c 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 3e35a94d46d88506d5b14b2c34f05b8651844452 +Subproject commit c1dee8234c23c8fc454108e59ecba20987f95cde From 43f6083b692b4e6c23edd3863f89307eecd13826 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 5 May 2020 14:57:54 -0700 Subject: [PATCH 064/153] Many changes to begin the compilation with RC-1.3 Cores now have an extra CoreParam, useSupervisor which was set to the default false. Whether a core has supervisor mode is the union of this and useVM which defaults true so not change was made by this addition. BusTopologies are now set with the Config system rather than a system mixin and so all configs now include the config most similar to the previous mixin Testchipip was updated to be able to replace the systembus, in this new config system, with a ring bus. The L2 cache repo needed a similar update on how to find the buses. It currently points to the ucb-bar fork Treadle is bumped to its release branch --- .gitmodules | 2 +- generators/ariane | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/System.scala | 1 - .../src/main/scala/config/ArianeConfigs.scala | 2 ++ .../src/main/scala/config/BoomConfigs.scala | 8 ++++++++ .../src/main/scala/config/HeteroConfigs.scala | 7 +++++++ .../src/main/scala/config/RocketConfigs.scala | 19 +++++++++++++++++++ .../main/scala/config/TracegenConfigs.scala | 5 +++++ .../main/scala/config/TutorialConfigs.scala | 4 ++++ generators/sifive-cache | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/System.scala | 1 - tools/treadle | 2 +- 14 files changed, 51 insertions(+), 8 deletions(-) diff --git a/.gitmodules b/.gitmodules index 34846d6195..b331ae3f5b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -33,7 +33,7 @@ url = https://github.com/firesim/icenet.git [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache - url = https://github.com/sifive/block-inclusivecache-sifive.git + url = https://github.com/ucb-bar/block-inclusivecache-sifive.git [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] path = toolchains/riscv-tools/riscv-gnu-toolchain url = https://github.com/riscv/riscv-gnu-toolchain.git diff --git a/generators/ariane b/generators/ariane index f4ba64a624..1086f90223 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit f4ba64a624091600e9d7d40c293b8d5c17f47c56 +Subproject commit 1086f90223bc03be6d46d019fcce10d6c27f5c12 diff --git a/generators/boom b/generators/boom index 90911dde1b..79c0e5583c 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 90911dde1b8730f10c958d172f26f72d718be5ae +Subproject commit 79c0e5583c37128e8e22591b264f5a7eed605b9a diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 6d99ca6a6a..222ff77cb3 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -22,7 +22,6 @@ import freechips.rocketchip.util.{DontTouch} * Base top with periphery devices and ports, and a BOOM + Rocket subsystem */ class System(implicit p: Parameters) extends Subsystem - with HasHierarchicalBusTopology with HasAsyncExtInterrupts with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 6dfb4c74a9..6fb2ef00f3 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -22,6 +22,7 @@ class ArianeConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new ariane.WithNArianeCores(1) ++ // single Ariane core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class dmiArianeConfig extends Config( @@ -37,4 +38,5 @@ class dmiArianeConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new ariane.WithNArianeCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 4c1943682e..48a9126e0b 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -22,6 +22,7 @@ class SmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new boom.common.WithSmallBooms ++ // small boom config new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class MediumBoomConfig extends Config( @@ -40,6 +41,7 @@ class MediumBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithMediumBooms ++ // medium boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class LargeBoomConfig extends Config( @@ -58,6 +60,7 @@ class LargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ // large boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class MegaBoomConfig extends Config( @@ -76,6 +79,7 @@ class MegaBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithMegaBooms ++ // mega boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class DualSmallBoomConfig extends Config( @@ -94,6 +98,7 @@ class DualSmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithSmallBooms ++ new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class SmallRV32BoomConfig extends Config( @@ -114,6 +119,7 @@ class SmallRV32BoomConfig extends Config( new boom.common.WithBoomRV32 ++ // rv32 (32bit) new boom.common.WithSmallBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class HwachaLargeBoomConfig extends Config( @@ -133,6 +139,7 @@ class HwachaLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class LoopbackNICLargeBoomConfig extends Config( @@ -153,5 +160,6 @@ class LoopbackNICLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index 11835aa4d8..4388ca2bb6 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -24,6 +24,7 @@ class LargeBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include start: BoomAndRocketWithHwacha @@ -46,6 +47,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: BoomAndRocketWithHwacha @@ -67,6 +69,7 @@ class DualLargeBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: DualBoomAndRocketOneHwacha @@ -91,6 +94,7 @@ class LargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocketOneHwacha @@ -115,6 +119,7 @@ class LargeBoomAndRV32RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -137,6 +142,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocket @@ -159,5 +165,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 4058fcf4f1..ac29c662d3 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -21,6 +21,7 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class HwachaRocketConfig extends Config( @@ -39,6 +40,7 @@ class HwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GemminiRocketConfig @@ -58,6 +60,7 @@ class GemminiRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GemminiRocketConfig @@ -77,6 +80,7 @@ class RoccRocketConfig extends Config( new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: JtagRocket @@ -96,6 +100,7 @@ class jtagRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: JtagRocket @@ -114,6 +119,7 @@ class dmiRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DmiRocket @@ -134,6 +140,7 @@ class GCDTLRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDTLRocketConfig @@ -154,6 +161,7 @@ class GCDAXI4BlackBoxRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig @@ -174,6 +182,7 @@ class SimBlockDeviceRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class BlockDeviceModelRocketConfig extends Config( @@ -193,6 +202,7 @@ class BlockDeviceModelRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GPIORocketConfig @@ -213,6 +223,7 @@ class GPIORocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GPIORocketConfig @@ -231,6 +242,7 @@ class QuadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( @@ -248,6 +260,7 @@ class RV32RocketConfig extends Config( new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class GB1MemoryRocketConfig extends Config( @@ -266,6 +279,7 @@ class GB1MemoryRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: Sha3Rocket @@ -285,6 +299,7 @@ class Sha3RocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: Sha3Rocket @@ -305,6 +320,7 @@ class InitZeroRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: InitZeroRocketConfig @@ -325,6 +341,7 @@ class LoopbackNICRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: scratchpadrocket @@ -344,6 +361,7 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: scratchpadrocket @@ -364,5 +382,6 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index fefa271dcf..2a31293ffb 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -8,6 +8,7 @@ class TraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenConfig extends Config( @@ -15,6 +16,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class BoomTraceGenConfig extends Config( @@ -23,6 +25,7 @@ class BoomTraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2Config extends Config( @@ -31,6 +34,7 @@ class NonBlockingTraceGenL2Config extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2RingConfig extends Config( @@ -40,4 +44,5 @@ class NonBlockingTraceGenL2RingConfig extends Config( new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index e149bd230c..c11d103d28 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -50,6 +50,7 @@ class TutorialStarterConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 // BaseConfig configures "bare" rocketchip system new freechips.rocketchip.system.BaseConfig ) @@ -79,6 +80,7 @@ class TutorialMMIOConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) @@ -104,6 +106,7 @@ class TutorialSha3Config extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) @@ -130,5 +133,6 @@ class TutorialSha3BlackBoxConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) diff --git a/generators/sifive-cache b/generators/sifive-cache index d3d95ece5a..9ac1a5242d 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit d3d95ece5a570b423892bede4fed6cb0030c7701 +Subproject commit 9ac1a5242d1fcbb16495f0289d329be35b28370c diff --git a/generators/testchipip b/generators/testchipip index cec2c0b6d6..8fbd4f43b6 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cec2c0b6d66c3df05d08462167bb8a58c0912d06 +Subproject commit 8fbd4f43b6351a7e2eeb27b6096cf4e81aa72bf7 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index cb5d0af8c5..1653ba796c 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -41,7 +41,6 @@ trait HasTraceGenTilesModuleImp extends LazyModuleImp { class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem with HasTraceGenTiles - with HasHierarchicalBusTopology with CanHaveMasterAXI4MemPort { override lazy val module = new TraceGenSystemModuleImp(this) } diff --git a/tools/treadle b/tools/treadle index a03b969af1..6ca4fec611 160000 --- a/tools/treadle +++ b/tools/treadle @@ -1 +1 @@ -Subproject commit a03b969af104770a7662ecdbac80cebf622e674b +Subproject commit 6ca4fec6117b58a58e628f55c3eac46d4b15d03a From a255417513180ab4e4f53ee20b964e9eac701674 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 5 May 2020 15:24:51 -0700 Subject: [PATCH 065/153] Update stage to use Dependency instead of classof --- .../src/main/scala/stage/ChipyardStage.scala | 34 +++++++++---------- .../scala/stage/phases/AddDefaultTests.scala | 8 ++--- .../phases/GenerateTestSuiteMakefrags.scala | 6 ++-- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala index a24afd43bf..4e429618c9 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -10,27 +10,27 @@ import firrtl.stage.FirrtlCli import freechips.rocketchip.stage.RocketChipCli import freechips.rocketchip.system.RocketChipStage -import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain} +import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency} import firrtl.options.phases.DeletedWrapper class ChipyardStage extends ChiselStage with PreservesAll[Phase] { override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli override val targets: Seq[PhaseDependency] = Seq( - classOf[freechips.rocketchip.stage.phases.Checks], - classOf[freechips.rocketchip.stage.phases.TransformAnnotations], - classOf[freechips.rocketchip.stage.phases.PreElaboration], - classOf[chisel3.stage.phases.Checks], - classOf[chisel3.stage.phases.Elaborate], - classOf[freechips.rocketchip.stage.phases.GenerateROMs], - classOf[chisel3.stage.phases.AddImplicitOutputFile], - classOf[chisel3.stage.phases.AddImplicitOutputAnnotationFile], - classOf[chisel3.stage.phases.MaybeAspectPhase], - classOf[chisel3.stage.phases.Emitter], - classOf[chisel3.stage.phases.Convert], - classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[freechips.rocketchip.stage.phases.AddDefaultTests], - classOf[chipyard.stage.phases.AddDefaultTests], - classOf[chipyard.stage.phases.GenerateTestSuiteMakefrags], - classOf[freechips.rocketchip.stage.phases.GenerateArtefacts], + Dependency[freechips.rocketchip.stage.phases.Checks], + Dependency[freechips.rocketchip.stage.phases.TransformAnnotations], + Dependency[freechips.rocketchip.stage.phases.PreElaboration], + Dependency[chisel3.stage.phases.Checks], + Dependency[chisel3.stage.phases.Elaborate], + Dependency[freechips.rocketchip.stage.phases.GenerateROMs], + Dependency[chisel3.stage.phases.AddImplicitOutputFile], + Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile], + Dependency[chisel3.stage.phases.MaybeAspectPhase], + Dependency[chisel3.stage.phases.Emitter], + Dependency[chisel3.stage.phases.Convert], + Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[freechips.rocketchip.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], + Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts], ) } diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 277d04b532..fce5d43294 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -10,7 +10,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3.stage.phases.Elaborate import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll} +import firrtl.options.{Phase, PreservesAll, Dependency} import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} @@ -23,9 +23,9 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). override val prerequisites = Seq( - classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[freechips.rocketchip.stage.phases.AddDefaultTests]) - override val dependents = Seq(classOf[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) + Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[freechips.rocketchip.stage.phases.AddDefaultTests]) + override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { val annotations = mutable.ArrayBuffer[Annotation]() diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala index 76f99ab774..0ed5ec1130 100644 --- a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -7,7 +7,7 @@ import scala.collection.mutable import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable} +import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency} import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} @@ -24,8 +24,8 @@ case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotat class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { // Our annotations tend not to be serializable, but are not marked as such. - override val prerequisites = Seq(classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[chipyard.stage.phases.AddDefaultTests]) + override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[chipyard.stage.phases.AddDefaultTests]) override def transform(annotations: AnnotationSeq): AnnotationSeq = { val targetDir = view[StageOptions](annotations).targetDir From 006ecd2b7c9e6f13a9067b5c7b2b67293dcad809 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 6 May 2020 21:46:25 +0000 Subject: [PATCH 066/153] Basic changes to barstools to get sim to compile --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index e230e8cf3f..02ffbd78b9 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit e230e8cf3f7c0bc3c958cab22c5d90d195ca6b01 +Subproject commit 02ffbd78b9a69e94edd22280da3d80f12b70fb22 From 3c18880064d9bb8d719dfa0d82204cbbf5b287c7 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 6 May 2020 18:39:42 -0700 Subject: [PATCH 067/153] Increase verilator reset length --- generators/utilities/src/main/resources/csrc/emulator.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 0e86b83665..acec6005f3 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -283,7 +283,7 @@ int main(int argc, char** argv) bool dump; // reset for several cycles to handle pipelined reset - for (int i = 0; i < 10; i++) { + for (int i = 0; i < 100; i++) { tile->reset = 1; tile->clock = 0; tile->eval(); From 596925020f97b10e822247f21444622ee0a74221 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 7 May 2020 11:24:17 -0700 Subject: [PATCH 068/153] Connect debug clocks when debug is tied off --- generators/chipyard/src/main/scala/IOBinders.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 281c5917ba..ea0f610b3b 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -256,8 +256,9 @@ class WithTiedOffDebug extends OverrideIOBinder({ Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p) // tieoffDebug doesn't actually tie everything off :/ debugPortOpt.foreach { d => - d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) + d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.clock }) d.dmactiveAck := DontCare + d.clock := th.clock } Nil } From 0bdf39ffe43791bbff07d47b06983ad66b1749c4 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 9 May 2020 04:21:49 +0000 Subject: [PATCH 069/153] [SBT] Hush up scalasbt resolver http complaint --- project/plugins.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/plugins.sbt b/project/plugins.sbt index d8d00e3513..8de7108106 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,4 +1,4 @@ -resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) +resolvers += Resolver.url("scalasbt", new URL("https://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) resolvers += Classpaths.sbtPluginReleases resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" From 2fa9a41902d2ac0c2df767be4663a924291c7199 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 11 May 2020 03:46:03 +0000 Subject: [PATCH 070/153] [make] Fix firrtl prerequiste lookup --- common.mk | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index b5a5bb072c..ddb2a35595 100644 --- a/common.mk +++ b/common.mk @@ -16,8 +16,9 @@ include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk ######################################################################################### -# variables to get all *.scala files +# Prerequisite lists ######################################################################################### +# Returns a list of files in directory $1 with file extension $2. lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) @@ -36,7 +37,7 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class ######################################################################################### FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -$(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) +$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala mkdir -p $(@D) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ @@ -45,7 +46,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) ######################################################################################### # create list of simulation file inputs ######################################################################################### -$(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR) +$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" ######################################################################################### From 2a6bd3bd5c6f8bf0147ae65433d15ba91eeb4bad Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Mon, 11 May 2020 23:02:37 -0700 Subject: [PATCH 071/153] Bump verilator to v4.034 (#547) * Bump verilator to v4.034 * Add new flags to verilator makefile * Conditionally set timescale flag based on Verilator version --- .circleci/defaults.sh | 2 +- .circleci/images/Dockerfile | 2 +- scripts/centos-req.sh | 2 +- scripts/ubuntu-req.sh | 2 +- sims/verilator/Makefile | 3 +++ 5 files changed, 7 insertions(+), 4 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 38da902bdc..3420a1a2d9 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -21,7 +21,7 @@ clean () { NPROC=8 # verilator version -VERILATOR_VERSION=v4.028 +VERILATOR_VERSION=v4.034 # remote variables REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB diff --git a/.circleci/images/Dockerfile b/.circleci/images/Dockerfile index 807c15f060..3efb4cc972 100644 --- a/.circleci/images/Dockerfile +++ b/.circleci/images/Dockerfile @@ -164,7 +164,7 @@ RUN apt-get install -y \ # Install verilator RUN git clone http://git.veripool.org/git/verilator \ && cd verilator \ - && git checkout v4.028 \ + && git checkout v4.034 \ && autoconf && ./configure && make && make install # Update PATH for Java tools diff --git a/scripts/centos-req.sh b/scripts/centos-req.sh index 30b9fe70dc..89e8644c36 100755 --- a/scripts/centos-req.sh +++ b/scripts/centos-req.sh @@ -22,5 +22,5 @@ sudo yum install -y dtc # install verilator git clone http://git.veripool.org/git/verilator cd verilator -git checkout v4.028 +git checkout v4.034 autoconf && ./configure && make -j16 && sudo make install diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index ee541e81ce..f72c48f4cc 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -23,5 +23,5 @@ sudo apt-get install -y device-tree-compiler # install verilator git clone http://git.veripool.org/git/verilator cd verilator -git checkout v4.028 +git checkout v4.034 autoconf && ./configure && make -j16 && sudo make install diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 432169d652..fd7f1bd6e5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -86,7 +86,10 @@ ARIANE_VERILATOR_FLAGS = \ CHIPYARD_VERILATOR_FLAGS = \ --assert +# Use --timescale to approximate timescale behavior of pre-4.034 +TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }') VERILATOR_NONCC_OPTS = \ + $(TIMESCALE_OPTS) \ --top-module $(VLOG_MODEL) \ $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ --output-split 10000 \ From d16c57867d162fcf47feda65f0a61ac7ff0c290c Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 12 May 2020 22:00:43 +0000 Subject: [PATCH 072/153] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index d5d4f4d6f8..e7bc535160 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit d5d4f4d6f8cf5a499fee5365eec9eec794bbd08c +Subproject commit e7bc535160e5887b7d642fcddcb1479dfcd98463 From 6950ad7cee715e6e935dcb67a9794a031af9ddf8 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 12 May 2020 22:01:14 +0000 Subject: [PATCH 073/153] Comment out Ariane from ScalaTests --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index c5af5cda7e..cf2358d9f7 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -141,9 +141,9 @@ class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimL class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } -class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { - runSuite("verilator")(NICLoopbackTests) -} +//class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { +// runSuite("verilator")(NICLoopbackTests) +//} // Disabled until RAM optimizations re-enabled in multiclock //class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") //class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") From 933d03356902cf37b68f664af2d0ffcec69401dc Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 12 May 2020 23:34:01 -0700 Subject: [PATCH 074/153] sifive cache bump to RC firrtl 1.3 --- .gitmodules | 2 +- generators/sifive-cache | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index b331ae3f5b..34846d6195 100644 --- a/.gitmodules +++ b/.gitmodules @@ -33,7 +33,7 @@ url = https://github.com/firesim/icenet.git [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache - url = https://github.com/ucb-bar/block-inclusivecache-sifive.git + url = https://github.com/sifive/block-inclusivecache-sifive.git [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] path = toolchains/riscv-tools/riscv-gnu-toolchain url = https://github.com/riscv/riscv-gnu-toolchain.git diff --git a/generators/sifive-cache b/generators/sifive-cache index 9ac1a5242d..4ebefa3e30 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 9ac1a5242d1fcbb16495f0289d329be35b28370c +Subproject commit 4ebefa3e30ec44bd2f4ff82747025fb7b362b954 From 9e95082a8a6484c911b497a061100fdb3d030aae Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 00:10:23 -0700 Subject: [PATCH 075/153] bump testchipip with buffer arg --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 8fbd4f43b6..5b3f2c9654 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8fbd4f43b6351a7e2eeb27b6096cf4e81aa72bf7 +Subproject commit 5b3f2c9654d4cb06a64e8ac5df864c706a07bda8 From f0389bbe66b36c6441ed9c3c3e3e67e724d6ae07 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 10:03:30 -0700 Subject: [PATCH 076/153] bump boom and ariane to master with RC firrtl 1.3 --- generators/ariane | 2 +- generators/boom | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/ariane b/generators/ariane index 1086f90223..66cbcd0115 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 1086f90223bc03be6d46d019fcce10d6c27f5c12 +Subproject commit 66cbcd0115f8f4e2abb38684532ec945622adcae diff --git a/generators/boom b/generators/boom index 79c0e5583c..d0077cff74 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 79c0e5583c37128e8e22591b264f5a7eed605b9a +Subproject commit d0077cff74140153e314f05f631c5e07b0d694ea From d5c1ad4c1f75058e5f2150501074417fba3ef976 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 13 May 2020 10:38:23 -0700 Subject: [PATCH 077/153] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 02ffbd78b9..c4e5f66c5e 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 02ffbd78b9a69e94edd22280da3d80f12b70fb22 +Subproject commit c4e5f66c5e795c744b7f3be2780f7f2bb15e9e23 From afb6518ec2f65080c54a6a899e69245697539f25 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 10:40:02 -0700 Subject: [PATCH 078/153] bump barstools to master with firrtl 1.3 --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 02ffbd78b9..c4e5f66c5e 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 02ffbd78b9a69e94edd22280da3d80f12b70fb22 +Subproject commit c4e5f66c5e795c744b7f3be2780f7f2bb15e9e23 From de617d16edfd1fb509998a7395d99c34696458a2 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 11:31:40 -0700 Subject: [PATCH 079/153] bump firesim with firrtl 1.3 --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index e7bc535160..6482be6d2e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e7bc535160e5887b7d642fcddcb1479dfcd98463 +Subproject commit 6482be6d2e435392815f5e24631b5644787e3467 From 3fc205997f24a54c0d5cb436457949e805e7f939 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 11:41:21 -0700 Subject: [PATCH 080/153] bump treadle to master --- tools/treadle | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/treadle b/tools/treadle index 6ca4fec611..1c67bc846a 160000 --- a/tools/treadle +++ b/tools/treadle @@ -1 +1 @@ -Subproject commit 6ca4fec6117b58a58e628f55c3eac46d4b15d03a +Subproject commit 1c67bc846aafc3bdd707f76ead8cefd5f93e0376 From 460455e79084811be7e35ded7b772cbb178d4b18 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 13 May 2020 13:18:06 -0700 Subject: [PATCH 081/153] extend midas examples timeout in ci --- .circleci/config.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index ff691e41dd..4d849e77b6 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -341,6 +341,7 @@ jobs: - run: name: Run midasexamples tests command: .circleci/run-midasexamples-tests.sh + no_output_timeout: 20m chipyard-ariane-run-tests: executor: main-env steps: From ebe993cefeab6bd6bff6481e6bb09f460e47b478 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 14 May 2020 03:09:39 +0000 Subject: [PATCH 082/153] Assemble the firrt-test.jar and put it in its own directory --- build.sbt | 2 +- common.mk | 7 +++++++ sims/firesim | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index b0e8c84daf..a87496c99a 100644 --- a/build.sbt +++ b/build.sbt @@ -2,7 +2,7 @@ import Tests._ // This gives us a nicer handle to the root project instead of using the // implicit one -lazy val chipyardRoot = RootProject(file(".")) +lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val commonSettings = Seq( organization := "edu.berkeley.cs", diff --git a/common.mk b/common.mk index ddb2a35595..e9248953b6 100644 --- a/common.mk +++ b/common.mk @@ -36,6 +36,7 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class # jar creation variables and rules ######################################################################################### FIRRTL_JAR := $(base_dir)/lib/firrtl.jar +FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar $(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala @@ -43,6 +44,12 @@ $(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ touch $@ +$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) + cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly" + mkdir -p $(@D) + cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ + touch $@ + ######################################################################################### # create list of simulation file inputs ######################################################################################### diff --git a/sims/firesim b/sims/firesim index 6482be6d2e..4ec7325ac6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6482be6d2e435392815f5e24631b5644787e3467 +Subproject commit 4ec7325ac60d3dd5862798cabb823e446040b90e From 7c7b336c3fef8aaf16a7266d95b3fbd9e7d9418b Mon Sep 17 00:00:00 2001 From: John Wright Date: Thu, 14 May 2020 19:19:50 -0700 Subject: [PATCH 083/153] Add SPI flash support (#546) * Add SPI flash configs, IOBinders, CI tests, and docs * Add writable SPI flash support * bump * Fix CI * Fix CI * Update docs/Generators/TestChipIP.rst Co-authored-by: Chick Markley * Maybe actually fix CI * Fix broken merge * Fix the tutorial patch * bump tcip to master * fix GPIO naming bug Co-authored-by: Chick Markley --- .circleci/config.yml | 40 +++- .circleci/defaults.sh | 2 + .circleci/images/Dockerfile | 26 ++- .circleci/run-tests.sh | 9 + docs/Generators/TestChipIP.rst | 8 + .../src/main/scala/ConfigFragments.scala | 7 + .../chipyard/src/main/scala/DigitalTop.scala | 2 + .../chipyard/src/main/scala/IOBinders.scala | 46 ++++- .../src/main/scala/config/RocketConfigs.scala | 40 ++++ generators/testchipip | 2 +- .../src/main/resources/csrc/emulator.cc | 8 +- .../RocketConfigs.scala.patch | 4 +- tests/.gitignore | 1 + tests/Makefile | 9 +- tests/spiflash.h | 174 ++++++++++++++++++ tests/spiflash.py | 11 ++ tests/spiflashread.c | 77 ++++++++ tests/spiflashwrite.c | 55 ++++++ 18 files changed, 505 insertions(+), 16 deletions(-) create mode 100644 tests/spiflash.h create mode 100755 tests/spiflash.py create mode 100644 tests/spiflashread.c create mode 100644 tests/spiflashwrite.c diff --git a/.circleci/config.yml b/.circleci/config.yml index 4d849e77b6..8e88f7eb65 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -12,7 +12,7 @@ parameters: executors: main-env: docker: - - image: ucbbar/chipyard-image:1.0.0 + - image: ucbbar/chipyard-image:1.0.1 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit @@ -262,6 +262,16 @@ jobs: steps: - prepare-rtl: project-key: "testchipip" + prepare-chipyard-spiflashwrite: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-spiflashwrite" + prepare-chipyard-spiflashread: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-spiflashread" chipyard-rocket-run-tests: executor: main-env steps: @@ -300,6 +310,16 @@ jobs: - run-tests: tools-version: "esp-tools" project-key: "chipyard-gemmini" + chipyard-spiflashwrite-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-spiflashwrite" + chipyard-spiflashread-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-spiflashread" tracegen-run-tests: executor: main-env steps: @@ -464,6 +484,16 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-spiflashwrite: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-spiflashread: + requires: + - install-riscv-toolchain + - install-verilator + # Run the respective tests # Run midasexamples test @@ -508,6 +538,14 @@ workflows: requires: - prepare-tracegen-boom + - chipyard-spiflashwrite-run-tests: + requires: + - prepare-chipyard-spiflashwrite + + - chipyard-spiflashread-run-tests: + requires: + - prepare-chipyard-spiflashread + # Run the firesim tests - firesim-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 3420a1a2d9..e944e7fddd 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -52,6 +52,8 @@ mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConf mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" +mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRocketConfig" +mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig" mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" diff --git a/.circleci/images/Dockerfile b/.circleci/images/Dockerfile index 3efb4cc972..7d03185026 100644 --- a/.circleci/images/Dockerfile +++ b/.circleci/images/Dockerfile @@ -13,6 +13,8 @@ RUN apt-get update \ git \ gnupg \ gzip \ + libfl2 \ + libfl-dev \ locales \ mercurial \ netcat \ @@ -24,7 +26,12 @@ RUN apt-get update \ unzip \ wget \ xvfb \ - zip + xxd \ + zip \ + ccache \ + libgoogle-perftools-dev \ + numactl \ + zlib1g # Set timezone to UTC by default RUN ln -sf /usr/share/zoneinfo/Etc/UTC /etc/localtime @@ -127,34 +134,46 @@ RUN apt-get install -y --no-install-recommends openjfx RUN apt-get install -y build-essential # Add RISCV toolchain necessary dependencies +RUN apt-get update RUN apt-get install -y \ autoconf \ automake \ autotools-dev \ babeltrace \ bc \ - bison \ curl \ device-tree-compiler \ expat \ flex \ gawk \ gperf \ + g++ \ libexpat-dev \ libgmp-dev \ libmpc-dev \ libmpfr-dev \ libtool \ libusb-1.0-0-dev \ + make \ patchutils \ pkg-config \ python \ - python-pexpect \ + python-pexpect-doc \ python3 \ texinfo \ zlib1g-dev \ rsync +# Use specific bison version to bypass Verilator 4.034 issues +# TODO: When Verilator is bumped, use apt to get newest bison +RUN wget https://ftp.gnu.org/gnu/bison/bison-3.5.4.tar.gz \ + && tar -xvf bison-3.5.4.tar.gz \ + && cd bison-3.5.4 \ + && ./configure && make && make install + +# Check bison version is 3.5.4 +RUN bison --version + # Add minimal QEMU dependencies RUN apt-get install -y \ libfdt-dev \ @@ -164,6 +183,7 @@ RUN apt-get install -y \ # Install verilator RUN git clone http://git.veripool.org/git/verilator \ && cd verilator \ + && git pull \ && git checkout v4.034 \ && autoconf && ./configure && make && make install diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 5f3056172a..c77941739b 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -62,6 +62,15 @@ case $1 in (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv ;; + chipyard-spiflashread) + make -C $LOCAL_CHIPYARD_DIR/tests + make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary + ;; + chipyard-spiflashwrite) + make -C $LOCAL_CHIPYARD_DIR/tests + make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary + [[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false + ;; tracegen) run_tracegen ${mapping[$1]} ;; diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 31f9ce536b..363e324598 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -84,3 +84,11 @@ output a UART log to a particular file using ``+uartlog=`` during By default, this UART Adapter is added to all systems within Chipyard by adding the ``WithUART`` and ``WithUARTAdapter`` configs. + +SPI Flash Model +--------------- + +The SPI flash model is a device that models a simple SPI flash device. It currently +only supports single read, quad read, single write, and quad write instructions. The +memory is backed by a file which is provided using ``+spiflash#=``, +where ``#`` is the SPI flash ID (usually ``0``). diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 2db12ff799..c2fec56f10 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -20,6 +20,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} @@ -52,6 +53,12 @@ class WithUART extends Config((site, here, up) => { UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) }) +class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { + // Note: the default size matches freedom with the addresses below + case PeripherySPIFlashKey => Seq( + SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) +}) + class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( core = tile.core.copy(nL2TLBEntries = entries) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index c7b3d49733..e8fb4f4cac 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -19,6 +19,7 @@ class DigitalTop(implicit p: Parameters) extends System with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs + with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget @@ -32,6 +33,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l) with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index ea0f610b3b..97cc0ba957 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ import barstools.iocell.chisel._ @@ -88,10 +89,8 @@ object AddIOCells { def gpio(gpios: Seq[GPIOPortIO], genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[Seq[Analog]], Seq[Seq[IOCell]]) = { gpios.zipWithIndex.map({ case (gpio, i) => gpio.pins.zipWithIndex.map({ case (pin, j) => - val g = IO(Analog(1.W)) - g.suggestName("gpio_${i}_${j}") - val iocell = genFn() - iocell.suggestName(s"iocell_gpio_${i}_${j}") + val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}") + val iocell = genFn().suggestName(s"iocell_gpio_${i}_${j}") iocell.io.o := pin.o.oval iocell.io.oe := pin.o.oe iocell.io.ie := pin.o.ie @@ -115,6 +114,37 @@ object AddIOCells { }).unzip } + /** + * Add IO cells to a SiFive SPI devices and name the IO ports. + * @param spiPins A Seq of SPI port bundles + * @param basename The base name for this port (defaults to "spi") + * @param genFn A callable function to generate a DigitalGPIOCell module to use + * @return Returns a tuple of (A Seq of top-level SPIChipIO IOs; a 2D Seq of IOCell module references) + */ + def spi(spiPins: Seq[SPIPortIO], basename: String = "spi", genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[SPIChipIO], Seq[Seq[IOCell]]) = { + spiPins.zipWithIndex.map({ case (s, i) => + val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"${basename}_${i}") + val iocellBase = s"iocell_${basename}_${i}" + + // SCK and CS are unidirectional outputs + val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck")) + val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs")) + + // DQ are bidirectional, so then need special treatment + val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) => + val iocell = genFn().suggestName(s"${iocellBase}_dq_${j}") + iocell.io.o := pin.o + iocell.io.oe := pin.oe + iocell.io.ie := true.B + pin.i := iocell.io.i + iocell.io.pad <> ana + iocell + } + + (port, dqIOs ++ csIOs ++ sckIOs) + }).unzip + } + /** * Add IO cells to a debug module and name the IO ports. * @param psd A PSDIO bundle @@ -172,6 +202,14 @@ class WithUARTAdapter extends OverrideIOBinder({ } }) +class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ + (system: HasPeripherySPIFlashModuleImp) => { + val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") + val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil } + Seq((ports, ioCells2d.flatten, Some(harnessFn))) + } +}) + class WithSimBlockDevice extends OverrideIOBinder({ (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectSimBlockDevice(system.clock, system.reset.asBool); Nil }) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index ac29c662d3..49d223851b 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -165,6 +165,46 @@ class GCDAXI4BlackBoxRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig +class LargeSPIFlashROMRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithSPIFlash ++ // add the SPI flash controller + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class SmallSPIFlashRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB) + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ diff --git a/generators/testchipip b/generators/testchipip index 5b3f2c9654..888a4547ad 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 5b3f2c9654d4cb06a64e8ac5df864c706a07bda8 +Subproject commit 888a4547adbf6387da7fb79c85f2f75cdcca6534 diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index acec6005f3..6ff63d3ead 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -38,8 +38,8 @@ extern remote_bitbang_t * jtag; extern int dramsim; static uint64_t trace_count = 0; -bool verbose; -bool done_reset; +bool verbose = false; +bool done_reset = false; void handle_sigterm(int sig) { @@ -282,6 +282,10 @@ int main(int argc, char** argv) signal(SIGTERM, handle_sigterm); bool dump; + // start reset off low so a rising edge triggers async reset + tile->reset = 0; + tile->clock = 0; + tile->eval(); // reset for several cycles to handle pipelined reset for (int i = 0; i < 100; i++) { tile->reset = 1; diff --git a/scripts/tutorial-patches/RocketConfigs.scala.patch b/scripts/tutorial-patches/RocketConfigs.scala.patch index eca5596d82..af383b0f55 100644 --- a/scripts/tutorial-patches/RocketConfigs.scala.patch +++ b/scripts/tutorial-patches/RocketConfigs.scala.patch @@ -1,8 +1,8 @@ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -index bc1dab6..1d84129 100644 +index 49d2238..afaa36d 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -@@ -293,7 +293,7 @@ class Sha3RocketConfig extends Config( +@@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/tests/.gitignore b/tests/.gitignore index b8212fd8bf..5cbdb5a956 100644 --- a/tests/.gitignore +++ b/tests/.gitignore @@ -1,4 +1,5 @@ *.o *.riscv *.dump +*.img libgloss/ diff --git a/tests/Makefile b/tests/Makefile index 6f247e7028..8754cbbc8d 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -5,12 +5,15 @@ LDFLAGS= -static include libgloss.mk -PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd +PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd spiflashread spiflashwrite + +spiflash.img: spiflash.py + python3 $< .DEFAULT_GOAL := default .PHONY: default -default: $(addsuffix .riscv,$(PROGRAMS)) +default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img .PHONY: dumps dumps: $(addsuffix .dump,$(PROGRAMS)) @@ -18,7 +21,7 @@ dumps: $(addsuffix .dump,$(PROGRAMS)) %.o: %.S $(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@ -%.o: %.c mmio.h +%.o: %.c mmio.h spiflash.h $(GCC) $(CFLAGS) -c $< -o $@ %.riscv: %.o $(libgloss) diff --git a/tests/spiflash.h b/tests/spiflash.h new file mode 100644 index 0000000000..94b27e361d --- /dev/null +++ b/tests/spiflash.h @@ -0,0 +1,174 @@ +#ifndef __SPIFLASH_H__ +#define __SPIFLASH_H__ + +// These are configuration-dependent, but for the unit test we'll use the example config +#define SPIFLASH_BASE_MEM 0x20000000 +#define SPIFLASH_BASE_MEM_SIZE 0x10000000 + +#define SPIFLASH_BASE_CTRL 0x10040000 +// Only defining the registers we use; there are more +// Software control +#define SPIFLASH_OFFS_CSMODE 0x18 +#define SPIFLASH_OFFS_FMT 0x40 +#define SPIFLASH_OFFS_TXDATA 0x48 +#define SPIFLASH_OFFS_RXDATA 0x4c +// Hardware state machine control +#define SPIFLASH_OFFS_FLASH_EN 0x60 +#define SPIFLASH_OFFS_FFMT 0x64 + +// chip select modes +#define CSMODE_AUTO 0 +#define CSMODE_HOLD 2 +#define CSMODE_OFF 3 + +// SPI flash protocol settings +#define SPIFLASH_PROTO_SINGLE 0 +#define SPIFLASH_PROTO_DUAL 1 +#define SPIFLASH_PROTO_QUAD 2 + +// SPI flash IO settings +#define SPIFLASH_IODIR_RX 0 +#define SPIFLASH_IODIR_TX 1 + +// SPI flash endianness settings +#define SPIFLASH_ENDIAN_MSB 0 +#define SPIFLASH_ENDIAN_LSB 1 + +static uint8_t test_data[] = {0x13,0x37,0x00,0xff,0xaa,0x55,0xfa,0xce,0x0f,0xf0,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef}; +static uint8_t test_len = 16; + +typedef union +{ + struct { + unsigned int proto : 2; + unsigned int endian : 1; + unsigned int iodir : 1; + unsigned int : 12; + unsigned int len : 4; + unsigned int : 12; + } fields; + uint32_t bits; +} spi_fmt; + +typedef union +{ + struct { + unsigned int cmd_en : 1; + unsigned int addr_len : 3; + unsigned int pad_cnt : 4; + unsigned int cmd_proto : 2; + unsigned int addr_proto : 2; + unsigned int data_proto : 2; + unsigned int : 2; + unsigned int cmd_code : 8; + unsigned int pad_code : 8; + } fields; + uint32_t bits; +} spiflash_ffmt; + +// send something to the SPI TX +void spi_data_write(uint8_t data) +{ + while (reg_read32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA) >= 0x80000000); + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA, (uint32_t)data); +} + +// configure the hardware flash controller +void configure_spiflash(spiflash_ffmt data) +{ + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0); + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FFMT, data.bits); + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1); +} + +// write some data to the flash using software (there is no hardware write controller) +void write_spiflash(uint8_t *data, uint32_t len, uint32_t addr, uint8_t cmd, uint8_t abytes, uint8_t aproto, uint8_t dproto) +{ + + spi_fmt fmt; + fmt.fields.proto = SPIFLASH_PROTO_SINGLE; + fmt.fields.endian = SPIFLASH_ENDIAN_MSB; + fmt.fields.iodir = SPIFLASH_IODIR_TX; + fmt.fields.len = 8; + + uint32_t i; + + // Need to be out of flash mode + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0); + + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits); + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_HOLD); + + spi_data_write(cmd); + + // need to wait a bit to flush the tx queue before changing fmt + for(i = 0; i < 0x100; i++) asm volatile ("nop"); + + fmt.fields.proto = aproto; + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits); + + for (i = abytes; i > 0; i--) + { + spi_data_write((uint8_t)(addr >> (i*8-8))); + } + + // need to wait a bit to flush the tx queue before changing fmt + for(i = 0; i < 0x100; i++) asm volatile ("nop"); + + fmt.fields.proto = dproto; + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits); + + for (i = 0; i < len; i++) + { + spi_data_write(data[i]); + } + + // need to wait a bit to flush the tx queue before deasserting CS + for(i = 0; i < 0x100; i++) asm volatile ("nop"); + + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_OFF); + + // go back into flash read mode + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1); + +} + +// test that a large chunk of memory contains (0xdeadbeef - address) or 0 +int test_spiflash(uint32_t start, uint32_t size, uint8_t zero) +{ + uint32_t i; + + for (i = start; i < (start + size); i += 4) + { + uint32_t data = reg_read32(SPIFLASH_BASE_MEM + i); + uint32_t check = 0; + if (!zero) check = 0xdeadbeef - i; + if(data != check) + { + printf("Error reading address 0x%08x from SPI flash. Got 0x%08x, expected 0x%08x.\n", i, data, check); + return 1; + } + } + + return 0; +} + +// this is a variant of test_spiflash that only tests a small array of values +int check_write(uint8_t *check, uint32_t len, uint32_t addr) +{ + uint32_t i; + for (i = 0; i < len; i += 4) + { + uint32_t data = reg_read32(SPIFLASH_BASE_MEM + addr + i); + uint32_t check32 = ((uint32_t *)check)[i/4]; + if(check32 != data) + { + printf("Error reading address 0x%08x from SPI flash. Got 0x%02x, expected 0x%02x.\n", i + addr, data, check32); + return 1; + } + } + + return 0; +} + +#endif /* __SPIFLASH_H__ */ diff --git a/tests/spiflash.py b/tests/spiflash.py new file mode 100755 index 0000000000..126cf1be9c --- /dev/null +++ b/tests/spiflash.py @@ -0,0 +1,11 @@ +#!/usr/bin/env python3 + +# Generates a binary file that the SPI test uses + +outfile = "spiflash.img" + +with open(outfile, 'wb') as f: + for i in range(0,0x100000,4): + check = 0xdeadbeef - i + f.write(check.to_bytes(4,'little')) + diff --git a/tests/spiflashread.c b/tests/spiflashread.c new file mode 100644 index 0000000000..393faa558d --- /dev/null +++ b/tests/spiflashread.c @@ -0,0 +1,77 @@ +#include +#include + +#include "mmio.h" +#include "spiflash.h" + +int main(void) +{ + spiflash_ffmt ffmt; + ffmt.fields.cmd_en = 1; + ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model + ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow + ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands + ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad + ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad + ffmt.fields.cmd_code = 0x13; // Slow read 4 byte + ffmt.fields.pad_code = 0x00; // Not used by our model + + printf("Testing SPI flash command 0x13...\n"); + configure_spiflash(ffmt); + if (test_spiflash(0x0, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x03...\n"); + ffmt.fields.cmd_code = 0x03; // Slow read 3 byte address + ffmt.fields.addr_len = 3; // 3 byte address + configure_spiflash(ffmt); + if (test_spiflash(0x0, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x0B...\n"); + ffmt.fields.cmd_code = 0x0B; // Fast read 3 byte address + ffmt.fields.pad_cnt = 8; // Needs to be 8 for fast read + configure_spiflash(ffmt); + if (test_spiflash(0x1000, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x0C...\n"); + ffmt.fields.cmd_code = 0x0C; // Fast read 4 byte address + ffmt.fields.addr_len = 4; // 4 byte address + configure_spiflash(ffmt); + if (test_spiflash(0x2340, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x6C...\n"); + ffmt.fields.cmd_code = 0x6C; // Fast read 4 byte address, quad data + ffmt.fields.data_proto = SPIFLASH_PROTO_QUAD; // Quad data + configure_spiflash(ffmt); + if (test_spiflash(0x410c, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x6B...\n"); + ffmt.fields.cmd_code = 0x6B; // Fast read 3 byte address, quad data + ffmt.fields.addr_len = 3; + configure_spiflash(ffmt); + if (test_spiflash(0x5ff8, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0xEB...\n"); + ffmt.fields.cmd_code = 0xEB; // Fast read 3 byte address, quad data, quad addr + ffmt.fields.addr_proto = SPIFLASH_PROTO_QUAD; + configure_spiflash(ffmt); + if (test_spiflash(0x7c04, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0xEC...\n"); + ffmt.fields.cmd_code = 0xEC; // Fast read 4 byte address, quad data, quad addr + ffmt.fields.addr_len = 4; + configure_spiflash(ffmt); + if (test_spiflash(0x9000, 0x100, 0)) return 1; + + printf("Testing SPI flash extended range...\n"); + // The provided memory image is only 1MiB, but the model has 16MiB of addressable space + // This should return 0 + if (test_spiflash(0x100000, 0x100, 1)) return 1; + + // This write should do nothing, so we can just re-test the first test + printf("Testing that the SPI is not writable...\n"); + write_spiflash(test_data, test_len, 0x0, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD); + if (test_spiflash(0x0, 0x100, 0)) return 1; + + return 0; + +} diff --git a/tests/spiflashwrite.c b/tests/spiflashwrite.c new file mode 100644 index 0000000000..f9c176053c --- /dev/null +++ b/tests/spiflashwrite.c @@ -0,0 +1,55 @@ +#include +#include + +#include "mmio.h" +#include "spiflash.h" + +int main(void) +{ + spiflash_ffmt ffmt; + ffmt.fields.cmd_en = 1; + ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model + ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow + ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands + ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad + ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad + ffmt.fields.cmd_code = 0x13; // Slow read 4 byte + ffmt.fields.pad_code = 0x00; // Not used by our model + + // Test that we can read + printf("Testing SPI flash command 0x13...\n"); + configure_spiflash(ffmt); + if (test_spiflash(0x0, 0x100, 0)) return 1; + + // 0x02: 3 byte addr, single/single + printf("Testing SPI flash command 0x02...\n"); + write_spiflash(test_data, test_len, 0x200, 0x02, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE); + if (check_write(test_data, test_len, 0x200)) return 1; + + // 0x32: 3 byte addr, single/quad + printf("Testing SPI flash command 0x32...\n"); + write_spiflash(test_data, test_len, 0x300, 0x32, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD); + if (check_write(test_data, test_len, 0x300)) return 1; + + // 0x38: 3 byte addr, quad/quad + printf("Testing SPI flash command 0x38...\n"); + write_spiflash(test_data, test_len, 0x400, 0x38, 3, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD); + if (check_write(test_data, test_len, 0x400)) return 1; + + // 0x12: 4 byte addr, single/single + printf("Testing SPI flash command 0x12...\n"); + write_spiflash(test_data, test_len, 0x500, 0x12, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE); + if (check_write(test_data, test_len, 0x500)) return 1; + + // 0x34: 4 byte addr, single/quad + printf("Testing SPI flash command 0x34...\n"); + write_spiflash(test_data, test_len, 0x600, 0x34, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD); + if (check_write(test_data, test_len, 0x600)) return 1; + + // 0x3E: 4 byte addr, quad/quad + printf("Testing SPI flash command 0x3E...\n"); + write_spiflash(test_data, test_len, 0x700, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD); + if (check_write(test_data, test_len, 0x700)) return 1; + + return 0; +} From 3f5a204fd0f7b280001e6a950430740c8542f9a6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 16 May 2020 00:21:24 -0700 Subject: [PATCH 084/153] BOOM Bump w. Fromajo (#523) * [uart] add uart adapter | add uart + adapter to all configs * [uart] change pty define name | add uart to all configs that need it * [uart] default to 115200 baudrate * [dromajo] first working commit * [dromajo] bump boom for commit-width > 1 fix * [dromajo] adjust dromajo commits * [dromajo] bump boom * commit dromajo changes * extra * [dromajo] add block device to configs * rebump older modules * bump firesim * [chipyard] enable dromajo in midas level simulation * [testchipip] forgot to bump * get rid of breaking things * bump firesim * bump boom * Bump BOOM to ifu3 WIP * bump firesim * fix how memory is passed to dromajo * bump boom and firesim * fix merge issues * add dromajo cosim bridge in chipyard * move traceio back into testchipip (#488) * refer to testchipip traceio in firechip (#490) * Move TraceIO fragment to chipyard (#492) * fix chipyard dromajo bridge (#493) * Sboom dromajo bump (#501) * [FireChip] Use clock in BridgeBinders * [firesim] Update TraceGen BridgeBinder * [Firechip] Add support for Tile <-> Uncore rational division * [firesim] Update the multiclock test * [firechip] Commit some Eagle X-related mock configs * [firechip] Instantiate multiple TracerV bridges * [Firechip] Include reset in tracerv tokens * [TracerV] Drop the first token in comparison tests * [Firechip] Make reverse instruction order in trace printf * WARNING: Point at a fork of boom @ davidbiancolin * [firesim] Update ClockBridge API * Add Gemmini to README [ci skip] (#487) * [firechip] Isolate all firesim-multiclock stuff in a single file * add documentation on ring network and system bus * Bump firesim for CI * Bump FireSim * Bump testchipip to dev [ci skip] * Bump FireSim * [make] split up specific make vars/targets into frags (#499) * [make] split up specific make vars/targets into frags * [make] move dramsim and max-cycles into SIM_FLAGS * [misc] move ariane configs to configs/ folder * [dromajo] add dromajo * [dromajo] bump for new traceio changes * bump firesim * bump firesim * point to chipyard traceio * bump boom Co-authored-by: David Biancolin Co-authored-by: Howard Mao * Support Dromajo + TracerV configurations * [docs] add documentation for Dromajo in FireSim + Chipyard * add a bit more docs * [docs] bump docs * [firesim] dump artefacts in firesim * [firesim] update firesim * [testchipip] remove extraneous items in testchipip * [dromajo] prevent dromajo from breaking when params unset * update firesim, dromajo, and testchipip * [firesim] bump firesim * [firesim] bump firesim * [misc] bump firesim and testchipip for reviewer comments * remove WithNoGPIO fragment * bump firesim * bump dromajo boom config * bump firesim * generate artefacts in firesim testsuite Co-authored-by: abejgonzalez Co-authored-by: Abraham Gonzalez Co-authored-by: David Biancolin Co-authored-by: Howard Mao --- .circleci/run-firesim-scala-tests.sh | 2 + .circleci/run-midasexamples-tests.sh | 4 ++ .gitmodules | 3 + build.sbt | 2 +- common.mk | 1 + docs/Advanced-Concepts/Debugging-RTL.rst | 25 +++++++- docs/Chipyard-Basics/Chipyard-Components.rst | 4 ++ docs/Tools/Dromajo.rst | 22 +++++++ docs/Tools/index.rst | 2 +- generators/boom | 2 +- .../src/main/scala/ConfigFragments.scala | 8 ++- .../chipyard/src/main/scala/IOBinders.scala | 8 +++ .../chipyard/src/main/scala/Subsystem.scala | 25 ++++++++ .../src/main/scala/config/BoomConfigs.scala | 21 +++++++ .../src/main/scala/BridgeBinders.scala | 17 ++++-- .../firechip/src/main/scala/FireSim.scala | 1 + .../src/main/scala/FireSimMulticlockPOC.scala | 1 + .../src/main/scala/TargetConfigs.scala | 10 +--- .../src/test/scala/ScalaTestSuite.scala | 3 +- generators/testchipip | 2 +- generators/tracegen/src/main/scala/Tile.scala | 13 +++- scripts/build-toolchains.sh | 3 + sims/firesim | 2 +- tools/dromajo/dromajo-src | 1 + tools/dromajo/dromajo.mk | 59 +++++++++++++++++++ 25 files changed, 217 insertions(+), 24 deletions(-) create mode 100644 docs/Tools/Dromajo.rst create mode 160000 tools/dromajo/dromajo-src create mode 100644 tools/dromajo/dromajo.mk diff --git a/.circleci/run-firesim-scala-tests.sh b/.circleci/run-firesim-scala-tests.sh index 93c4561db5..3e2bb87f76 100755 --- a/.circleci/run-firesim-scala-tests.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -22,6 +22,8 @@ cd $LOCAL_CHIPYARD_DIR/sims/firesim ./scripts/build-libdwarf.sh cd $LOCAL_CHIPYARD_DIR +make -C $LOCAL_CHIPYARD_DIR/tools/dromajo/dromajo-src/src + # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh index 467dc0e9f9..092d011ee9 100755 --- a/.circleci/run-midasexamples-tests.sh +++ b/.circleci/run-midasexamples-tests.sh @@ -12,6 +12,10 @@ trap clean EXIT cd $LOCAL_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh + +# build libdromajo_cosim +make -C $LOCAL_CHIPYARD_DIR/tools/dromajo/dromajo-src/src + cd sims/firesim/sim/midas # set stricthostkeychecking to no (must happen before rsync) diff --git a/.gitmodules b/.gitmodules index 34846d6195..04f1a20e9e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -119,3 +119,6 @@ [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git +[submodule "tools/dromajo/dromajo-src"] + path = tools/dromajo/dromajo-src + url = https://github.com/abejgonzalez/dromajo.git diff --git a/build.sbt b/build.sbt index a87496c99a..8cf8e6887d 100644 --- a/build.sbt +++ b/build.sbt @@ -147,7 +147,7 @@ lazy val hwacha = (project in file("generators/hwacha")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val boom = (project in file("generators/boom")) +lazy val boom = conditionalDependsOn(project in file("generators/boom")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/common.mk b/common.mk index e9248953b6..991a8db684 100644 --- a/common.mk +++ b/common.mk @@ -14,6 +14,7 @@ SHELL=/bin/bash ######################################################################################### include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk +include $(base_dir)/tools/dromajo/dromajo.mk ######################################################################################### # Prerequisite lists diff --git a/docs/Advanced-Concepts/Debugging-RTL.rst b/docs/Advanced-Concepts/Debugging-RTL.rst index df1c1c5586..86e5ced30f 100644 --- a/docs/Advanced-Concepts/Debugging-RTL.rst +++ b/docs/Advanced-Concepts/Debugging-RTL.rst @@ -86,9 +86,32 @@ identical program behavior. The torture utility can also be configured to run continuously for stress-testing. The torture utility exists within the ``utilities`` directory. +Dromajo Co-simulation for BOOM designs +-------------------------------------- +Dromajo co-simulation is setup to work when two config. fragments are added to a BOOM config. +First, a ``chipyard.config.WithTraceIO`` config. fragment must be added so that BOOM's traceport is enabled. +Second, a ``chipyard.iobinders.WithSimDromajoBridge`` config. fragment must be added to +connect the Dromajo co-simulator to the traceport. +Once both config. fragments are added Dromajo should be enabled. + +To build/run Dromajo with a BOOM design, run your configuration the following make commands: + +.. code-block:: shell + + # build the default Dromajo BOOM config. without waveform dumps + # replace "DromajoBoomConfig" with your particular config + make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 + + # run a simulation with Dromajo + make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY= run-binary + +.. warning:: Dromajo currently only works in single-core BOOM systems without accelerators. + +.. warning:: Dromajo currently only works in VCS simulation and FireSim. + Firesim Debugging --------------------------- -Chisel printfs, asserts, and waveform generation are also available in FireSim +Chisel printfs, asserts, Dromajo co-simulation, and waveform generation are also available in FireSim FPGA-accelerated simulation. See the FireSim `documentation `__ for more detail. diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index d3ec9a9513..7a89e93a80 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -79,6 +79,10 @@ Tools **Dsptools** A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). +**Dromajo** + A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technology. + See :ref:`Dromajo` for more information. + Toolchains ------------------------------------------- diff --git a/docs/Tools/Dromajo.rst b/docs/Tools/Dromajo.rst new file mode 100644 index 0000000000..2266bac1cb --- /dev/null +++ b/docs/Tools/Dromajo.rst @@ -0,0 +1,22 @@ +Dromajo +=============================== + +`Dromajo `__ is a RV64GC functional simulator designed for co-simulation. +To use it as a co-simulator, it requires you to pass the committed trace of instructions coming from the core into the tool. +Within Chipyard, this is done by connecting to the `TracePort`` signals that are piped to the top level of the DUT. +While the Rocket core does have a `TracePort`, it does not provide the committed write data that Dromajo requires. +Thus, Dromajo uses the `ExtendedTracePort` only probided by BOOM (BOOM is the only core that supports Dromajo co-simulation). +An example of a divergence and Dromajo's printout is shown below. + +.. code-block:: shell + + [error] EMU PC ffffffe001055d84, DUT PC ffffffe001055d84 + [error] EMU INSN 14102973, DUT INSN 14102973 + [error] EMU WDATA 00000000000220d6, DUT WDATA 00000000000220d4 + [error] EMU MSTATUS a000000a0, DUT MSTATUS 00000000 + [error] DUT pending exception -1 pending interrupt -1 + +Dromajo shows the divergence compared to simulation (PC, inst, inst-bits, write data, etc) and also provides the register state on failure. +It is useful to catch bugs that affect architectural state before a simulation hangs or crashes. + +To use Dromajo with BOOM, refer to :ref:`Debugging RTL` section on Dromajo. diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index 09fd0d04b0..fecb204350 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -14,4 +14,4 @@ The following pages will introduce them, and how we can use them in order to gen Chisel-Testers Dsptools Barstools - + Dromajo diff --git a/generators/boom b/generators/boom index d0077cff74..8c4ac6fd40 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit d0077cff74140153e314f05f631c5e07b0d694ea +Subproject commit 8c4ac6fd40b455387cec369080b9b47d6fd1466e diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index c2fec56f10..69cedb6f1b 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import freechips.rocketchip.util.{AsyncResetReg} import boom.common.{BoomTilesKey} - +import ariane.{ArianeTilesKey} import testchipip._ import hwacha.{Hwacha} @@ -153,3 +153,9 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) + +class WithTraceIO extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) + case TracePortKey => Some(TracePortParams()) +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 97cc0ba957..4c27a65aca 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -351,4 +351,12 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ } }) +class WithSimDromajoBridge extends ComposeIOBinder({ + (system: CanHaveTraceIOModuleImp) => { + system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } + Nil + } +}) + + } /* end package object */ diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 8fe0871bcc..4dfa7d7382 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -104,4 +104,29 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule // create file with boom params ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) + + // Generate C header with relevant information for Dromajo + // THIS IS INCLUDED IN THE `dromajo_params.h` header file + var dromajoParams: String = "" + dromajoParams += "#ifndef DROMAJO_PARAMS_H" + dromajoParams += "\n#define DROMAJO_PARAMS_H" + dromajoParams += "\n\n" + "#define DROMAJO_RESET_VECTOR " + "\"" + "0x" + f"${p(BootROMParams).hang}%X" + "\"" + dromajoParams += "\n" + "#define DROMAJO_MMIO_START " + "\"" + "0x" + f"${p(BootROMParams).address + p(BootROMParams).size}%X" + "\"" + p(ExtMem) map { eP => + dromajoParams += "\n" + "#define DROMAJO_MMIO_END " + "\"" + "0x" + f"${eP.master.base}%X" + "\"" + // dromajo memory is in MiB chunks + dromajoParams += "\n" + "#define DROMAJO_MEM_SIZE " + "\"" + "0x" + f"${eP.master.size >> 20}%X" + "\"" + } + p(PLICKey) map { pP => + dromajoParams += "\n" + "#define DROMAJO_PLIC_BASE " + "\"" + "0x" + f"${pP.baseAddress}%X" + "\"" + dromajoParams += "\n" + "#define DROMAJO_PLIC_SIZE " + "\"" + "0x" + f"${PLICConsts.size(pP.maxHarts)}%X" + "\"" + } + p(CLINTKey) map { cP => + dromajoParams += "\n" + "#define DROMAJO_CLINT_BASE " + "\"" + "0x" + f"${cP.baseAddress}%X" + "\"" + dromajoParams += "\n" + "#define DROMAJO_CLINT_SIZE " + "\"" + "0x" + f"${CLINTConsts.size}%X" + "\"" + } + dromajoParams += "\n\n#endif" + + ElaborationArtefacts.add("""dromajo_params.h""", dromajoParams) + } diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 48a9126e0b..e8358e957f 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -163,3 +163,24 @@ class LoopbackNICLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) +class DromajoBoomConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimDromajoBridge ++ // attach Dromajo + new testchipip.WithTSI ++ + new chipyard.config.WithTraceIO ++ // enable the traceio + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithSmallBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 043f1f4ebf..772d0b8d35 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} -import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp} +import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp} import icenet.CanHavePeripheryIceNICModuleImp import junctions.{NastiKey, NastiParameters} @@ -27,7 +27,8 @@ import ariane.ArianeTile import boom.common.{BoomTile} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} -import chipyard.HasChipyardTilesModuleImp +import chipyard.{HasChipyardTilesModuleImp} +import testchipip.{CanHaveTraceIOModuleImp} object MainMemoryConsts { val regionNamePrefix = "MainMemory" @@ -72,12 +73,20 @@ class WithFASEDBridge extends OverrideIOBinder({ } }) -class WithTracerVBridge extends OverrideIOBinder({ +class WithTracerVBridge extends ComposeIOBinder({ (system: CanHaveTraceIOModuleImp) => system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil }) + +class WithDromajoBridge extends ComposeIOBinder({ + (system: CanHaveTraceIOModuleImp) => { + system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil + } +}) + + class WithTraceGenBridge extends OverrideIOBinder({ (system: HasTraceGenTilesModuleImp) => GroundTestBridge(system.clock, system.success)(system.p); Nil @@ -116,7 +125,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) // tieoffDebug doesn't actually tie everything off :/ - system.debug.foreach { d => + system.debug.foreach { d => d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) d.dmactiveAck := DontCare } diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 923e1cd128..50f6f658fe 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -45,6 +45,7 @@ class FireSim(implicit val p: Parameters) extends RawModule { })) (lazyModule, Module(lazyModule.module)) } + val peekPokeBridge = PeekPokeBridge(clock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's LazyModule class instance diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index fdc2939faa..758cb05539 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -79,6 +79,7 @@ class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop override lazy val module = new FiresimMulticlockTopModule(this) } + class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp // Harness Definition diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 63199c0efa..1a0dcd696e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -73,13 +73,6 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) -// Enables tracing on all cores -class WithTraceIO extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) - case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) - case TracePortKey => Some(TracePortParams()) -}) - // Tweaks that are generally applied to all firesim configs class WithFireSimConfigTweaks extends Config( @@ -92,7 +85,7 @@ class WithFireSimConfigTweaks extends Config( // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) new WithoutTLMonitors ++ // Optional: Adds IO to attach tracerV bridges - new WithTraceIO ++ + new chipyard.config.WithTraceIO ++ // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1) new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible @@ -143,7 +136,6 @@ class FireSimLargeBoomConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.LargeBoomConfig) - //******************************************************************** // Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig //******************************************************************** diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index cf2358d9f7..3ab4162ce8 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -75,7 +75,7 @@ abstract class FireSimTestSuite( case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv" case _ => "" } - val results = suite.names.toSeq sliding (N, N) map { t => + val results = suite.names.toSeq sliding (N, N) map { t => val subresults = t map (name => Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) Await result (Future sequence subresults, Duration.Inf) @@ -130,6 +130,7 @@ abstract class FireSimTestSuite( mkdirs elaborate generateTestSuiteMakefrags + generateArtefacts runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) diff --git a/generators/testchipip b/generators/testchipip index 888a4547ad..e43e818f44 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 888a4547adbf6387da7fb79c85f2f75cdcca6534 +Subproject commit e43e818f443764cb1a1bdaa243b5adc795083217 diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 28974e1ba9..d395211fc5 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -86,7 +86,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) io.lsu.dis_uops(0).valid := io.tracegen.req.fire() io.lsu.dis_uops(0).bits := tracegen_uop - + when (io.tracegen.req.fire()) { rob_tail := WrapInc(rob_tail, rob_sz) rob_bsy(rob_tail) := true.B @@ -165,8 +165,15 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) io.lsu.rob_pnr_idx := rob_tail io.lsu.commit_load_at_rob_head := false.B - io.lsu.brinfo := DontCare - io.lsu.brinfo.valid := false.B + io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.exu.BrUpdateMasks) + io.lsu.brupdate.b2.uop := DontCare + io.lsu.brupdate.b2.mispredict := false.B + io.lsu.brupdate.b2.taken := false.B + io.lsu.brupdate.b2.cfi_type := 0.U + io.lsu.brupdate.b2.pc_sel := 0.U + io.lsu.brupdate.b2.jalr_target := 0.U + io.lsu.brupdate.b2.target_offset := 0.S(2.W) + io.lsu.rob_head_idx := rob_head diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index b5d767c04d..cbe1516182 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -130,6 +130,9 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu +# make Dromajo +make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src + cd "$RDIR" # create specific env.sh diff --git a/sims/firesim b/sims/firesim index 4ec7325ac6..4e94c1a013 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4ec7325ac60d3dd5862798cabb823e446040b90e +Subproject commit 4e94c1a0131dc673f894c62f9a110637844a806a diff --git a/tools/dromajo/dromajo-src b/tools/dromajo/dromajo-src new file mode 160000 index 0000000000..56e2ff46b7 --- /dev/null +++ b/tools/dromajo/dromajo-src @@ -0,0 +1 @@ +Subproject commit 56e2ff46b70521916c362799517f4ed8e67e9e88 diff --git a/tools/dromajo/dromajo.mk b/tools/dromajo/dromajo.mk new file mode 100644 index 0000000000..067faa2f96 --- /dev/null +++ b/tools/dromajo/dromajo.mk @@ -0,0 +1,59 @@ +############################################################## +# extra variables/targets ingested by the chipyard make system +############################################################## + +DROMAJO_DIR = $(base_dir)/tools/dromajo/dromajo-src/src +DROMAJO_LIB_NAME = dromajo_cosim +DROMAJO_LIB = $(DROMAJO_DIR)/lib$(DROMAJO_LIB_NAME).a + +# Dromajo assumes using the default bootrom +DROMAJO_ROM = $(base_dir)/bootrom/bootrom.rv64.img + +DTS_FILE = $(build_dir)/$(long_name).dts +DROMAJO_DTB = $(build_dir)/$(long_name).dtb + +$(DTS_FILE): $(FIRRTL_FILE) + +$(DROMAJO_DTB): $(DTS_FILE) + dtc -I dts -O dtb -o $(DROMAJO_DTB) $(DTS_FILE) + +DROMAJO_SRCS = $(call lookup_srcs,$(DROMAJO_DIR),cc) $(call lookup_srcs,$(DROMAJO_DIR),h) + +$(DROMAJO_LIB): $(DROMAJO_SRCS) + $(MAKE) -C $(DROMAJO_DIR) + +# depending on where the simulation is done, use the auto-variable or the hardcoded defined one +ifeq ($(BINARY),) +DROMAJO_BIN = $(<) +else +DROMAJO_BIN = $(BINARY) +endif + +DROMAJO_FLAGS = +drj_dtb=$(DROMAJO_DTB) +drj_rom=$(DROMAJO_ROM) +drj_bin=$(DROMAJO_BIN) + +DROMAJO_PARAMS_FILE = $(build_dir)/$(long_name).dromajo_params.h +DROMAJO_PARAMS_SYMLINK = $(build_dir)/dromajo_params.h + +$(DROMAJO_PARAMS_FILE): $(FIRRTL_FILE) + +$(DROMAJO_PARAMS_SYMLINK): $(DROMAJO_PARAMS_FILE) + rm -rf $(DROMAJO_PARAMS_SYMLINK) + ln -s $(DROMAJO_PARAMS_FILE) $(DROMAJO_PARAMS_SYMLINK) + +################################################################## +# THE FOLLOWING MUST BE += operators +################################################################## + +# simargs needed (i.e. like +drj_test=hello) +ifdef ENABLE_DROMAJO +EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS) + +# CC flags needed for all simulations +EXTRA_SIM_CC_FLAGS += -I$(DROMAJO_DIR) + +# sourced needed for simulation +EXTRA_SIM_SOURCES += $(DROMAJO_LIB) + +# requirements needed for simulation +EXTRA_SIM_REQS += $(DROMAJO_PARAMS_SYMLINK) $(DROMAJO_LIB) $(DROMAJO_DTB) +endif From 85b555dbcefba32ce286c133951b47cf85faf63c Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 16 May 2020 12:22:30 -0700 Subject: [PATCH 085/153] NVDLA Integration + Cleanup Ariane Preprocessing (#505) * [nvdla] initial nvdla integration * [nvdla] add firesim configs * [nvdla] re-add accidentally deleted line * [nvdla] works on master with small * [nvdla] use master branch of nvdla * [nvdla] remove extra sources * [nvdla] bump * [nvdla + ariane] bump and use insert-includes for pre-processing * [nvdla] add ci | remove target configs in FireChip | update naming * [nvdla] bump nvdla | fix ci run-tests error * [nvdla] re-enable PCWM-L error | fix/update makefile(s) * [nvdla] bump nvdla fragments in FireChip * [misc] bump tutorial patches * [chipyard] remove extra import * [nvdla] bump nvdla for pbus [ci skip] * [nvdla] update firemarshal and add nvdla workload * [nvdla] bump nvdla-workload * [nvdla] bump hw * [docs] add basic documentation * [docs] adjustments to documentation * [misc] update docs | bump firesim with recipe * [misc] disable error on warnings in verilator | bump number width to match RC * [docs] fix doc build error * [verilator] move no fail on warning to be global * [ci skip] [nvdla] bump submodule urls * [misc] move firesim specific configs into nvdla dir [ci skip] * [nvdla] fix run-tests in ci * update RC configs | bump marshal | bump nvdla-workload * [nvdla] bump nvdla-workload [ci skip] * add topology mixin to nvdla configs * update tutorial patches --- .circleci/config.yml | 18 + .circleci/defaults.sh | 1 + .circleci/run-tests.sh | 4 + .gitmodules | 6 + README.md | 3 +- build.sbt | 6 +- common.mk | 1 + docs/Generators/NVDLA.rst | 16 + docs/Generators/index.rst | 1 + generators/ariane | 2 +- .../src/main/scala/ConfigFragments.scala | 7 - .../chipyard/src/main/scala/DigitalTop.scala | 1 + .../src/main/scala/config/RocketConfigs.scala | 38 + .../src/main/scala/TargetConfigs.scala | 7 +- generators/nvdla | 1 + scripts/insert-includes.py | 51 + .../RocketConfigs.scala.patch | 2 +- scripts/tutorial-patches/build.sbt.patch | 8 +- sims/vcs/Makefile | 8 +- sims/verilator/Makefile | 3 +- software/firemarshal | 2 +- software/nvdla-workload | 1 + tests/Makefile | 2 +- tests/nvdla.c | 468 ++ tests/nvdla.h | 6433 +++++++++++++++++ 25 files changed, 7063 insertions(+), 27 deletions(-) create mode 100644 docs/Generators/NVDLA.rst create mode 160000 generators/nvdla create mode 100755 scripts/insert-includes.py create mode 160000 software/nvdla-workload create mode 100644 tests/nvdla.c create mode 100644 tests/nvdla.h diff --git a/.circleci/config.yml b/.circleci/config.yml index 8e88f7eb65..5361a9449b 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -262,6 +262,11 @@ jobs: steps: - prepare-rtl: project-key: "testchipip" + prepare-chipyard-nvdla: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-nvdla" prepare-chipyard-spiflashwrite: executor: main-env steps: @@ -368,6 +373,11 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" + chipyard-nvdla-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-nvdla" icenet-run-tests: executor: main-env steps: @@ -484,6 +494,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-nvdla: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-spiflashwrite: requires: - install-riscv-toolchain @@ -567,6 +582,9 @@ workflows: requires: - prepare-chipyard-ariane + - chipyard-nvdla-run-tests: + requires: + - prepare-chipyard-nvdla - icenet-run-tests: requires: - prepare-icenet diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e944e7fddd..d9699df8e5 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -56,6 +56,7 @@ mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRo mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig" mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" +mapping["chipyard-nvdla"]="SUB_PROJECT=chipyard CONFIG=SmallNVDLARocketConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index c77941739b..19a0e566c6 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -80,6 +80,10 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; + chipyard-nvdla) + make -C $LOCAL_CHIPYARD_DIR/tests + make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary + ;; icenet) make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]} ;; diff --git a/.gitmodules b/.gitmodules index 04f1a20e9e..cae791ddc2 100644 --- a/.gitmodules +++ b/.gitmodules @@ -119,6 +119,12 @@ [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git +[submodule "generators/nvdla"] + path = generators/nvdla + url = https://github.com/ucb-bar/nvdla-wrapper.git +[submodule "software/nvdla-workload"] + path = software/nvdla-workload + url = https://github.com/ucb-bar/nvdla-workload.git [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src url = https://github.com/abejgonzalez/dromajo.git diff --git a/README.md b/README.md index 8d4cccc526..5d44edb375 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. @@ -65,3 +65,4 @@ These publications cover many of the internal components used in Chipyard. Howev [firemarshal]: https://github.com/firesim/FireMarshal/ [ariane]: https://github.com/pulp-platform/ariane/ [gemmini]: https://github.com/ucb-bar/gemmini +[nvdla]: http://nvdla.org/ diff --git a/build.sbt b/build.sbt index 8cf8e6887d..17fdbba5ff 100644 --- a/build.sbt +++ b/build.sbt @@ -129,7 +129,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches - gemmini, icenet, tracegen, ariane) + gemmini, icenet, tracegen, ariane, nvdla) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -163,6 +163,10 @@ lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) .settings(commonSettings) +lazy val nvdla = (project in file("generators/nvdla")) + .dependsOn(rocketchip) + .settings(commonSettings) + lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) .dependsOn(chisel_testers, chipyard) .settings(commonSettings) diff --git a/common.mk b/common.mk index 991a8db684..f07342de41 100644 --- a/common.mk +++ b/common.mk @@ -14,6 +14,7 @@ SHELL=/bin/bash ######################################################################################### include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk +include $(base_dir)/generators/nvdla/nvdla.mk include $(base_dir)/tools/dromajo/dromajo.mk ######################################################################################### diff --git a/docs/Generators/NVDLA.rst b/docs/Generators/NVDLA.rst new file mode 100644 index 0000000000..d3e8528670 --- /dev/null +++ b/docs/Generators/NVDLA.rst @@ -0,0 +1,16 @@ +NVDLA +==================================== + +`NVDLA `_ is an open-source deep learning accelerator developed by NVIDIA. +The `NVDLA` is attached as a TileLink peripheral so it can be used as a component within the `Rocket Chip SoC generator`. +The accelerator by itself exposes an AXI memory interface (or two if you use the "Large" configuration), a control interface, and an interrupt line. +The main way to use the accelerator in Chipyard is to use the `NVDLA SW repository `_ that was ported to work on FireSim Linux. +However, you can also use the accelerator in baremetal simulations (refer to ``tests/nvdla.c``). + +For more information on both the HW architecture and the SW, please visit their `website `_. + +NVDLA Software with FireMarshal +------------------------------- + +Located at ``software/nvdla-workload`` is a FireMarshal-based workload to boot Linux with the proper NVDLA drivers. +Refer to that ``README.md`` for more information on how to run a simulation. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 675318d934..be9c5e5588 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -28,4 +28,5 @@ so changes to the generators themselves will automatically be used when building SiFive-Generators SHA3 Ariane + NVDLA diff --git a/generators/ariane b/generators/ariane index 66cbcd0115..d914fc8f03 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 66cbcd0115f8f4e2abb38684532ec945622adcae +Subproject commit d914fc8f0320ba5b087d515b25baf98959b0facb diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 69cedb6f1b..72eaa414b4 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -72,7 +72,6 @@ class WithTracegenSystem extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) }) - class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length)) @@ -83,12 +82,6 @@ class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) }) - - -// ------------------ -// Multi-RoCC Support -// ------------------ - /** * Map from a hartId to a particular RoCC accelerator */ diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index e8fb4f4cac..a61594f2d7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -23,6 +23,7 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget + with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { override lazy val module = new DigitalTopModule(this) } diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 49d223851b..f29c5804f7 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -425,3 +425,41 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket + +class SmallNVDLARocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class LargeNVDLARocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 1a0dcd696e..63b4d2feaf 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -44,14 +44,12 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) }) - class WithPerfCounters extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( core = tile.core.copy(nPerfCounters = 29) )) }) - // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) @@ -63,7 +61,6 @@ class WithScalaTestFeatures extends Config((site, here, up) => { case TracePortKey => up(TracePortKey, site).map(_.copy(print = true)) }) - // FASED Config Aliases. This to enable config generation via "_" concatenation // which requires that all config classes be defined in the same package class DDR3FRFCFS extends FRFCFS16GBQuadRank @@ -71,7 +68,9 @@ class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) - +// Adds a small/large NVDLA to the system +class WithNVDLALarge extends nvidia.blocks.dla.WithNVDLA("large") +class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small") // Tweaks that are generally applied to all firesim configs diff --git a/generators/nvdla b/generators/nvdla new file mode 160000 index 0000000000..b2b78c9f89 --- /dev/null +++ b/generators/nvdla @@ -0,0 +1 @@ +Subproject commit b2b78c9f892a6196634eb3f1fbc443436c897a00 diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py new file mode 100755 index 0000000000..1e8a43ac4c --- /dev/null +++ b/scripts/insert-includes.py @@ -0,0 +1,51 @@ +#!/usr/bin/python + +# replaces a `include with the full include file +# +# args +# $1 - file to remove includes from +# $2 - file to write output to +# $3 - list of directories to search for includes in (note: NON-RECURSIVE must specify all dirs) +# includes are found relative to this path +# this is equivalent to something like +incdir+ + +import sys +import re +import os + +inVlog = sys.argv[1] +outVlog = sys.argv[2] +print("[INFO] Replaces includes from: " + str(inVlog)) + +if inVlog == outVlog: + sys.exit("[ERROR] The input and output file cannot be the same.") + +# add directories to search list +incDirs = sys.argv[3:] +print("[INFO] Searching following dirs for includes: " + str(incDirs)) + +# open file +with open(inVlog, 'r') as inFile: + with open(outVlog, 'w') as outFile: + # for each include found, search through all dirs and replace if found, error if not + for num, line in enumerate(inFile, 1): + match = re.match(r"^ *`include +\"(.*)\"", line) + if match: + # search for include and replace + found = False + for d in incDirs: + potentialIncFileName = d + "/" + match.group(1) + if os.path.exists(potentialIncFileName): + found = True + with open(potentialIncFileName, 'r') as incFile: + for iline in incFile: + outFile.write(iline) + break + + # must find something to include with + if not found: + sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num)) + else: + outFile.write(line) + +print("[INFO] Success. Writing output to: " + str(outVlog)) diff --git a/scripts/tutorial-patches/RocketConfigs.scala.patch b/scripts/tutorial-patches/RocketConfigs.scala.patch index af383b0f55..cc9910c746 100644 --- a/scripts/tutorial-patches/RocketConfigs.scala.patch +++ b/scripts/tutorial-patches/RocketConfigs.scala.patch @@ -1,5 +1,5 @@ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -index 49d2238..afaa36d 100644 +index f29c580..0bd36ca 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config( diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 6f20a3cecf..40e773fe6e 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,17 +1,17 @@ diff --git a/build.sbt b/build.sbt -index a633066..3df8b74 100644 +index 0c4581f..ff0597c 100644 --- a/build.sbt +++ b/build.sbt -@@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) +@@ -128,7 +128,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches - gemmini, icenet, tracegen, ariane) + gemmini, icenet, tracegen, ariane, nvdla) .settings(commonSettings) -@@ -151,9 +151,9 @@ lazy val ariane = (project in file("generators/ariane")) +@@ -155,9 +155,9 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index f5b7e5dbae..80e5a1a8e7 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -55,18 +55,16 @@ VCS_CC_OPTS = \ VCS_NONCC_OPTS = \ +lint=all,noVCDE,noONGS,noUI \ - -error=PCWM-L \ -timescale=1ns/1ps \ -quiet \ -q \ +rad \ - +v2k \ +vcs+lic+wait \ +vc+list \ -error=noZMMCM \ - -assert svaext \ - -sverilog \ - +libext+.v \ + -error=PCWM-L \ + -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ + +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ +incdir+$(build_dir) \ -f $(sim_common_files) \ $(sim_vsrcs) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index fd7f1bd6e5..9d99f78cc7 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -72,7 +72,6 @@ ARIANE_VERILATOR_FLAGS = \ --unroll-count 256 \ -Werror-PINMISSING \ -Werror-IMPLICIT \ - -Wno-fatal \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ @@ -91,9 +90,11 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 VERILATOR_NONCC_OPTS = \ $(TIMESCALE_OPTS) \ --top-module $(VLOG_MODEL) \ + -Wno-fatal \ $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ --output-split 10000 \ --output-split-cfuncs 100 \ + --max-num-width 1048576 \ -f $(sim_common_files) \ $(sim_vsrcs) diff --git a/software/firemarshal b/software/firemarshal index c8e89bbeb5..a40f0252c4 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit c8e89bbeb575be027670afa21c761319c2fd7e33 +Subproject commit a40f0252c4e426e794313ba02b0015e5f22133f4 diff --git a/software/nvdla-workload b/software/nvdla-workload new file mode 160000 index 0000000000..02faf59692 --- /dev/null +++ b/software/nvdla-workload @@ -0,0 +1 @@ +Subproject commit 02faf59692f88b66f8720d4eefa85aae385288a0 diff --git a/tests/Makefile b/tests/Makefile index 8754cbbc8d..af1bbd9cf3 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -5,7 +5,7 @@ LDFLAGS= -static include libgloss.mk -PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd spiflashread spiflashwrite +PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd nvdla spiflashread spiflashwrite spiflash.img: spiflash.py python3 $< diff --git a/tests/nvdla.c b/tests/nvdla.c new file mode 100644 index 0000000000..5cf57f158f --- /dev/null +++ b/tests/nvdla.c @@ -0,0 +1,468 @@ +#include + +#include "nvdla.h" +#include "mmio.h" +#include + +#define NVDLA_BASE 0x10040000 +#define reg_write(addr,val) reg_write32(NVDLA_BASE+addr,val) +#define reg_read(addr) reg_read32(NVDLA_BASE+addr) + +int main(void) +{ + //----------## Layer:CDP_0: cross layer dependency, begin---------- + //----------## Layer:CDP_0: cross layer dependency, end---------- + //----------## Layer:CDP_0: set producer pointer, begin---------- + reg_write(CDP_S_POINTER_0, 0); + reg_write(CDP_RDMA_S_POINTER_0, 0); + //----------## Layer:CDP_0: set producer pointer, end---------- + //----------## Layer:CDP_0: LUT programming, begin---------- + reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x30000); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x10); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x11); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x12); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x13); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x14); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x15); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x16); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x17); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x18); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x19); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x20); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x21); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x22); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x23); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x24); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x25); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x26); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x27); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x28); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x29); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x30); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x31); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x32); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x33); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x34); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x35); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x36); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x37); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x38); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x39); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x40); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x41); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x42); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x43); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x44); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x45); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x46); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x47); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x48); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x49); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x50); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x51); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x52); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x53); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x54); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x55); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x56); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x57); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x58); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x59); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x60); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x61); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x62); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x63); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x64); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x65); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x66); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x67); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x68); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x69); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x70); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x71); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x72); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x73); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x74); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x75); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x76); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x77); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x78); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x79); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x80); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x81); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x82); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x83); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x84); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x85); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x86); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x87); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x88); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x89); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x90); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x91); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x92); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x93); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x94); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x95); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x96); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x97); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x98); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x99); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xaa); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xab); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xac); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xad); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xae); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xaf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xba); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbe); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xca); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xce); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xda); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xde); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xea); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xeb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xec); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xed); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xee); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xef); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfa); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfe); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xff); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x100); + reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x20000); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x10); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x11); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x12); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x13); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x14); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x15); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x16); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x17); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x18); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x19); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x20); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x21); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x22); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x23); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x24); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x25); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x26); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x27); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x28); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x29); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x30); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x31); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x32); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x33); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x34); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x35); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x36); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x37); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x38); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x39); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x40); + reg_write(CDP_S_LUT_LE_START_LOW_0, 0x0); + // CDP_S_LUT_LE_START_LOW_0.LUT_LE_START_LOW:0x0 + reg_write(CDP_S_LUT_LO_END_LOW_0, 0x100); + // CDP_S_LUT_LO_END_LOW_0.LUT_LO_END_LOW:0x100 + reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x0); + // CDP_S_LUT_ACCESS_CFG_0.LUT_ACCESS_TYPE:READ : 0x0 + // CDP_S_LUT_ACCESS_CFG_0.LUT_TABLE_ID:LE : 0x0 + // CDP_S_LUT_ACCESS_CFG_0.LUT_ADDR:0x0 + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0); + // CDP_S_LUT_ACCESS_DATA_0.LUT_DATA:0x0 + reg_write(CDP_S_LUT_LE_START_HIGH_0, 0x0); + // CDP_S_LUT_LE_START_HIGH_0.LUT_LE_START_HIGH:0x0 + reg_write(CDP_S_LUT_LO_END_HIGH_0, 0x0); + // CDP_S_LUT_LO_END_HIGH_0.LUT_LO_END_HIGH:0x0 + reg_write(CDP_S_LUT_CFG_0, 0x1); + // CDP_S_LUT_CFG_0.LUT_UFLOW_PRIORITY:LE : 0x0 + // CDP_S_LUT_CFG_0.LUT_OFLOW_PRIORITY:LE : 0x0 + // CDP_S_LUT_CFG_0.LUT_HYBRID_PRIORITY:LE : 0x0 + // CDP_S_LUT_CFG_0.LUT_LE_FUNCTION:LINEAR : 0x1 + reg_write(CDP_S_LUT_LE_SLOPE_SHIFT_0, 0x0); + // CDP_S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_OFLOW_SHIFT:0x0 + // CDP_S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_UFLOW_SHIFT:0x0 + reg_write(CDP_S_LUT_LE_SLOPE_SCALE_0, 0x0); + // CDP_S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_UFLOW_SCALE:0x0 + // CDP_S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_OFLOW_SCALE:0x0 + reg_write(CDP_S_LUT_INFO_0, 0x0); + // CDP_S_LUT_INFO_0.LUT_LE_INDEX_SELECT:0x0 + // CDP_S_LUT_INFO_0.LUT_LE_INDEX_OFFSET:0x0 + // CDP_S_LUT_INFO_0.LUT_LO_INDEX_SELECT:0x0 + reg_write(CDP_S_LUT_LE_END_LOW_0, 0x40); + // CDP_S_LUT_LE_END_LOW_0.LUT_LE_END_LOW:0x40 + reg_write(CDP_S_LUT_LO_SLOPE_SCALE_0, 0x0); + // CDP_S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_OFLOW_SCALE:0x0 + // CDP_S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_UFLOW_SCALE:0x0 + reg_write(CDP_S_LUT_LE_END_HIGH_0, 0x0); + // CDP_S_LUT_LE_END_HIGH_0.LUT_LE_END_HIGH:0x0 + reg_write(CDP_S_LUT_LO_START_HIGH_0, 0x0); + // CDP_S_LUT_LO_START_HIGH_0.LUT_LO_START_HIGH:0x0 + reg_write(CDP_S_LUT_LO_START_LOW_0, 0x0); + // CDP_S_LUT_LO_START_LOW_0.LUT_LO_START_LOW:0x0 + reg_write(CDP_S_LUT_LO_SLOPE_SHIFT_0, 0x0); + // CDP_S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_UFLOW_SHIFT:0x0 + // CDP_S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_OFLOW_SHIFT:0x0 + //----------## Layer:CDP_0: LUT programming, end---------- + //----------## Layer:CDP_0: configuraion, begin---------- + reg_write(CDP_D_DATOUT_OFFSET_0, 0x80); + // CDP_D_DATOUT_OFFSET_0.DATOUT_OFFSET:0x80 + reg_write(CDP_D_DST_SURFACE_STRIDE_0, 0x800); + // CDP_D_DST_SURFACE_STRIDE_0.DST_SURFACE_STRIDE:0x40 + reg_write(CDP_RDMA_D_SRC_BASE_ADDR_LOW_0, 0x90000000); + // CDP_RDMA_D_SRC_BASE_ADDR_LOW_0.SRC_BASE_ADDR_LOW:0x4000000 + reg_write(CDP_D_DST_DMA_CFG_0, 0x1); + // CDP_D_DST_DMA_CFG_0.DST_RAM_TYPE:MC : 0x1 + reg_write(CDP_RDMA_D_DATA_CUBE_WIDTH_0, 0x7); + // CDP_RDMA_D_DATA_CUBE_WIDTH_0.WIDTH:0x7 + reg_write(CDP_RDMA_D_DATA_FORMAT_0, 0x0); + // CDP_RDMA_D_DATA_FORMAT_0.INPUT_DATA:INT8 : 0x0 + reg_write(CDP_D_DATIN_SCALE_0, 0x1); + // CDP_D_DATIN_SCALE_0.DATIN_SCALE:0x1 + reg_write(CDP_D_DATOUT_SHIFTER_0, 0x0); + // CDP_D_DATOUT_SHIFTER_0.DATOUT_SHIFTER:0x0 + reg_write(CDP_D_CYA_0, 0x0); + // CDP_D_CYA_0.CYA:0x0 + reg_write(CDP_RDMA_D_PERF_ENABLE_0, 0x0); + // CDP_RDMA_D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0 + reg_write(CDP_D_LRN_CFG_0, 0x0); + // CDP_D_LRN_CFG_0.NORMALZ_LEN:LEN3 : 0x0 + reg_write(CDP_RDMA_D_DATA_CUBE_CHANNEL_0, 0x1f); + // CDP_RDMA_D_DATA_CUBE_CHANNEL_0.CHANNEL:0x1f + reg_write(CDP_D_DATA_FORMAT_0, 0x0); + // CDP_D_DATA_FORMAT_0.INPUT_DATA_TYPE:INT8 : 0x0 + reg_write(CDP_D_DATIN_SHIFTER_0, 0x0); + // CDP_D_DATIN_SHIFTER_0.DATIN_SHIFTER:0x0 + reg_write(CDP_D_PERF_ENABLE_0, 0x0); + // CDP_D_PERF_ENABLE_0.LUT_EN:DISABLE : 0x0 + // CDP_D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0 + reg_write(CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0, 0x0); + // CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0.SRC_BASE_ADDR_HIGH:0x0 + reg_write(CDP_D_DST_BASE_ADDR_HIGH_0, 0x0); + // CDP_D_DST_BASE_ADDR_HIGH_0.DST_BASE_ADDR_HIGH:0x0 + reg_write(CDP_RDMA_D_SRC_DMA_CFG_0, 0x1); + // CDP_RDMA_D_SRC_DMA_CFG_0.SRC_RAM_TYPE:MC : 0x1 + reg_write(CDP_D_DATOUT_SCALE_0, 0x1); + // CDP_D_DATOUT_SCALE_0.DATOUT_SCALE:0x1 + reg_write(CDP_D_DATIN_OFFSET_0, 0x80); + // CDP_D_DATIN_OFFSET_0.DATIN_OFFSET:0x80 + reg_write(CDP_D_NAN_FLUSH_TO_ZERO_0, 0x0); + // CDP_D_NAN_FLUSH_TO_ZERO_0.NAN_TO_ZERO:DISABLE : 0x0 + reg_write(CDP_D_FUNC_BYPASS_0, 0x3); + // CDP_D_FUNC_BYPASS_0.SQSUM_BYPASS:ENABLE : 0x1 + // CDP_D_FUNC_BYPASS_0.MUL_BYPASS:ENABLE : 0x1 + reg_write(CDP_D_DST_BASE_ADDR_LOW_0, 0x90080000); + // CDP_D_DST_BASE_ADDR_LOW_0.DST_BASE_ADDR_LOW:0x4004000 + reg_write(CDP_RDMA_D_CYA_0, 0x0); + // CDP_RDMA_D_CYA_0.CYA:0x0 + reg_write(CDP_RDMA_D_SRC_SURFACE_STRIDE_0, 0x800); + // CDP_RDMA_D_SRC_SURFACE_STRIDE_0.SRC_SURFACE_STRIDE:0x40 + reg_write(CDP_D_DST_LINE_STRIDE_0, 0x100); + // CDP_D_DST_LINE_STRIDE_0.DST_LINE_STRIDE:0x8 + reg_write(CDP_RDMA_D_SRC_LINE_STRIDE_0, 0x100); + // CDP_RDMA_D_SRC_LINE_STRIDE_0.SRC_LINE_STRIDE:0x8 + reg_write(CDP_RDMA_D_DATA_CUBE_HEIGHT_0, 0x7); + // CDP_RDMA_D_DATA_CUBE_HEIGHT_0.HEIGHT:0x7 + //----------## Layer:CDP_0: configuraion, end---------- + //----------## Layer:CDP_0: operation enable, begin---------- + //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, begin -- + reg_write(CDP_RDMA_D_OP_ENABLE_0,0x1); + //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, end -- + //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, begin -- + reg_write(CDP_D_OP_ENABLE_0,0x1); + //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, end -- + //----------## Layer:CDP_0: operation enable, end---------- + + register uint64_t cycle1 = rdcycle(); + + for (register int idx = 0; idx < 32767; idx++) { + if (reg_read(GLB_S_INTR_STATUS_0) != 0) + break; + } + + uint64_t cycle2 = rdcycle(); + printf("cycle1: %lu, cycle2: %lu, diff: %lu\n", cycle1, cycle2, cycle2 - cycle1 ); + + return 0; +} diff --git a/tests/nvdla.h b/tests/nvdla.h new file mode 100644 index 0000000000..dfcb3b0f84 --- /dev/null +++ b/tests/nvdla.h @@ -0,0 +1,6433 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of NVIDIA CORPORATION nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __OPENDLA_SMALL_H_ +#define __OPENDLA_SMALL_H_ + +// Register NVDLA_CFGROM_CFGROM_HW_VERSION_0 +#define NVDLA_CFGROM_CFGROM_HW_VERSION_0 _MK_ADDR_CONST(0x0) +#define NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_GLB_DESC_0 +#define NVDLA_CFGROM_CFGROM_GLB_DESC_0 _MK_ADDR_CONST(0x4) +#define NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_DESC_0 +#define NVDLA_CFGROM_CFGROM_CIF_DESC_0 _MK_ADDR_CONST(0x8) +#define NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0 _MK_ADDR_CONST(0xc) +#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0 _MK_ADDR_CONST(0x10) +#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0 _MK_ADDR_CONST(0x14) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_FIELD _MK_FIELD_CONST(0xff, NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0 +#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0 _MK_ADDR_CONST(0x18) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0 +#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0 _MK_ADDR_CONST(0x1c) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_FIELD _MK_FIELD_CONST(0x7ffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0 _MK_ADDR_CONST(0x20) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_FIELD _MK_FIELD_CONST(0x7ffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_DESC_0 +#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0 _MK_ADDR_CONST(0x24) +#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x28) +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0 _MK_ADDR_CONST(0x2c) +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x30) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0x34) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0x38) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0x3c) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x40) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0 _MK_ADDR_CONST(0x44) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0 _MK_ADDR_CONST(0x48) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0 _MK_ADDR_CONST(0x4c) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0 +#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0 _MK_ADDR_CONST(0x50) +#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0 +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0 _MK_ADDR_CONST(0x54) +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0 +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0 _MK_ADDR_CONST(0x58) +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_DESC_0 +#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0 _MK_ADDR_CONST(0x5c) +#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x60) +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0 _MK_ADDR_CONST(0x64) +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0 +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0 _MK_ADDR_CONST(0x68) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0 _MK_ADDR_CONST(0x6c) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0 +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0 _MK_ADDR_CONST(0x70) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0 _MK_ADDR_CONST(0x74) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_DESC_0 +#define NVDLA_CFGROM_CFGROM_CSC_DESC_0 _MK_ADDR_CONST(0x78) +#define NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x7c) +#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0 _MK_ADDR_CONST(0x80) +#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x84) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0x88) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0x8c) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0x90) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x94) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0 _MK_ADDR_CONST(0x98) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0 _MK_ADDR_CONST(0x9c) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0 _MK_ADDR_CONST(0xa0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0 _MK_ADDR_CONST(0xa4) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0 +#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0 _MK_ADDR_CONST(0xa8) +#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0 _MK_ADDR_CONST(0xac) +#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0 _MK_ADDR_CONST(0xb0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0 _MK_ADDR_CONST(0xb4) +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0xb8) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0xbc) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0xc0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0xc4) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0 _MK_ADDR_CONST(0xc8) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0 _MK_ADDR_CONST(0xcc) +#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0 _MK_ADDR_CONST(0xd0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0 _MK_ADDR_CONST(0xd4) +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0xd8) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0xdc) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0xe0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0xe4) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0 _MK_ADDR_CONST(0xe8) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_DESC_0 +#define NVDLA_CFGROM_CFGROM_CACC_DESC_0 _MK_ADDR_CONST(0xec) +#define NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0 _MK_ADDR_CONST(0xf0) +#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0 _MK_ADDR_CONST(0xf4) +#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0xf8) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0xfc) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0x100) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0x104) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0 _MK_ADDR_CONST(0x108) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0 +#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0 _MK_ADDR_CONST(0x10c) +#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0 _MK_ADDR_CONST(0x110) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x114) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0 _MK_ADDR_CONST(0x118) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x11c) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0 _MK_ADDR_CONST(0x120) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_DESC_0 +#define NVDLA_CFGROM_CFGROM_SDP_DESC_0 _MK_ADDR_CONST(0x124) +#define NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x128) +#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0 _MK_ADDR_CONST(0x12c) +#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x130) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0x134) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0 _MK_ADDR_CONST(0x138) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0 +#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0 _MK_ADDR_CONST(0x13c) +#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0 _MK_ADDR_CONST(0x140) +#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0 _MK_ADDR_CONST(0x144) +#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0 _MK_ADDR_CONST(0x148) +#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0 _MK_ADDR_CONST(0x14c) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x150) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0 _MK_ADDR_CONST(0x154) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x158) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0 _MK_ADDR_CONST(0x15c) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_DESC_0 +#define NVDLA_CFGROM_CFGROM_PDP_DESC_0 _MK_ADDR_CONST(0x160) +#define NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x164) +#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0 _MK_ADDR_CONST(0x168) +#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x16c) +#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0 _MK_ADDR_CONST(0x170) +#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0 _MK_ADDR_CONST(0x174) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x178) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0 _MK_ADDR_CONST(0x17c) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x180) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0 _MK_ADDR_CONST(0x184) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_DESC_0 +#define NVDLA_CFGROM_CFGROM_CDP_DESC_0 _MK_ADDR_CONST(0x188) +#define NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x18c) +#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0 _MK_ADDR_CONST(0x190) +#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x194) +#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0 _MK_ADDR_CONST(0x198) +#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_END_OF_LIST_0 +#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0 _MK_ADDR_CONST(0x19c) +#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register GLB_S_NVDLA_HW_VERSION_0 +#define GLB_S_NVDLA_HW_VERSION_0 _MK_ADDR_CONST(0x1000) +#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT _MK_SHIFT_CONST(0) +#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_FIELD _MK_FIELD_CONST(0xff, GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT) +#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT _MK_SHIFT_CONST(8) +#define GLB_S_NVDLA_HW_VERSION_0_MINOR_FIELD _MK_FIELD_CONST(0xffff, GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT) + + +// Register GLB_S_INTR_MASK_0 +#define GLB_S_INTR_MASK_0 _MK_ADDR_CONST(0x1004) +#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT _MK_SHIFT_CONST(0) +#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT _MK_SHIFT_CONST(1) +#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT _MK_SHIFT_CONST(2) +#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT _MK_SHIFT_CONST(3) +#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT _MK_SHIFT_CONST(4) +#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT _MK_SHIFT_CONST(5) +#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT _MK_SHIFT_CONST(6) +#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT _MK_SHIFT_CONST(7) +#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT _MK_SHIFT_CONST(8) +#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT _MK_SHIFT_CONST(9) +#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT _MK_SHIFT_CONST(16) +#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT _MK_SHIFT_CONST(17) +#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT _MK_SHIFT_CONST(18) +#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT _MK_SHIFT_CONST(19) +#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT _MK_SHIFT_CONST(20) +#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT _MK_SHIFT_CONST(21) +#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT) + + +// Register GLB_S_INTR_SET_0 +#define GLB_S_INTR_SET_0 _MK_ADDR_CONST(0x1008) +#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT _MK_SHIFT_CONST(0) +#define GLB_S_INTR_SET_0_SDP_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT _MK_SHIFT_CONST(1) +#define GLB_S_INTR_SET_0_SDP_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT _MK_SHIFT_CONST(2) +#define GLB_S_INTR_SET_0_CDP_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT _MK_SHIFT_CONST(3) +#define GLB_S_INTR_SET_0_CDP_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT _MK_SHIFT_CONST(4) +#define GLB_S_INTR_SET_0_PDP_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT _MK_SHIFT_CONST(5) +#define GLB_S_INTR_SET_0_PDP_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT _MK_SHIFT_CONST(6) +#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT _MK_SHIFT_CONST(7) +#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT _MK_SHIFT_CONST(8) +#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT _MK_SHIFT_CONST(9) +#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT _MK_SHIFT_CONST(16) +#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT _MK_SHIFT_CONST(17) +#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT _MK_SHIFT_CONST(18) +#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT _MK_SHIFT_CONST(19) +#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT _MK_SHIFT_CONST(20) +#define GLB_S_INTR_SET_0_CACC_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT _MK_SHIFT_CONST(21) +#define GLB_S_INTR_SET_0_CACC_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT) + + +// Register GLB_S_INTR_STATUS_0 +#define GLB_S_INTR_STATUS_0 _MK_ADDR_CONST(0x100c) +#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(0) +#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(1) +#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(2) +#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(3) +#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(4) +#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(5) +#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(6) +#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(7) +#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(8) +#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(9) +#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(16) +#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(17) +#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(18) +#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(19) +#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(20) +#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(21) +#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register NVDLA_MCIF_CFG_RD_WEIGHT_0_0 +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0 _MK_ADDR_CONST(0x2000) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT) + + +// Register NVDLA_MCIF_CFG_RD_WEIGHT_1_0 +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0 _MK_ADDR_CONST(0x2004) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT) + + +// Register NVDLA_MCIF_CFG_RD_WEIGHT_2_0 +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0 _MK_ADDR_CONST(0x2008) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT) + + +// Register NVDLA_MCIF_CFG_WR_WEIGHT_0_0 +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0 _MK_ADDR_CONST(0x200c) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT) + + +// Register NVDLA_MCIF_CFG_WR_WEIGHT_1_0 +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0 _MK_ADDR_CONST(0x2010) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT) + + +// Register NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 _MK_ADDR_CONST(0x2014) +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT) +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT) + + +// Register NVDLA_MCIF_STATUS_0 +#define NVDLA_MCIF_STATUS_0 _MK_ADDR_CONST(0x2018) +#define NVDLA_MCIF_STATUS_0_IDLE_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_STATUS_0_IDLE_FIELD _MK_FIELD_CONST(0x1, NVDLA_MCIF_STATUS_0_IDLE_SHIFT) +#define NVDLA_MCIF_STATUS_0_IDLE_NO _MK_ENUM_CONST(0x0) +#define NVDLA_MCIF_STATUS_0_IDLE_YES _MK_ENUM_CONST(0x1) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CDMA_S_STATUS_0 +#define CDMA_S_STATUS_0 _MK_ADDR_CONST(0x3000) +#define CDMA_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_0_SHIFT) +#define CDMA_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CDMA_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CDMA_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CDMA_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_1_SHIFT) +#define CDMA_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CDMA_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CDMA_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CDMA_S_POINTER_0 +#define CDMA_S_POINTER_0 _MK_ADDR_CONST(0x3004) +#define CDMA_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_PRODUCER_SHIFT) +#define CDMA_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDMA_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CDMA_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_CONSUMER_SHIFT) +#define CDMA_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDMA_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CDMA_S_ARBITER_0 +#define CDMA_S_ARBITER_0 _MK_ADDR_CONST(0x3008) +#define CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_S_ARBITER_0_ARB_WEIGHT_FIELD _MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT) +#define CDMA_S_ARBITER_0_ARB_WMB_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_S_ARBITER_0_ARB_WMB_FIELD _MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WMB_SHIFT) + + +// Register CDMA_S_CBUF_FLUSH_STATUS_0 +#define CDMA_S_CBUF_FLUSH_STATUS_0 _MK_ADDR_CONST(0x300c) +#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_FIELD _MK_FIELD_CONST(0x1, CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT) + + +// Register CDMA_D_OP_ENABLE_0 +#define CDMA_D_OP_ENABLE_0 _MK_ADDR_CONST(0x3010) +#define CDMA_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CDMA_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CDMA_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_MISC_CFG_0 +#define CDMA_D_MISC_CFG_0 _MK_ADDR_CONST(0x3014) +#define CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CDMA_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT _MK_SHIFT_CONST(8) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_FIELD _MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_MISC_CFG_0_DATA_REUSE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT) +#define CDMA_D_MISC_CFG_0_DATA_REUSE_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_DATA_REUSE_ENABLE _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT _MK_SHIFT_CONST(20) +#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT) +#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT _MK_SHIFT_CONST(24) +#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT) +#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT _MK_SHIFT_CONST(28) +#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT) +#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_DATAIN_FORMAT_0 +#define CDMA_D_DATAIN_FORMAT_0 _MK_ADDR_CONST(0x3018) +#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT) +#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE _MK_ENUM_CONST(0x0) +#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL _MK_ENUM_CONST(0x1) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT _MK_SHIFT_CONST(8) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_FIELD _MK_FIELD_CONST(0x3f, CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8 _MK_ENUM_CONST(0x0) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10 _MK_ENUM_CONST(0x1) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R12 _MK_ENUM_CONST(0x2) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16 _MK_ENUM_CONST(0x3) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_I _MK_ENUM_CONST(0x4) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_F _MK_ENUM_CONST(0x5) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16 _MK_ENUM_CONST(0x6) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X16B16G16R16 _MK_ENUM_CONST(0x7) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16_F _MK_ENUM_CONST(0x8) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16 _MK_ENUM_CONST(0x9) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V16U16Y16A16 _MK_ENUM_CONST(0xa) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16_F _MK_ENUM_CONST(0xb) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8B8G8R8 _MK_ENUM_CONST(0xc) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8R8G8B8 _MK_ENUM_CONST(0xd) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8A8 _MK_ENUM_CONST(0xe) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8A8 _MK_ENUM_CONST(0xf) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8B8G8R8 _MK_ENUM_CONST(0x10) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8R8G8B8 _MK_ENUM_CONST(0x11) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8X8 _MK_ENUM_CONST(0x12) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8X8 _MK_ENUM_CONST(0x13) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2B10G10R10 _MK_ENUM_CONST(0x14) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2R10G10B10 _MK_ENUM_CONST(0x15) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B10G10R10A2 _MK_ENUM_CONST(0x16) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10G10B10A2 _MK_ENUM_CONST(0x17) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2Y10U10V10 _MK_ENUM_CONST(0x18) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V10U10Y10A2 _MK_ENUM_CONST(0x19) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8Y8U8V8 _MK_ENUM_CONST(0x1a) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V8U8Y8A8 _MK_ENUM_CONST(0x1b) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___U8V8_N444 _MK_ENUM_CONST(0x1c) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___V8U8_N444 _MK_ENUM_CONST(0x1d) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___U10V10_N444 _MK_ENUM_CONST(0x1e) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___V10U10_N444 _MK_ENUM_CONST(0x1f) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___U12V12_N444 _MK_ENUM_CONST(0x20) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___V12U12_N444 _MK_ENUM_CONST(0x21) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___U16V16_N444 _MK_ENUM_CONST(0x22) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___V16U16_N444 _MK_ENUM_CONST(0x23) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PITCH_LINEAR _MK_ENUM_CONST(0x0) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RESERVED_LINEAR _MK_ENUM_CONST(0x1) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT _MK_SHIFT_CONST(20) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_UNSIGNED_INT _MK_ENUM_CONST(0x0) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SIGNED_INT _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_DATAIN_SIZE_0_0 +#define CDMA_D_DATAIN_SIZE_0_0 _MK_ADDR_CONST(0x301c) +#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT) +#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT) + + +// Register CDMA_D_DATAIN_SIZE_1_0 +#define CDMA_D_DATAIN_SIZE_1_0 _MK_ADDR_CONST(0x3020) +#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT) + + +// Register CDMA_D_DATAIN_SIZE_EXT_0_0 +#define CDMA_D_DATAIN_SIZE_EXT_0_0 _MK_ADDR_CONST(0x3024) +#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT) +#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT) + + +// Register CDMA_D_PIXEL_OFFSET_0 +#define CDMA_D_PIXEL_OFFSET_0 _MK_ADDR_CONST(0x3028) +#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT) +#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_FIELD _MK_FIELD_CONST(0x7, CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT) + + +// Register CDMA_D_DAIN_RAM_TYPE_0 +#define CDMA_D_DAIN_RAM_TYPE_0 _MK_ADDR_CONST(0x302c) +#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT) +#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF _MK_ENUM_CONST(0x0) +#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_DAIN_ADDR_HIGH_0_0 +#define CDMA_D_DAIN_ADDR_HIGH_0_0 _MK_ADDR_CONST(0x3030) +#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT) + + +// Register CDMA_D_DAIN_ADDR_LOW_0_0 +#define CDMA_D_DAIN_ADDR_LOW_0_0 _MK_ADDR_CONST(0x3034) +#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT) + + +// Register CDMA_D_DAIN_ADDR_HIGH_1_0 +#define CDMA_D_DAIN_ADDR_HIGH_1_0 _MK_ADDR_CONST(0x3038) +#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT) + + +// Register CDMA_D_DAIN_ADDR_LOW_1_0 +#define CDMA_D_DAIN_ADDR_LOW_1_0 _MK_ADDR_CONST(0x303c) +#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT) + + +// Register CDMA_D_LINE_STRIDE_0 +#define CDMA_D_LINE_STRIDE_0 _MK_ADDR_CONST(0x3040) +#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT) + + +// Register CDMA_D_LINE_UV_STRIDE_0 +#define CDMA_D_LINE_UV_STRIDE_0 _MK_ADDR_CONST(0x3044) +#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT) + + +// Register CDMA_D_SURF_STRIDE_0 +#define CDMA_D_SURF_STRIDE_0 _MK_ADDR_CONST(0x3048) +#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT) + + +// Register CDMA_D_DAIN_MAP_0 +#define CDMA_D_DAIN_MAP_0 _MK_ADDR_CONST(0x304c) +#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT) +#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FALSE _MK_ENUM_CONST(0x0) +#define CDMA_D_DAIN_MAP_0_LINE_PACKED_TRUE _MK_ENUM_CONST(0x1) +#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT) +#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FALSE _MK_ENUM_CONST(0x0) +#define CDMA_D_DAIN_MAP_0_SURF_PACKED_TRUE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_RESERVED_X_CFG_0 +#define CDMA_D_RESERVED_X_CFG_0 _MK_ADDR_CONST(0x3050) +#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_FIELD _MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT) +#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_FIELD _MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT) + + +// Register CDMA_D_RESERVED_Y_CFG_0 +#define CDMA_D_RESERVED_Y_CFG_0 _MK_ADDR_CONST(0x3054) +#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_FIELD _MK_FIELD_CONST(0x7, CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT) +#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT) + + +// Register CDMA_D_BATCH_NUMBER_0 +#define CDMA_D_BATCH_NUMBER_0 _MK_ADDR_CONST(0x3058) +#define CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_BATCH_NUMBER_0_BATCHES_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT) + + +// Register CDMA_D_BATCH_STRIDE_0 +#define CDMA_D_BATCH_STRIDE_0 _MK_ADDR_CONST(0x305c) +#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT) + + +// Register CDMA_D_ENTRY_PER_SLICE_0 +#define CDMA_D_ENTRY_PER_SLICE_0 _MK_ADDR_CONST(0x3060) +#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD _MK_FIELD_CONST(0x3fff, CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT) + + +// Register CDMA_D_FETCH_GRAIN_0 +#define CDMA_D_FETCH_GRAIN_0 _MK_ADDR_CONST(0x3064) +#define CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_FETCH_GRAIN_0_GRAINS_FIELD _MK_FIELD_CONST(0xfff, CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT) + + +// Register CDMA_D_WEIGHT_FORMAT_0 +#define CDMA_D_WEIGHT_FORMAT_0 _MK_ADDR_CONST(0x3068) +#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD _MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT) +#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED _MK_ENUM_CONST(0x0) +#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_WEIGHT_SIZE_0_0 +#define CDMA_D_WEIGHT_SIZE_0_0 _MK_ADDR_CONST(0x306c) +#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_FIELD _MK_FIELD_CONST(0x3ffff, CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT) + + +// Register CDMA_D_WEIGHT_SIZE_1_0 +#define CDMA_D_WEIGHT_SIZE_1_0 _MK_ADDR_CONST(0x3070) +#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT) + + +// Register CDMA_D_WEIGHT_RAM_TYPE_0 +#define CDMA_D_WEIGHT_RAM_TYPE_0 _MK_ADDR_CONST(0x3074) +#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT) +#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_CVIF _MK_ENUM_CONST(0x0) +#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_MCIF _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_WEIGHT_ADDR_HIGH_0 +#define CDMA_D_WEIGHT_ADDR_HIGH_0 _MK_ADDR_CONST(0x3078) +#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT) + + +// Register CDMA_D_WEIGHT_ADDR_LOW_0 +#define CDMA_D_WEIGHT_ADDR_LOW_0 _MK_ADDR_CONST(0x307c) +#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT) + + +// Register CDMA_D_WEIGHT_BYTES_0 +#define CDMA_D_WEIGHT_BYTES_0 _MK_ADDR_CONST(0x3080) +#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT) + + +// Register CDMA_D_WGS_ADDR_HIGH_0 +#define CDMA_D_WGS_ADDR_HIGH_0 _MK_ADDR_CONST(0x3084) +#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT) + + +// Register CDMA_D_WGS_ADDR_LOW_0 +#define CDMA_D_WGS_ADDR_LOW_0 _MK_ADDR_CONST(0x3088) +#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT) + + +// Register CDMA_D_WMB_ADDR_HIGH_0 +#define CDMA_D_WMB_ADDR_HIGH_0 _MK_ADDR_CONST(0x308c) +#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT) + + +// Register CDMA_D_WMB_ADDR_LOW_0 +#define CDMA_D_WMB_ADDR_LOW_0 _MK_ADDR_CONST(0x3090) +#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT) + + +// Register CDMA_D_WMB_BYTES_0 +#define CDMA_D_WMB_BYTES_0 _MK_ADDR_CONST(0x3094) +#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WMB_BYTES_0_WMB_BYTES_FIELD _MK_FIELD_CONST(0xfffffff, CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT) + + +// Register CDMA_D_MEAN_FORMAT_0 +#define CDMA_D_MEAN_FORMAT_0 _MK_ADDR_CONST(0x3098) +#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT) +#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_MEAN_GLOBAL_0_0 +#define CDMA_D_MEAN_GLOBAL_0_0 _MK_ADDR_CONST(0x309c) +#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT) +#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT) + + +// Register CDMA_D_MEAN_GLOBAL_1_0 +#define CDMA_D_MEAN_GLOBAL_1_0 _MK_ADDR_CONST(0x30a0) +#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT) +#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT) + + +// Register CDMA_D_CVT_CFG_0 +#define CDMA_D_CVT_CFG_0 _MK_ADDR_CONST(0x30a4) +#define CDMA_D_CVT_CFG_0_CVT_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CVT_CFG_0_CVT_EN_FIELD _MK_FIELD_CONST(0x1, CDMA_D_CVT_CFG_0_CVT_EN_SHIFT) +#define CDMA_D_CVT_CFG_0_CVT_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_CVT_CFG_0_CVT_EN_ENABLE _MK_ENUM_CONST(0x1) +#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT _MK_SHIFT_CONST(4) +#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_FIELD _MK_FIELD_CONST(0x3f, CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT) + + +// Register CDMA_D_CVT_OFFSET_0 +#define CDMA_D_CVT_OFFSET_0 _MK_ADDR_CONST(0x30a8) +#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT) + + +// Register CDMA_D_CVT_SCALE_0 +#define CDMA_D_CVT_SCALE_0 _MK_ADDR_CONST(0x30ac) +#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CVT_SCALE_0_CVT_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT) + + +// Register CDMA_D_CONV_STRIDE_0 +#define CDMA_D_CONV_STRIDE_0 _MK_ADDR_CONST(0x30b0) +#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_FIELD _MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT) +#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_FIELD _MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT) + + +// Register CDMA_D_ZERO_PADDING_0 +#define CDMA_D_ZERO_PADDING_0 _MK_ADDR_CONST(0x30b4) +#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT) +#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT _MK_SHIFT_CONST(8) +#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_FIELD _MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT) +#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_ZERO_PADDING_0_PAD_TOP_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT) +#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT _MK_SHIFT_CONST(24) +#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_FIELD _MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT) + + +// Register CDMA_D_ZERO_PADDING_VALUE_0 +#define CDMA_D_ZERO_PADDING_VALUE_0 _MK_ADDR_CONST(0x30b8) +#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT) + + +// Register CDMA_D_BANK_0 +#define CDMA_D_BANK_0 _MK_ADDR_CONST(0x30bc) +#define CDMA_D_BANK_0_DATA_BANK_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_BANK_0_DATA_BANK_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_BANK_0_DATA_BANK_SHIFT) +#define CDMA_D_BANK_0_WEIGHT_BANK_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_BANK_0_WEIGHT_BANK_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_BANK_0_WEIGHT_BANK_SHIFT) + + +// Register CDMA_D_NAN_FLUSH_TO_ZERO_0 +#define CDMA_D_NAN_FLUSH_TO_ZERO_0 _MK_ADDR_CONST(0x30c0) +#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD _MK_FIELD_CONST(0x1, CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT) +#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_NAN_INPUT_DATA_NUM_0 +#define CDMA_D_NAN_INPUT_DATA_NUM_0 _MK_ADDR_CONST(0x30c4) +#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT) + + +// Register CDMA_D_NAN_INPUT_WEIGHT_NUM_0 +#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0 _MK_ADDR_CONST(0x30c8) +#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT) + + +// Register CDMA_D_INF_INPUT_DATA_NUM_0 +#define CDMA_D_INF_INPUT_DATA_NUM_0 _MK_ADDR_CONST(0x30cc) +#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT) + + +// Register CDMA_D_INF_INPUT_WEIGHT_NUM_0 +#define CDMA_D_INF_INPUT_WEIGHT_NUM_0 _MK_ADDR_CONST(0x30d0) +#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT) + + +// Register CDMA_D_PERF_ENABLE_0 +#define CDMA_D_PERF_ENABLE_0 _MK_ADDR_CONST(0x30d4) +#define CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT) + + +// Register CDMA_D_PERF_DAT_READ_STALL_0 +#define CDMA_D_PERF_DAT_READ_STALL_0 _MK_ADDR_CONST(0x30d8) +#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT) + + +// Register CDMA_D_PERF_WT_READ_STALL_0 +#define CDMA_D_PERF_WT_READ_STALL_0 _MK_ADDR_CONST(0x30dc) +#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT) + + +// Register CDMA_D_PERF_DAT_READ_LATENCY_0 +#define CDMA_D_PERF_DAT_READ_LATENCY_0 _MK_ADDR_CONST(0x30e0) +#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT) + + +// Register CDMA_D_PERF_WT_READ_LATENCY_0 +#define CDMA_D_PERF_WT_READ_LATENCY_0 _MK_ADDR_CONST(0x30e4) +#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT) + + +// Register CDMA_D_CYA_0 +#define CDMA_D_CYA_0 _MK_ADDR_CONST(0x30e8) +#define CDMA_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CSC_S_STATUS_0 +#define CSC_S_STATUS_0 _MK_ADDR_CONST(0x4000) +#define CSC_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CSC_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_0_SHIFT) +#define CSC_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CSC_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CSC_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CSC_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CSC_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_1_SHIFT) +#define CSC_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CSC_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CSC_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CSC_S_POINTER_0 +#define CSC_S_POINTER_0 _MK_ADDR_CONST(0x4004) +#define CSC_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CSC_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CSC_S_POINTER_0_PRODUCER_SHIFT) +#define CSC_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CSC_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CSC_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CSC_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CSC_S_POINTER_0_CONSUMER_SHIFT) +#define CSC_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CSC_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CSC_D_OP_ENABLE_0 +#define CSC_D_OP_ENABLE_0 _MK_ADDR_CONST(0x4008) +#define CSC_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CSC_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CSC_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CSC_D_MISC_CFG_0 +#define CSC_D_MISC_CFG_0 _MK_ADDR_CONST(0x400c) +#define CSC_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CSC_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT _MK_SHIFT_CONST(8) +#define CSC_D_MISC_CFG_0_IN_PRECISION_FIELD _MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT) +#define CSC_D_MISC_CFG_0_IN_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_IN_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_IN_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_MISC_CFG_0_DATA_REUSE_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT) +#define CSC_D_MISC_CFG_0_DATA_REUSE_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_DATA_REUSE_ENABLE _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT _MK_SHIFT_CONST(20) +#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT) +#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT _MK_SHIFT_CONST(24) +#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT) +#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT _MK_SHIFT_CONST(28) +#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT) +#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CSC_D_DATAIN_FORMAT_0 +#define CSC_D_DATAIN_FORMAT_0 _MK_ADDR_CONST(0x4010) +#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD _MK_FIELD_CONST(0x1, CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT) +#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE _MK_ENUM_CONST(0x0) +#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL _MK_ENUM_CONST(0x1) + + +// Register CSC_D_DATAIN_SIZE_EXT_0_0 +#define CSC_D_DATAIN_SIZE_EXT_0_0 _MK_ADDR_CONST(0x4014) +#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT) +#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT) + + +// Register CSC_D_DATAIN_SIZE_EXT_1_0 +#define CSC_D_DATAIN_SIZE_EXT_1_0 _MK_ADDR_CONST(0x4018) +#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT) + + +// Register CSC_D_BATCH_NUMBER_0 +#define CSC_D_BATCH_NUMBER_0 _MK_ADDR_CONST(0x401c) +#define CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_BATCH_NUMBER_0_BATCHES_FIELD _MK_FIELD_CONST(0x1f, CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT) + + +// Register CSC_D_POST_Y_EXTENSION_0 +#define CSC_D_POST_Y_EXTENSION_0 _MK_ADDR_CONST(0x4020) +#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_FIELD _MK_FIELD_CONST(0x3, CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT) + + +// Register CSC_D_ENTRY_PER_SLICE_0 +#define CSC_D_ENTRY_PER_SLICE_0 _MK_ADDR_CONST(0x4024) +#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD _MK_FIELD_CONST(0x3fff, CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT) + + +// Register CSC_D_WEIGHT_FORMAT_0 +#define CSC_D_WEIGHT_FORMAT_0 _MK_ADDR_CONST(0x4028) +#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD _MK_FIELD_CONST(0x1, CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT) +#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED _MK_ENUM_CONST(0x0) +#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED _MK_ENUM_CONST(0x1) + + +// Register CSC_D_WEIGHT_SIZE_EXT_0_0 +#define CSC_D_WEIGHT_SIZE_EXT_0_0 _MK_ADDR_CONST(0x402c) +#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT) +#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT) + + +// Register CSC_D_WEIGHT_SIZE_EXT_1_0 +#define CSC_D_WEIGHT_SIZE_EXT_1_0 _MK_ADDR_CONST(0x4030) +#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT) +#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT) + + +// Register CSC_D_WEIGHT_BYTES_0 +#define CSC_D_WEIGHT_BYTES_0 _MK_ADDR_CONST(0x4034) +#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD _MK_FIELD_CONST(0xffffffff, CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT) + + +// Register CSC_D_WMB_BYTES_0 +#define CSC_D_WMB_BYTES_0 _MK_ADDR_CONST(0x4038) +#define CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WMB_BYTES_0_WMB_BYTES_FIELD _MK_FIELD_CONST(0xfffffff, CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT) + + +// Register CSC_D_DATAOUT_SIZE_0_0 +#define CSC_D_DATAOUT_SIZE_0_0 _MK_ADDR_CONST(0x403c) +#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT) +#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT) + + +// Register CSC_D_DATAOUT_SIZE_1_0 +#define CSC_D_DATAOUT_SIZE_1_0 _MK_ADDR_CONST(0x4040) +#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT) + + +// Register CSC_D_ATOMICS_0 +#define CSC_D_ATOMICS_0 _MK_ADDR_CONST(0x4044) +#define CSC_D_ATOMICS_0_ATOMICS_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_ATOMICS_0_ATOMICS_FIELD _MK_FIELD_CONST(0x1fffff, CSC_D_ATOMICS_0_ATOMICS_SHIFT) + + +// Register CSC_D_RELEASE_0 +#define CSC_D_RELEASE_0 _MK_ADDR_CONST(0x4048) +#define CSC_D_RELEASE_0_RLS_SLICES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_RELEASE_0_RLS_SLICES_FIELD _MK_FIELD_CONST(0xfff, CSC_D_RELEASE_0_RLS_SLICES_SHIFT) + + +// Register CSC_D_CONV_STRIDE_EXT_0 +#define CSC_D_CONV_STRIDE_EXT_0 _MK_ADDR_CONST(0x404c) +#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_FIELD _MK_FIELD_CONST(0x7, CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT) +#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_FIELD _MK_FIELD_CONST(0x7, CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT) + + +// Register CSC_D_DILATION_EXT_0 +#define CSC_D_DILATION_EXT_0 _MK_ADDR_CONST(0x4050) +#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT) +#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT) + + +// Register CSC_D_ZERO_PADDING_0 +#define CSC_D_ZERO_PADDING_0 _MK_ADDR_CONST(0x4054) +#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_ZERO_PADDING_0_PAD_LEFT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT) +#define CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_ZERO_PADDING_0_PAD_TOP_FIELD _MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT) + + +// Register CSC_D_ZERO_PADDING_VALUE_0 +#define CSC_D_ZERO_PADDING_VALUE_0 _MK_ADDR_CONST(0x4058) +#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD _MK_FIELD_CONST(0xffff, CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT) + + +// Register CSC_D_BANK_0 +#define CSC_D_BANK_0 _MK_ADDR_CONST(0x405c) +#define CSC_D_BANK_0_DATA_BANK_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_BANK_0_DATA_BANK_FIELD _MK_FIELD_CONST(0x1f, CSC_D_BANK_0_DATA_BANK_SHIFT) +#define CSC_D_BANK_0_WEIGHT_BANK_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_BANK_0_WEIGHT_BANK_FIELD _MK_FIELD_CONST(0x1f, CSC_D_BANK_0_WEIGHT_BANK_SHIFT) + + +// Register CSC_D_PRA_CFG_0 +#define CSC_D_PRA_CFG_0 _MK_ADDR_CONST(0x4060) +#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_FIELD _MK_FIELD_CONST(0x3, CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT) + + +// Register CSC_D_CYA_0 +#define CSC_D_CYA_0 _MK_ADDR_CONST(0x4064) +#define CSC_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CSC_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CMAC_A_S_STATUS_0 +#define CMAC_A_S_STATUS_0 _MK_ADDR_CONST(0x5000) +#define CMAC_A_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_A_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_0_SHIFT) +#define CMAC_A_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CMAC_A_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CMAC_A_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CMAC_A_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CMAC_A_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_1_SHIFT) +#define CMAC_A_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CMAC_A_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CMAC_A_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CMAC_A_S_POINTER_0 +#define CMAC_A_S_POINTER_0 _MK_ADDR_CONST(0x5004) +#define CMAC_A_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_A_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_PRODUCER_SHIFT) +#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CMAC_A_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CMAC_A_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_CONSUMER_SHIFT) +#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CMAC_A_D_OP_ENABLE_0 +#define CMAC_A_D_OP_ENABLE_0 _MK_ADDR_CONST(0x5008) +#define CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_A_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CMAC_A_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CMAC_A_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CMAC_A_D_MISC_CFG_0 +#define CMAC_A_D_MISC_CFG_0 _MK_ADDR_CONST(0x500c) +#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_A_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CMAC_B_S_STATUS_0 +#define CMAC_B_S_STATUS_0 _MK_ADDR_CONST(0x6000) +#define CMAC_B_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_B_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_0_SHIFT) +#define CMAC_B_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CMAC_B_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CMAC_B_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CMAC_B_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CMAC_B_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_1_SHIFT) +#define CMAC_B_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CMAC_B_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CMAC_B_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CMAC_B_S_POINTER_0 +#define CMAC_B_S_POINTER_0 _MK_ADDR_CONST(0x6004) +#define CMAC_B_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_B_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_PRODUCER_SHIFT) +#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CMAC_B_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CMAC_B_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_CONSUMER_SHIFT) +#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CMAC_B_D_OP_ENABLE_0 +#define CMAC_B_D_OP_ENABLE_0 _MK_ADDR_CONST(0x6008) +#define CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_B_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CMAC_B_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CMAC_B_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CMAC_B_D_MISC_CFG_0 +#define CMAC_B_D_MISC_CFG_0 _MK_ADDR_CONST(0x600c) +#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_B_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CACC_S_STATUS_0 +#define CACC_S_STATUS_0 _MK_ADDR_CONST(0x7000) +#define CACC_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CACC_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_0_SHIFT) +#define CACC_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CACC_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CACC_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CACC_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CACC_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_1_SHIFT) +#define CACC_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CACC_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CACC_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CACC_S_POINTER_0 +#define CACC_S_POINTER_0 _MK_ADDR_CONST(0x7004) +#define CACC_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CACC_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CACC_S_POINTER_0_PRODUCER_SHIFT) +#define CACC_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CACC_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CACC_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CACC_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CACC_S_POINTER_0_CONSUMER_SHIFT) +#define CACC_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CACC_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CACC_D_OP_ENABLE_0 +#define CACC_D_OP_ENABLE_0 _MK_ADDR_CONST(0x7008) +#define CACC_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CACC_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CACC_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CACC_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CACC_D_MISC_CFG_0 +#define CACC_D_MISC_CFG_0 _MK_ADDR_CONST(0x700c) +#define CACC_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CACC_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CACC_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CACC_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + +// Register CACC_D_DATAOUT_SIZE_0_0 +#define CACC_D_DATAOUT_SIZE_0_0 _MK_ADDR_CONST(0x7010) +#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT) +#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT _MK_SHIFT_CONST(16) +#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT) + + +// Register CACC_D_DATAOUT_SIZE_1_0 +#define CACC_D_DATAOUT_SIZE_1_0 _MK_ADDR_CONST(0x7014) +#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT) + + +// Register CACC_D_DATAOUT_ADDR_0 +#define CACC_D_DATAOUT_ADDR_0 _MK_ADDR_CONST(0x7018) +#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_FIELD _MK_FIELD_CONST(0xffffffff, CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT) + + +// Register CACC_D_BATCH_NUMBER_0 +#define CACC_D_BATCH_NUMBER_0 _MK_ADDR_CONST(0x701c) +#define CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_BATCH_NUMBER_0_BATCHES_FIELD _MK_FIELD_CONST(0x1f, CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT) + + +// Register CACC_D_LINE_STRIDE_0 +#define CACC_D_LINE_STRIDE_0 _MK_ADDR_CONST(0x7020) +#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffff, CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT) + + +// Register CACC_D_SURF_STRIDE_0 +#define CACC_D_SURF_STRIDE_0 _MK_ADDR_CONST(0x7024) +#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_FIELD _MK_FIELD_CONST(0xffffff, CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT) + + +// Register CACC_D_DATAOUT_MAP_0 +#define CACC_D_DATAOUT_MAP_0 _MK_ADDR_CONST(0x7028) +#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FIELD _MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT) +#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FALSE _MK_ENUM_CONST(0x0) +#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE _MK_ENUM_CONST(0x1) +#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT _MK_SHIFT_CONST(16) +#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FIELD _MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT) +#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FALSE _MK_ENUM_CONST(0x0) +#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE _MK_ENUM_CONST(0x1) + + +// Register CACC_D_CLIP_CFG_0 +#define CACC_D_CLIP_CFG_0 _MK_ADDR_CONST(0x702c) +#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_FIELD _MK_FIELD_CONST(0x1f, CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT) + + +// Register CACC_D_OUT_SATURATION_0 +#define CACC_D_OUT_SATURATION_0 _MK_ADDR_CONST(0x7030) +#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_OUT_SATURATION_0_SAT_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT) + + +// Register CACC_D_CYA_0 +#define CACC_D_CYA_0 _MK_ADDR_CONST(0x7034) +#define CACC_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CACC_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register SDP_RDMA_S_STATUS_0 +#define SDP_RDMA_S_STATUS_0 _MK_ADDR_CONST(0x8000) +#define SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT) +#define SDP_RDMA_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define SDP_RDMA_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define SDP_RDMA_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT) +#define SDP_RDMA_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define SDP_RDMA_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register SDP_RDMA_S_POINTER_0 +#define SDP_RDMA_S_POINTER_0 _MK_ADDR_CONST(0x8004) +#define SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT) +#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define SDP_RDMA_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT) +#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_OP_ENABLE_0 +#define SDP_RDMA_D_OP_ENABLE_0 _MK_ADDR_CONST(0x8008) +#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT) +#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_DATA_CUBE_WIDTH_0 +#define SDP_RDMA_D_DATA_CUBE_WIDTH_0 _MK_ADDR_CONST(0x800c) +#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT) + + +// Register SDP_RDMA_D_DATA_CUBE_HEIGHT_0 +#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0 _MK_ADDR_CONST(0x8010) +#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT) + + +// Register SDP_RDMA_D_DATA_CUBE_CHANNEL_0 +#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0 _MK_ADDR_CONST(0x8014) +#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT) + + +// Register SDP_RDMA_D_SRC_BASE_ADDR_LOW_0 +#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x8018) +#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 +#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x801c) +#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_RDMA_D_SRC_LINE_STRIDE_0 +#define SDP_RDMA_D_SRC_LINE_STRIDE_0 _MK_ADDR_CONST(0x8020) +#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_SRC_SURFACE_STRIDE_0 +#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x8024) +#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BRDMA_CFG_0 +#define SDP_RDMA_D_BRDMA_CFG_0 _MK_ADDR_CONST(0x8028) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_YES _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_MUL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_ALU _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_BOTH _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT _MK_SHIFT_CONST(3) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_ONE_BYTE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_TWO_BYTE _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT _MK_SHIFT_CONST(4) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_KERNEL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_ELEMENT _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT _MK_SHIFT_CONST(5) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_BS_BASE_ADDR_LOW_0 +#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x802c) +#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_RDMA_D_BS_BASE_ADDR_HIGH_0 +#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x8030) +#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_RDMA_D_BS_LINE_STRIDE_0 +#define SDP_RDMA_D_BS_LINE_STRIDE_0 _MK_ADDR_CONST(0x8034) +#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BS_SURFACE_STRIDE_0 +#define SDP_RDMA_D_BS_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x8038) +#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BS_BATCH_STRIDE_0 +#define SDP_RDMA_D_BS_BATCH_STRIDE_0 _MK_ADDR_CONST(0x803c) +#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_NRDMA_CFG_0 +#define SDP_RDMA_D_NRDMA_CFG_0 _MK_ADDR_CONST(0x8040) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_YES _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_MUL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_ALU _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_BOTH _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT _MK_SHIFT_CONST(3) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_ONE_BYTE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_TWO_BYTE _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT _MK_SHIFT_CONST(4) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_KERNEL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_ELEMENT _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT _MK_SHIFT_CONST(5) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_BN_BASE_ADDR_LOW_0 +#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x8044) +#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_RDMA_D_BN_BASE_ADDR_HIGH_0 +#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x8048) +#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_RDMA_D_BN_LINE_STRIDE_0 +#define SDP_RDMA_D_BN_LINE_STRIDE_0 _MK_ADDR_CONST(0x804c) +#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BN_SURFACE_STRIDE_0 +#define SDP_RDMA_D_BN_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x8050) +#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BN_BATCH_STRIDE_0 +#define SDP_RDMA_D_BN_BATCH_STRIDE_0 _MK_ADDR_CONST(0x8054) +#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_ERDMA_CFG_0 +#define SDP_RDMA_D_ERDMA_CFG_0 _MK_ADDR_CONST(0x8058) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_YES _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_MUL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_ALU _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_BOTH _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT _MK_SHIFT_CONST(3) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_ONE_BYTE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_TWO_BYTE _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT _MK_SHIFT_CONST(4) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_KERNEL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_ELEMENT _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT _MK_SHIFT_CONST(5) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_EW_BASE_ADDR_LOW_0 +#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x805c) +#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_RDMA_D_EW_BASE_ADDR_HIGH_0 +#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x8060) +#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_RDMA_D_EW_LINE_STRIDE_0 +#define SDP_RDMA_D_EW_LINE_STRIDE_0 _MK_ADDR_CONST(0x8064) +#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_EW_SURFACE_STRIDE_0 +#define SDP_RDMA_D_EW_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x8068) +#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_EW_BATCH_STRIDE_0 +#define SDP_RDMA_D_EW_BATCH_STRIDE_0 _MK_ADDR_CONST(0x806c) +#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_FEATURE_MODE_CFG_0 +#define SDP_RDMA_D_FEATURE_MODE_CFG_0 _MK_ADDR_CONST(0x8070) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_ON _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT _MK_SHIFT_CONST(2) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(4) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT _MK_SHIFT_CONST(6) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT _MK_SHIFT_CONST(8) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD _MK_FIELD_CONST(0x1f, SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT) + + +// Register SDP_RDMA_D_SRC_DMA_CFG_0 +#define SDP_RDMA_D_SRC_DMA_CFG_0 _MK_ADDR_CONST(0x8074) +#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT) +#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0 +#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0 _MK_ADDR_CONST(0x8078) +#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT) + + +// Register SDP_RDMA_D_STATUS_INF_INPUT_NUM_0 +#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0 _MK_ADDR_CONST(0x807c) +#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT) + + +// Register SDP_RDMA_D_PERF_ENABLE_0 +#define SDP_RDMA_D_PERF_ENABLE_0 _MK_ADDR_CONST(0x8080) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_YES _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_PERF_MRDMA_READ_STALL_0 +#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0 _MK_ADDR_CONST(0x8084) +#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT) + + +// Register SDP_RDMA_D_PERF_BRDMA_READ_STALL_0 +#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0 _MK_ADDR_CONST(0x8088) +#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT) + + +// Register SDP_RDMA_D_PERF_NRDMA_READ_STALL_0 +#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0 _MK_ADDR_CONST(0x808c) +#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT) + + +// Register SDP_RDMA_D_PERF_ERDMA_READ_STALL_0 +#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0 _MK_ADDR_CONST(0x8090) +#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register SDP_S_STATUS_0 +#define SDP_S_STATUS_0 _MK_ADDR_CONST(0x9000) +#define SDP_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_0_SHIFT) +#define SDP_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define SDP_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define SDP_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define SDP_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_1_SHIFT) +#define SDP_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define SDP_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define SDP_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register SDP_S_POINTER_0 +#define SDP_S_POINTER_0 _MK_ADDR_CONST(0x9004) +#define SDP_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, SDP_S_POINTER_0_PRODUCER_SHIFT) +#define SDP_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define SDP_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define SDP_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, SDP_S_POINTER_0_CONSUMER_SHIFT) +#define SDP_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define SDP_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register SDP_S_LUT_ACCESS_CFG_0 +#define SDP_S_LUT_ACCESS_CFG_0 _MK_ADDR_CONST(0x9008) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD _MK_FIELD_CONST(0x3ff, SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO _MK_ENUM_CONST(0x1) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(17) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE _MK_ENUM_CONST(0x1) + + +// Register SDP_S_LUT_ACCESS_DATA_0 +#define SDP_S_LUT_ACCESS_DATA_0 _MK_ADDR_CONST(0x900c) +#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT) + + +// Register SDP_S_LUT_CFG_0 +#define SDP_S_LUT_CFG_0 _MK_ADDR_CONST(0x9010) +#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT) +#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR _MK_ENUM_CONST(0x1) +#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT _MK_SHIFT_CONST(4) +#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT) +#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO _MK_ENUM_CONST(0x1) +#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT _MK_SHIFT_CONST(5) +#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT) +#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO _MK_ENUM_CONST(0x1) +#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT _MK_SHIFT_CONST(6) +#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT) +#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO _MK_ENUM_CONST(0x1) + + +// Register SDP_S_LUT_INFO_0 +#define SDP_S_LUT_INFO_0 _MK_ADDR_CONST(0x9014) +#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT) +#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT) +#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT) + + +// Register SDP_S_LUT_LE_START_0 +#define SDP_S_LUT_LE_START_0 _MK_ADDR_CONST(0x9018) +#define SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LE_START_0_LUT_LE_START_FIELD _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT) + + +// Register SDP_S_LUT_LE_END_0 +#define SDP_S_LUT_LE_END_0 _MK_ADDR_CONST(0x901c) +#define SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LE_END_0_LUT_LE_END_FIELD _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT) + + +// Register SDP_S_LUT_LO_START_0 +#define SDP_S_LUT_LO_START_0 _MK_ADDR_CONST(0x9020) +#define SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LO_START_0_LUT_LO_START_FIELD _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT) + + +// Register SDP_S_LUT_LO_END_0 +#define SDP_S_LUT_LO_END_0 _MK_ADDR_CONST(0x9024) +#define SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LO_END_0_LUT_LO_END_FIELD _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT) + + +// Register SDP_S_LUT_LE_SLOPE_SCALE_0 +#define SDP_S_LUT_LE_SLOPE_SCALE_0 _MK_ADDR_CONST(0x9028) +#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT) +#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT) + + +// Register SDP_S_LUT_LE_SLOPE_SHIFT_0 +#define SDP_S_LUT_LE_SLOPE_SHIFT_0 _MK_ADDR_CONST(0x902c) +#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT) +#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(5) +#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT) + + +// Register SDP_S_LUT_LO_SLOPE_SCALE_0 +#define SDP_S_LUT_LO_SLOPE_SCALE_0 _MK_ADDR_CONST(0x9030) +#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT) +#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT) + + +// Register SDP_S_LUT_LO_SLOPE_SHIFT_0 +#define SDP_S_LUT_LO_SLOPE_SHIFT_0 _MK_ADDR_CONST(0x9034) +#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT) +#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(5) +#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT) + + +// Register SDP_D_OP_ENABLE_0 +#define SDP_D_OP_ENABLE_0 _MK_ADDR_CONST(0x9038) +#define SDP_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_OP_ENABLE_0_OP_EN_SHIFT) +#define SDP_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define SDP_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DATA_CUBE_WIDTH_0 +#define SDP_D_DATA_CUBE_WIDTH_0 _MK_ADDR_CONST(0x903c) +#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT) + + +// Register SDP_D_DATA_CUBE_HEIGHT_0 +#define SDP_D_DATA_CUBE_HEIGHT_0 _MK_ADDR_CONST(0x9040) +#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT) + + +// Register SDP_D_DATA_CUBE_CHANNEL_0 +#define SDP_D_DATA_CUBE_CHANNEL_0 _MK_ADDR_CONST(0x9044) +#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT) + + +// Register SDP_D_DST_BASE_ADDR_LOW_0 +#define SDP_D_DST_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x9048) +#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_D_DST_BASE_ADDR_HIGH_0 +#define SDP_D_DST_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x904c) +#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_D_DST_LINE_STRIDE_0 +#define SDP_D_DST_LINE_STRIDE_0 _MK_ADDR_CONST(0x9050) +#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT) + + +// Register SDP_D_DST_SURFACE_STRIDE_0 +#define SDP_D_DST_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x9054) +#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT) + + +// Register SDP_D_DP_BS_CFG_0 +#define SDP_D_DP_BS_CFG_0 _MK_ADDR_CONST(0x9058) +#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_CFG_0_BS_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_FIELD _MK_FIELD_CONST(0x3, SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MAX _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MIN _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SUM _MK_ENUM_CONST(0x2) +#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT _MK_SHIFT_CONST(4) +#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT _MK_SHIFT_CONST(5) +#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT _MK_SHIFT_CONST(6) +#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_BS_ALU_CFG_0 +#define SDP_D_DP_BS_ALU_CFG_0 _MK_ADDR_CONST(0x905c) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_FIELD _MK_FIELD_CONST(0x3f, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT) + + +// Register SDP_D_DP_BS_ALU_SRC_VALUE_0 +#define SDP_D_DP_BS_ALU_SRC_VALUE_0 _MK_ADDR_CONST(0x9060) +#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT) + + +// Register SDP_D_DP_BS_MUL_CFG_0 +#define SDP_D_DP_BS_MUL_CFG_0 _MK_ADDR_CONST(0x9064) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_FIELD _MK_FIELD_CONST(0xff, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT) + + +// Register SDP_D_DP_BS_MUL_SRC_VALUE_0 +#define SDP_D_DP_BS_MUL_SRC_VALUE_0 _MK_ADDR_CONST(0x9068) +#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT) + + +// Register SDP_D_DP_BN_CFG_0 +#define SDP_D_DP_BN_CFG_0 _MK_ADDR_CONST(0x906c) +#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_CFG_0_BN_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_FIELD _MK_FIELD_CONST(0x3, SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MAX _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MIN _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SUM _MK_ENUM_CONST(0x2) +#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT _MK_SHIFT_CONST(4) +#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT _MK_SHIFT_CONST(5) +#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT _MK_SHIFT_CONST(6) +#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_BN_ALU_CFG_0 +#define SDP_D_DP_BN_ALU_CFG_0 _MK_ADDR_CONST(0x9070) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_FIELD _MK_FIELD_CONST(0x3f, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT) + + +// Register SDP_D_DP_BN_ALU_SRC_VALUE_0 +#define SDP_D_DP_BN_ALU_SRC_VALUE_0 _MK_ADDR_CONST(0x9074) +#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT) + + +// Register SDP_D_DP_BN_MUL_CFG_0 +#define SDP_D_DP_BN_MUL_CFG_0 _MK_ADDR_CONST(0x9078) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_FIELD _MK_FIELD_CONST(0xff, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT) + + +// Register SDP_D_DP_BN_MUL_SRC_VALUE_0 +#define SDP_D_DP_BN_MUL_SRC_VALUE_0 _MK_ADDR_CONST(0x907c) +#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT) + + +// Register SDP_D_DP_EW_CFG_0 +#define SDP_D_DP_EW_CFG_0 _MK_ADDR_CONST(0x9080) +#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_CFG_0_EW_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_FIELD _MK_FIELD_CONST(0x3, SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MAX _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MIN _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SUM _MK_ENUM_CONST(0x2) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_EQL _MK_ENUM_CONST(0x3) +#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT _MK_SHIFT_CONST(4) +#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT _MK_SHIFT_CONST(5) +#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT _MK_SHIFT_CONST(6) +#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_EW_ALU_CFG_0 +#define SDP_D_DP_EW_ALU_CFG_0 _MK_ADDR_CONST(0x9084) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_EW_ALU_SRC_VALUE_0 +#define SDP_D_DP_EW_ALU_SRC_VALUE_0 _MK_ADDR_CONST(0x9088) +#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT) + + +// Register SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0 +#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0 _MK_ADDR_CONST(0x908c) +#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT) + + +// Register SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0 +#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0 _MK_ADDR_CONST(0x9090) +#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT) + + +// Register SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0 +#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0 _MK_ADDR_CONST(0x9094) +#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_FIELD _MK_FIELD_CONST(0x3f, SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT) + + +// Register SDP_D_DP_EW_MUL_CFG_0 +#define SDP_D_DP_EW_MUL_CFG_0 _MK_ADDR_CONST(0x9098) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_EW_MUL_SRC_VALUE_0 +#define SDP_D_DP_EW_MUL_SRC_VALUE_0 _MK_ADDR_CONST(0x909c) +#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT) + + +// Register SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0 +#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0 _MK_ADDR_CONST(0x90a0) +#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT) + + +// Register SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0 +#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0 _MK_ADDR_CONST(0x90a4) +#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT) + + +// Register SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0 +#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0 _MK_ADDR_CONST(0x90a8) +#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_FIELD _MK_FIELD_CONST(0x3f, SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT) + + +// Register SDP_D_DP_EW_TRUNCATE_VALUE_0 +#define SDP_D_DP_EW_TRUNCATE_VALUE_0 _MK_ADDR_CONST(0x90ac) +#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_FIELD _MK_FIELD_CONST(0x3ff, SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT) + + +// Register SDP_D_FEATURE_MODE_CFG_0 +#define SDP_D_FEATURE_MODE_CFG_0 _MK_ADDR_CONST(0x90b0) +#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT) +#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF _MK_ENUM_CONST(0x0) +#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON _MK_ENUM_CONST(0x1) +#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_FIELD _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT) +#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_MEM _MK_ENUM_CONST(0x0) +#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PDP _MK_ENUM_CONST(0x1) +#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT) +#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF _MK_ENUM_CONST(0x0) +#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_ON _MK_ENUM_CONST(0x1) +#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT _MK_SHIFT_CONST(3) +#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_FIELD _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT) +#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DISABLE _MK_ENUM_CONST(0x0) +#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_ENABLE _MK_ENUM_CONST(0x1) +#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD _MK_FIELD_CONST(0x1f, SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT) + + +// Register SDP_D_DST_DMA_CFG_0 +#define SDP_D_DST_DMA_CFG_0 _MK_ADDR_CONST(0x90b4) +#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT) +#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DST_BATCH_STRIDE_0 +#define SDP_D_DST_BATCH_STRIDE_0 _MK_ADDR_CONST(0x90b8) +#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT) + + +// Register SDP_D_DATA_FORMAT_0 +#define SDP_D_DATA_FORMAT_0 _MK_ADDR_CONST(0x90bc) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + +// Register SDP_D_CVT_OFFSET_0 +#define SDP_D_CVT_OFFSET_0 _MK_ADDR_CONST(0x90c0) +#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT) + + +// Register SDP_D_CVT_SCALE_0 +#define SDP_D_CVT_SCALE_0 _MK_ADDR_CONST(0x90c4) +#define SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_CVT_SCALE_0_CVT_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT) + + +// Register SDP_D_CVT_SHIFT_0 +#define SDP_D_CVT_SHIFT_0 _MK_ADDR_CONST(0x90c8) +#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_FIELD _MK_FIELD_CONST(0x3f, SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT) + + +// Register SDP_D_STATUS_0 +#define SDP_D_STATUS_0 _MK_ADDR_CONST(0x90cc) +#define SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_STATUS_0_STATUS_UNEQUAL_FIELD _MK_FIELD_CONST(0x1, SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT) + + +// Register SDP_D_STATUS_NAN_INPUT_NUM_0 +#define SDP_D_STATUS_NAN_INPUT_NUM_0 _MK_ADDR_CONST(0x90d0) +#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT) + + +// Register SDP_D_STATUS_INF_INPUT_NUM_0 +#define SDP_D_STATUS_INF_INPUT_NUM_0 _MK_ADDR_CONST(0x90d4) +#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT) + + +// Register SDP_D_STATUS_NAN_OUTPUT_NUM_0 +#define SDP_D_STATUS_NAN_OUTPUT_NUM_0 _MK_ADDR_CONST(0x90d8) +#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT) + + +// Register SDP_D_PERF_ENABLE_0 +#define SDP_D_PERF_ENABLE_0 _MK_ADDR_CONST(0x90dc) +#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT) +#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_YES _MK_ENUM_CONST(0x1) +#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT) +#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_YES _MK_ENUM_CONST(0x1) +#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT) +#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_YES _MK_ENUM_CONST(0x1) +#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT _MK_SHIFT_CONST(3) +#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT) +#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_PERF_WDMA_WRITE_STALL_0 +#define SDP_D_PERF_WDMA_WRITE_STALL_0 _MK_ADDR_CONST(0x90e0) +#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT) + + +// Register SDP_D_PERF_LUT_UFLOW_0 +#define SDP_D_PERF_LUT_UFLOW_0 _MK_ADDR_CONST(0x90e4) +#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT) + + +// Register SDP_D_PERF_LUT_OFLOW_0 +#define SDP_D_PERF_LUT_OFLOW_0 _MK_ADDR_CONST(0x90e8) +#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT) + + +// Register SDP_D_PERF_OUT_SATURATION_0 +#define SDP_D_PERF_OUT_SATURATION_0 _MK_ADDR_CONST(0x90ec) +#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT) + + +// Register SDP_D_PERF_LUT_HYBRID_0 +#define SDP_D_PERF_LUT_HYBRID_0 _MK_ADDR_CONST(0x90f0) +#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT) + + +// Register SDP_D_PERF_LUT_LE_HIT_0 +#define SDP_D_PERF_LUT_LE_HIT_0 _MK_ADDR_CONST(0x90f4) +#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT) + + +// Register SDP_D_PERF_LUT_LO_HIT_0 +#define SDP_D_PERF_LUT_LO_HIT_0 _MK_ADDR_CONST(0x90f8) +#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register PDP_RDMA_S_STATUS_0 +#define PDP_RDMA_S_STATUS_0 _MK_ADDR_CONST(0xa000) +#define PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT) +#define PDP_RDMA_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define PDP_RDMA_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define PDP_RDMA_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define PDP_RDMA_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT) +#define PDP_RDMA_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define PDP_RDMA_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define PDP_RDMA_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register PDP_RDMA_S_POINTER_0 +#define PDP_RDMA_S_POINTER_0 _MK_ADDR_CONST(0xa004) +#define PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT) +#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define PDP_RDMA_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT) +#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_OP_ENABLE_0 +#define PDP_RDMA_D_OP_ENABLE_0 _MK_ADDR_CONST(0xa008) +#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT) +#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0 +#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0 _MK_ADDR_CONST(0xa00c) +#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT) + + +// Register PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0 +#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0 _MK_ADDR_CONST(0xa010) +#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT) + + +// Register PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0 +#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0 _MK_ADDR_CONST(0xa014) +#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT) + + +// Register PDP_RDMA_D_FLYING_MODE_0 +#define PDP_RDMA_D_FLYING_MODE_0 _MK_ADDR_CONST(0xa018) +#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT) +#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_ON_FLYING _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_OFF_FLYING _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_SRC_BASE_ADDR_LOW_0 +#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xa01c) +#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT) + + +// Register PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 +#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xa020) +#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT) + + +// Register PDP_RDMA_D_SRC_LINE_STRIDE_0 +#define PDP_RDMA_D_SRC_LINE_STRIDE_0 _MK_ADDR_CONST(0xa024) +#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT) + + +// Register PDP_RDMA_D_SRC_SURFACE_STRIDE_0 +#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xa028) +#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT) + + +// Register PDP_RDMA_D_SRC_RAM_CFG_0 +#define PDP_RDMA_D_SRC_RAM_CFG_0 _MK_ADDR_CONST(0xa02c) +#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT) +#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_DATA_FORMAT_0 +#define PDP_RDMA_D_DATA_FORMAT_0 _MK_ADDR_CONST(0xa030) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x3, PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8 _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16 _MK_ENUM_CONST(0x1) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16 _MK_ENUM_CONST(0x2) + + +// Register PDP_RDMA_D_OPERATION_MODE_CFG_0 +#define PDP_RDMA_D_OPERATION_MODE_CFG_0 _MK_ADDR_CONST(0xa034) +#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD _MK_FIELD_CONST(0xff, PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT) + + +// Register PDP_RDMA_D_POOLING_KERNEL_CFG_0 +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0 _MK_ADDR_CONST(0xa038) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 _MK_ENUM_CONST(0x1) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 _MK_ENUM_CONST(0x2) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 _MK_ENUM_CONST(0x3) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 _MK_ENUM_CONST(0x4) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 _MK_ENUM_CONST(0x5) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 _MK_ENUM_CONST(0x6) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 _MK_ENUM_CONST(0x7) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT _MK_SHIFT_CONST(4) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT) + + +// Register PDP_RDMA_D_POOLING_PADDING_CFG_0 +#define PDP_RDMA_D_POOLING_PADDING_CFG_0 _MK_ADDR_CONST(0xa03c) +#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT) + + +// Register PDP_RDMA_D_PARTIAL_WIDTH_IN_0 +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0 _MK_ADDR_CONST(0xa040) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT _MK_SHIFT_CONST(10) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT _MK_SHIFT_CONST(20) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT) + + +// Register PDP_RDMA_D_PERF_ENABLE_0 +#define PDP_RDMA_D_PERF_ENABLE_0 _MK_ADDR_CONST(0xa044) +#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT) +#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_PERF_READ_STALL_0 +#define PDP_RDMA_D_PERF_READ_STALL_0 _MK_ADDR_CONST(0xa048) +#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT) + + +// Register PDP_RDMA_D_CYA_0 +#define PDP_RDMA_D_CYA_0 _MK_ADDR_CONST(0xa04c) +#define PDP_RDMA_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register PDP_S_STATUS_0 +#define PDP_S_STATUS_0 _MK_ADDR_CONST(0xb000) +#define PDP_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define PDP_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_0_SHIFT) +#define PDP_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define PDP_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define PDP_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define PDP_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define PDP_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_1_SHIFT) +#define PDP_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define PDP_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define PDP_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register PDP_S_POINTER_0 +#define PDP_S_POINTER_0 _MK_ADDR_CONST(0xb004) +#define PDP_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define PDP_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, PDP_S_POINTER_0_PRODUCER_SHIFT) +#define PDP_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define PDP_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define PDP_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define PDP_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, PDP_S_POINTER_0_CONSUMER_SHIFT) +#define PDP_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define PDP_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register PDP_D_OP_ENABLE_0 +#define PDP_D_OP_ENABLE_0 _MK_ADDR_CONST(0xb008) +#define PDP_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, PDP_D_OP_ENABLE_0_OP_EN_SHIFT) +#define PDP_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_D_DATA_CUBE_IN_WIDTH_0 +#define PDP_D_DATA_CUBE_IN_WIDTH_0 _MK_ADDR_CONST(0xb00c) +#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT) + + +// Register PDP_D_DATA_CUBE_IN_HEIGHT_0 +#define PDP_D_DATA_CUBE_IN_HEIGHT_0 _MK_ADDR_CONST(0xb010) +#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT) + + +// Register PDP_D_DATA_CUBE_IN_CHANNEL_0 +#define PDP_D_DATA_CUBE_IN_CHANNEL_0 _MK_ADDR_CONST(0xb014) +#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT) + + +// Register PDP_D_DATA_CUBE_OUT_WIDTH_0 +#define PDP_D_DATA_CUBE_OUT_WIDTH_0 _MK_ADDR_CONST(0xb018) +#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT) + + +// Register PDP_D_DATA_CUBE_OUT_HEIGHT_0 +#define PDP_D_DATA_CUBE_OUT_HEIGHT_0 _MK_ADDR_CONST(0xb01c) +#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT) + + +// Register PDP_D_DATA_CUBE_OUT_CHANNEL_0 +#define PDP_D_DATA_CUBE_OUT_CHANNEL_0 _MK_ADDR_CONST(0xb020) +#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT) + + +// Register PDP_D_OPERATION_MODE_CFG_0 +#define PDP_D_OPERATION_MODE_CFG_0 _MK_ADDR_CONST(0xb024) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_FIELD _MK_FIELD_CONST(0x3, PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE _MK_ENUM_CONST(0x0) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX _MK_ENUM_CONST(0x1) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN _MK_ENUM_CONST(0x2) +#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT _MK_SHIFT_CONST(4) +#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_FIELD _MK_FIELD_CONST(0x1, PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT) +#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING _MK_ENUM_CONST(0x0) +#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING _MK_ENUM_CONST(0x1) +#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT _MK_SHIFT_CONST(8) +#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD _MK_FIELD_CONST(0xff, PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT) + + +// Register PDP_D_NAN_FLUSH_TO_ZERO_0 +#define PDP_D_NAN_FLUSH_TO_ZERO_0 _MK_ADDR_CONST(0xb028) +#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD _MK_FIELD_CONST(0x1, PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT) +#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_D_PARTIAL_WIDTH_IN_0 +#define PDP_D_PARTIAL_WIDTH_IN_0 _MK_ADDR_CONST(0xb02c) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT _MK_SHIFT_CONST(10) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT _MK_SHIFT_CONST(20) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT) + + +// Register PDP_D_PARTIAL_WIDTH_OUT_0 +#define PDP_D_PARTIAL_WIDTH_OUT_0 _MK_ADDR_CONST(0xb030) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT _MK_SHIFT_CONST(10) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT _MK_SHIFT_CONST(20) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT) + + +// Register PDP_D_POOLING_KERNEL_CFG_0 +#define PDP_D_POOLING_KERNEL_CFG_0 _MK_ADDR_CONST(0xb034) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 _MK_ENUM_CONST(0x0) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 _MK_ENUM_CONST(0x1) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 _MK_ENUM_CONST(0x2) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 _MK_ENUM_CONST(0x3) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 _MK_ENUM_CONST(0x4) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 _MK_ENUM_CONST(0x5) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 _MK_ENUM_CONST(0x6) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 _MK_ENUM_CONST(0x7) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT _MK_SHIFT_CONST(8) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_FIELD _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_1 _MK_ENUM_CONST(0x0) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_2 _MK_ENUM_CONST(0x1) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_3 _MK_ENUM_CONST(0x2) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_4 _MK_ENUM_CONST(0x3) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_5 _MK_ENUM_CONST(0x4) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_6 _MK_ENUM_CONST(0x5) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_7 _MK_ENUM_CONST(0x6) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_8 _MK_ENUM_CONST(0x7) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT _MK_SHIFT_CONST(16) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT _MK_SHIFT_CONST(20) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_FIELD _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT) + + +// Register PDP_D_RECIP_KERNEL_WIDTH_0 +#define PDP_D_RECIP_KERNEL_WIDTH_0 _MK_ADDR_CONST(0xb038) +#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_FIELD _MK_FIELD_CONST(0x1ffff, PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT) + + +// Register PDP_D_RECIP_KERNEL_HEIGHT_0 +#define PDP_D_RECIP_KERNEL_HEIGHT_0 _MK_ADDR_CONST(0xb03c) +#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_FIELD _MK_FIELD_CONST(0x1ffff, PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT) + + +// Register PDP_D_POOLING_PADDING_CFG_0 +#define PDP_D_POOLING_PADDING_CFG_0 _MK_ADDR_CONST(0xb040) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_FIELD _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT _MK_SHIFT_CONST(4) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_FIELD _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT _MK_SHIFT_CONST(8) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_FIELD _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT _MK_SHIFT_CONST(12) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_FIELD _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_1_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0 _MK_ADDR_CONST(0xb044) +#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_2_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0 _MK_ADDR_CONST(0xb048) +#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_3_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0 _MK_ADDR_CONST(0xb04c) +#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_4_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0 _MK_ADDR_CONST(0xb050) +#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_5_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0 _MK_ADDR_CONST(0xb054) +#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_6_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0 _MK_ADDR_CONST(0xb058) +#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_7_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0 _MK_ADDR_CONST(0xb05c) +#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT) + + +// Register PDP_D_SRC_BASE_ADDR_LOW_0 +#define PDP_D_SRC_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xb060) +#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT) + + +// Register PDP_D_SRC_BASE_ADDR_HIGH_0 +#define PDP_D_SRC_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xb064) +#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT) + + +// Register PDP_D_SRC_LINE_STRIDE_0 +#define PDP_D_SRC_LINE_STRIDE_0 _MK_ADDR_CONST(0xb068) +#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT) + + +// Register PDP_D_SRC_SURFACE_STRIDE_0 +#define PDP_D_SRC_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xb06c) +#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT) + + +// Register PDP_D_DST_BASE_ADDR_LOW_0 +#define PDP_D_DST_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xb070) +#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT) + + +// Register PDP_D_DST_BASE_ADDR_HIGH_0 +#define PDP_D_DST_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xb074) +#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT) + + +// Register PDP_D_DST_LINE_STRIDE_0 +#define PDP_D_DST_LINE_STRIDE_0 _MK_ADDR_CONST(0xb078) +#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT) + + +// Register PDP_D_DST_SURFACE_STRIDE_0 +#define PDP_D_DST_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xb07c) +#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT) + + +// Register PDP_D_DST_RAM_CFG_0 +#define PDP_D_DST_RAM_CFG_0 _MK_ADDR_CONST(0xb080) +#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT) +#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register PDP_D_DATA_FORMAT_0 +#define PDP_D_DATA_FORMAT_0 _MK_ADDR_CONST(0xb084) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x3, PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT8 _MK_ENUM_CONST(0x0) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT16 _MK_ENUM_CONST(0x1) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FP16 _MK_ENUM_CONST(0x2) + + +// Register PDP_D_INF_INPUT_NUM_0 +#define PDP_D_INF_INPUT_NUM_0 _MK_ADDR_CONST(0xb088) +#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT) + + +// Register PDP_D_NAN_INPUT_NUM_0 +#define PDP_D_NAN_INPUT_NUM_0 _MK_ADDR_CONST(0xb08c) +#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT) + + +// Register PDP_D_NAN_OUTPUT_NUM_0 +#define PDP_D_NAN_OUTPUT_NUM_0 _MK_ADDR_CONST(0xb090) +#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT) + + +// Register PDP_D_PERF_ENABLE_0 +#define PDP_D_PERF_ENABLE_0 _MK_ADDR_CONST(0xb094) +#define PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT) +#define PDP_D_PERF_ENABLE_0_DMA_EN_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_D_PERF_ENABLE_0_DMA_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_D_PERF_WRITE_STALL_0 +#define PDP_D_PERF_WRITE_STALL_0 _MK_ADDR_CONST(0xb098) +#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT) + + +// Register PDP_D_CYA_0 +#define PDP_D_CYA_0 _MK_ADDR_CONST(0xb09c) +#define PDP_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CDP_RDMA_S_STATUS_0 +#define CDP_RDMA_S_STATUS_0 _MK_ADDR_CONST(0xc000) +#define CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT) +#define CDP_RDMA_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CDP_RDMA_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CDP_RDMA_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT) +#define CDP_RDMA_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CDP_RDMA_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CDP_RDMA_S_POINTER_0 +#define CDP_RDMA_S_POINTER_0 _MK_ADDR_CONST(0xc004) +#define CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT) +#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CDP_RDMA_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT) +#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_OP_ENABLE_0 +#define CDP_RDMA_D_OP_ENABLE_0 _MK_ADDR_CONST(0xc008) +#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_DATA_CUBE_WIDTH_0 +#define CDP_RDMA_D_DATA_CUBE_WIDTH_0 _MK_ADDR_CONST(0xc00c) +#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT) + + +// Register CDP_RDMA_D_DATA_CUBE_HEIGHT_0 +#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0 _MK_ADDR_CONST(0xc010) +#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT) + + +// Register CDP_RDMA_D_DATA_CUBE_CHANNEL_0 +#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0 _MK_ADDR_CONST(0xc014) +#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT) + + +// Register CDP_RDMA_D_SRC_BASE_ADDR_LOW_0 +#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xc018) +#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT) + + +// Register CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 +#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xc01c) +#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT) + + +// Register CDP_RDMA_D_SRC_LINE_STRIDE_0 +#define CDP_RDMA_D_SRC_LINE_STRIDE_0 _MK_ADDR_CONST(0xc020) +#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT) + + +// Register CDP_RDMA_D_SRC_SURFACE_STRIDE_0 +#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xc024) +#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT) + + +// Register CDP_RDMA_D_SRC_DMA_CFG_0 +#define CDP_RDMA_D_SRC_DMA_CFG_0 _MK_ADDR_CONST(0xc028) +#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT) +#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_SRC_COMPRESSION_EN_0 +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0 _MK_ADDR_CONST(0xc02c) +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT) +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_OPERATION_MODE_0 +#define CDP_RDMA_D_OPERATION_MODE_0 _MK_ADDR_CONST(0xc030) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_FIELD _MK_FIELD_CONST(0x3, CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_READPHILE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WRITEPHILE _MK_ENUM_CONST(0x1) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_ORDINARY _MK_ENUM_CONST(0x2) + + +// Register CDP_RDMA_D_DATA_FORMAT_0 +#define CDP_RDMA_D_DATA_FORMAT_0 _MK_ADDR_CONST(0xc034) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x3, CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8 _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16 _MK_ENUM_CONST(0x1) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16 _MK_ENUM_CONST(0x2) + + +// Register CDP_RDMA_D_PERF_ENABLE_0 +#define CDP_RDMA_D_PERF_ENABLE_0 _MK_ADDR_CONST(0xc038) +#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT) +#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_PERF_READ_STALL_0 +#define CDP_RDMA_D_PERF_READ_STALL_0 _MK_ADDR_CONST(0xc03c) +#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT) + + +// Register CDP_RDMA_D_CYA_0 +#define CDP_RDMA_D_CYA_0 _MK_ADDR_CONST(0xc040) +#define CDP_RDMA_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CDP_S_STATUS_0 +#define CDP_S_STATUS_0 _MK_ADDR_CONST(0xd000) +#define CDP_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_0_SHIFT) +#define CDP_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CDP_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CDP_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CDP_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_1_SHIFT) +#define CDP_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CDP_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CDP_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CDP_S_POINTER_0 +#define CDP_S_POINTER_0 _MK_ADDR_CONST(0xd004) +#define CDP_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CDP_S_POINTER_0_PRODUCER_SHIFT) +#define CDP_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDP_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CDP_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CDP_S_POINTER_0_CONSUMER_SHIFT) +#define CDP_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDP_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CDP_S_LUT_ACCESS_CFG_0 +#define CDP_S_LUT_ACCESS_CFG_0 _MK_ADDR_CONST(0xd008) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD _MK_FIELD_CONST(0x3ff, CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO _MK_ENUM_CONST(0x1) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(17) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE _MK_ENUM_CONST(0x1) + + +// Register CDP_S_LUT_ACCESS_DATA_0 +#define CDP_S_LUT_ACCESS_DATA_0 _MK_ADDR_CONST(0xd00c) +#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT) + + +// Register CDP_S_LUT_CFG_0 +#define CDP_S_LUT_CFG_0 _MK_ADDR_CONST(0xd010) +#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT) +#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR _MK_ENUM_CONST(0x1) +#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT _MK_SHIFT_CONST(4) +#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT) +#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO _MK_ENUM_CONST(0x1) +#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT _MK_SHIFT_CONST(5) +#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT) +#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO _MK_ENUM_CONST(0x1) +#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT _MK_SHIFT_CONST(6) +#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT) +#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO _MK_ENUM_CONST(0x1) + + +// Register CDP_S_LUT_INFO_0 +#define CDP_S_LUT_INFO_0 _MK_ADDR_CONST(0xd014) +#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT) +#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT) +#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT) + + +// Register CDP_S_LUT_LE_START_LOW_0 +#define CDP_S_LUT_LE_START_LOW_0 _MK_ADDR_CONST(0xd018) +#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT) + + +// Register CDP_S_LUT_LE_START_HIGH_0 +#define CDP_S_LUT_LE_START_HIGH_0 _MK_ADDR_CONST(0xd01c) +#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_FIELD _MK_FIELD_CONST(0x3f, CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT) + + +// Register CDP_S_LUT_LE_END_LOW_0 +#define CDP_S_LUT_LE_END_LOW_0 _MK_ADDR_CONST(0xd020) +#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT) + + +// Register CDP_S_LUT_LE_END_HIGH_0 +#define CDP_S_LUT_LE_END_HIGH_0 _MK_ADDR_CONST(0xd024) +#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_FIELD _MK_FIELD_CONST(0x3f, CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT) + + +// Register CDP_S_LUT_LO_START_LOW_0 +#define CDP_S_LUT_LO_START_LOW_0 _MK_ADDR_CONST(0xd028) +#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT) + + +// Register CDP_S_LUT_LO_START_HIGH_0 +#define CDP_S_LUT_LO_START_HIGH_0 _MK_ADDR_CONST(0xd02c) +#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_FIELD _MK_FIELD_CONST(0x3f, CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT) + + +// Register CDP_S_LUT_LO_END_LOW_0 +#define CDP_S_LUT_LO_END_LOW_0 _MK_ADDR_CONST(0xd030) +#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT) + + +// Register CDP_S_LUT_LO_END_HIGH_0 +#define CDP_S_LUT_LO_END_HIGH_0 _MK_ADDR_CONST(0xd034) +#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_FIELD _MK_FIELD_CONST(0x3f, CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT) + + +// Register CDP_S_LUT_LE_SLOPE_SCALE_0 +#define CDP_S_LUT_LE_SLOPE_SCALE_0 _MK_ADDR_CONST(0xd038) +#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT) +#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT) + + +// Register CDP_S_LUT_LE_SLOPE_SHIFT_0 +#define CDP_S_LUT_LE_SLOPE_SHIFT_0 _MK_ADDR_CONST(0xd03c) +#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT) +#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(5) +#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT) + + +// Register CDP_S_LUT_LO_SLOPE_SCALE_0 +#define CDP_S_LUT_LO_SLOPE_SCALE_0 _MK_ADDR_CONST(0xd040) +#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT) +#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT) + + +// Register CDP_S_LUT_LO_SLOPE_SHIFT_0 +#define CDP_S_LUT_LO_SLOPE_SHIFT_0 _MK_ADDR_CONST(0xd044) +#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT) +#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(5) +#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT) + + +// Register CDP_D_OP_ENABLE_0 +#define CDP_D_OP_ENABLE_0 _MK_ADDR_CONST(0xd048) +#define CDP_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CDP_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CDP_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_FUNC_BYPASS_0 +#define CDP_D_FUNC_BYPASS_0 _MK_ADDR_CONST(0xd04c) +#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_FIELD _MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT) +#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_ENABLE _MK_ENUM_CONST(0x1) +#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_FIELD _MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT) +#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_DST_BASE_ADDR_LOW_0 +#define CDP_D_DST_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xd050) +#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT) + + +// Register CDP_D_DST_BASE_ADDR_HIGH_0 +#define CDP_D_DST_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xd054) +#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT) + + +// Register CDP_D_DST_LINE_STRIDE_0 +#define CDP_D_DST_LINE_STRIDE_0 _MK_ADDR_CONST(0xd058) +#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT) + + +// Register CDP_D_DST_SURFACE_STRIDE_0 +#define CDP_D_DST_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xd05c) +#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT) + + +// Register CDP_D_DST_DMA_CFG_0 +#define CDP_D_DST_DMA_CFG_0 _MK_ADDR_CONST(0xd060) +#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT) +#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register CDP_D_DST_COMPRESSION_EN_0 +#define CDP_D_DST_COMPRESSION_EN_0 _MK_ADDR_CONST(0xd064) +#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_FIELD _MK_FIELD_CONST(0x1, CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT) +#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_DATA_FORMAT_0 +#define CDP_D_DATA_FORMAT_0 _MK_ADDR_CONST(0xd068) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FIELD _MK_FIELD_CONST(0x3, CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT8 _MK_ENUM_CONST(0x0) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT16 _MK_ENUM_CONST(0x1) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FP16 _MK_ENUM_CONST(0x2) + + +// Register CDP_D_NAN_FLUSH_TO_ZERO_0 +#define CDP_D_NAN_FLUSH_TO_ZERO_0 _MK_ADDR_CONST(0xd06c) +#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD _MK_FIELD_CONST(0x1, CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT) +#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_LRN_CFG_0 +#define CDP_D_LRN_CFG_0 _MK_ADDR_CONST(0xd070) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_FIELD _MK_FIELD_CONST(0x3, CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN3 _MK_ENUM_CONST(0x0) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN5 _MK_ENUM_CONST(0x1) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN7 _MK_ENUM_CONST(0x2) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9 _MK_ENUM_CONST(0x3) + + +// Register CDP_D_DATIN_OFFSET_0 +#define CDP_D_DATIN_OFFSET_0 _MK_ADDR_CONST(0xd074) +#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_FIELD _MK_FIELD_CONST(0xffff, CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT) + + +// Register CDP_D_DATIN_SCALE_0 +#define CDP_D_DATIN_SCALE_0 _MK_ADDR_CONST(0xd078) +#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT) + + +// Register CDP_D_DATIN_SHIFTER_0 +#define CDP_D_DATIN_SHIFTER_0 _MK_ADDR_CONST(0xd07c) +#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_FIELD _MK_FIELD_CONST(0x1f, CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT) + + +// Register CDP_D_DATOUT_OFFSET_0 +#define CDP_D_DATOUT_OFFSET_0 _MK_ADDR_CONST(0xd080) +#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT) + + +// Register CDP_D_DATOUT_SCALE_0 +#define CDP_D_DATOUT_SCALE_0 _MK_ADDR_CONST(0xd084) +#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT) + + +// Register CDP_D_DATOUT_SHIFTER_0 +#define CDP_D_DATOUT_SHIFTER_0 _MK_ADDR_CONST(0xd088) +#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_FIELD _MK_FIELD_CONST(0x3f, CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT) + + +// Register CDP_D_NAN_INPUT_NUM_0 +#define CDP_D_NAN_INPUT_NUM_0 _MK_ADDR_CONST(0xd08c) +#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT) + + +// Register CDP_D_INF_INPUT_NUM_0 +#define CDP_D_INF_INPUT_NUM_0 _MK_ADDR_CONST(0xd090) +#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT) + + +// Register CDP_D_NAN_OUTPUT_NUM_0 +#define CDP_D_NAN_OUTPUT_NUM_0 _MK_ADDR_CONST(0xd094) +#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT) + + +// Register CDP_D_OUT_SATURATION_0 +#define CDP_D_OUT_SATURATION_0 _MK_ADDR_CONST(0xd098) +#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT) + + +// Register CDP_D_PERF_ENABLE_0 +#define CDP_D_PERF_ENABLE_0 _MK_ADDR_CONST(0xd09c) +#define CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT) +#define CDP_D_PERF_ENABLE_0_DMA_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_PERF_ENABLE_0_DMA_EN_ENABLE _MK_ENUM_CONST(0x1) +#define CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT _MK_SHIFT_CONST(1) +#define CDP_D_PERF_ENABLE_0_LUT_EN_FIELD _MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT) +#define CDP_D_PERF_ENABLE_0_LUT_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_PERF_ENABLE_0_LUT_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_PERF_WRITE_STALL_0 +#define CDP_D_PERF_WRITE_STALL_0 _MK_ADDR_CONST(0xd0a0) +#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT) + + +// Register CDP_D_PERF_LUT_UFLOW_0 +#define CDP_D_PERF_LUT_UFLOW_0 _MK_ADDR_CONST(0xd0a4) +#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT) + + +// Register CDP_D_PERF_LUT_OFLOW_0 +#define CDP_D_PERF_LUT_OFLOW_0 _MK_ADDR_CONST(0xd0a8) +#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT) + + +// Register CDP_D_PERF_LUT_HYBRID_0 +#define CDP_D_PERF_LUT_HYBRID_0 _MK_ADDR_CONST(0xd0ac) +#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT) + + +// Register CDP_D_PERF_LUT_LE_HIT_0 +#define CDP_D_PERF_LUT_LE_HIT_0 _MK_ADDR_CONST(0xd0b0) +#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT) + + +// Register CDP_D_PERF_LUT_LO_HIT_0 +#define CDP_D_PERF_LUT_LO_HIT_0 _MK_ADDR_CONST(0xd0b4) +#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT) + + +// Register CDP_D_CYA_0 +#define CDP_D_CYA_0 _MK_ADDR_CONST(0xd0b8) +#define CDP_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register NVDLA_GEC_FEATURE_0 +#define NVDLA_GEC_FEATURE_0 _MK_ADDR_CONST(0xe000) +#define NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_FIELD _MK_FIELD_CONST(0x3f, NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_SHIFT) +#define NVDLA_GEC_FEATURE_0_NUM_ERR_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_FEATURE_0_NUM_ERR_FIELD _MK_FIELD_CONST(0xffff, NVDLA_GEC_FEATURE_0_NUM_ERR_SHIFT) + + +// Register NVDLA_GEC_SWRESET_0 +#define NVDLA_GEC_SWRESET_0 _MK_ADDR_CONST(0xe004) +#define NVDLA_GEC_SWRESET_0_SWRST_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_SWRESET_0_SWRST_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_SWRESET_0_SWRST_SHIFT) + + +// Register NVDLA_GEC_MISSIONERR_TYPE_0 +#define NVDLA_GEC_MISSIONERR_TYPE_0 _MK_ADDR_CONST(0xe008) +#define NVDLA_GEC_MISSIONERR_TYPE_0_CODE_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_MISSIONERR_TYPE_0_CODE_FIELD _MK_FIELD_CONST(0x3f, NVDLA_GEC_MISSIONERR_TYPE_0_CODE_SHIFT) + + +// Register NVDLA_GEC_CURRENT_COUNTER_VALUE_0 +#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0 _MK_ADDR_CONST(0xe00c) +#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_FIELD _MK_FIELD_CONST(0x1ff, NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT) + + +// Register NVDLA_GEC_MISSIONERR_INDEX_0 +#define NVDLA_GEC_MISSIONERR_INDEX_0 _MK_ADDR_CONST(0xe014) +#define NVDLA_GEC_MISSIONERR_INDEX_0_IDX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_MISSIONERR_INDEX_0_IDX_FIELD _MK_FIELD_CONST(0x7f, NVDLA_GEC_MISSIONERR_INDEX_0_IDX_SHIFT) + + +// Register NVDLA_GEC_CORRECTABLE_THRESHOLD_0 +#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0 _MK_ADDR_CONST(0xe018) +#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT) + + +// Register NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0 +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0 _MK_ADDR_CONST(0xe01c) +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD _MK_FIELD_CONST(0xff, NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT) +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK _MK_ENUM_CONST(0xe1) + + +// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0 _MK_ADDR_CONST(0xe030) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0 _MK_ADDR_CONST(0xe034) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0 _MK_ADDR_CONST(0xe038) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0 +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0 _MK_ADDR_CONST(0xe03c) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0 _MK_ADDR_CONST(0xe040) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0 _MK_ADDR_CONST(0xe044) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0 _MK_ADDR_CONST(0xe048) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0 +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0 _MK_ADDR_CONST(0xe050) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_RELOAD _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0 _MK_ADDR_CONST(0xe060) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0 _MK_ADDR_CONST(0xe064) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0 _MK_ADDR_CONST(0xe068) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0 _MK_ADDR_CONST(0xe06c) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0 _MK_ADDR_CONST(0xe070) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0 _MK_ADDR_CONST(0xe074) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0 _MK_ADDR_CONST(0xe078) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0 +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0 _MK_ADDR_CONST(0xe080) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_RELOAD _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0 _MK_ADDR_CONST(0xe084) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0 _MK_ADDR_CONST(0xe090) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0 _MK_ADDR_CONST(0xe094) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0 _MK_ADDR_CONST(0xe098) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0 +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0 _MK_ADDR_CONST(0xe09c) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0 _MK_ADDR_CONST(0xe0a0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0 _MK_ADDR_CONST(0xe0a4) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0 _MK_ADDR_CONST(0xe0a8) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0 +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0 _MK_ADDR_CONST(0xe0b0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_RELOAD _MK_ENUM_CONST(0x1) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register NVDLA_CVIF_CFG_RD_WEIGHT_0_0 +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0 _MK_ADDR_CONST(0xf000) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT) + + +// Register NVDLA_CVIF_CFG_RD_WEIGHT_1_0 +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0 _MK_ADDR_CONST(0xf004) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT) + + +// Register NVDLA_CVIF_CFG_RD_WEIGHT_2_0 +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0 _MK_ADDR_CONST(0xf008) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT) + + +// Register NVDLA_CVIF_CFG_WR_WEIGHT_0_0 +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0 _MK_ADDR_CONST(0xf00c) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT) + + +// Register NVDLA_CVIF_CFG_WR_WEIGHT_1_0 +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0 _MK_ADDR_CONST(0xf010) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT) + + +// Register NVDLA_CVIF_CFG_OUTSTANDING_CNT_0 +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0 _MK_ADDR_CONST(0xf014) +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT) +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT) + + +// Register NVDLA_CVIF_STATUS_0 +#define NVDLA_CVIF_STATUS_0 _MK_ADDR_CONST(0xf018) +#define NVDLA_CVIF_STATUS_0_IDLE_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_STATUS_0_IDLE_FIELD _MK_FIELD_CONST(0x1, NVDLA_CVIF_STATUS_0_IDLE_SHIFT) +#define NVDLA_CVIF_STATUS_0_IDLE_NO _MK_ENUM_CONST(0x0) +#define NVDLA_CVIF_STATUS_0_IDLE_YES _MK_ENUM_CONST(0x1) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register BDMA_CFG_SRC_ADDR_LOW_0 +#define BDMA_CFG_SRC_ADDR_LOW_0 _MK_ADDR_CONST(0x10000) +#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_SRC_ADDR_LOW_0_V32_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT) + + +// Register BDMA_CFG_SRC_ADDR_HIGH_0 +#define BDMA_CFG_SRC_ADDR_HIGH_0 _MK_ADDR_CONST(0x10004) +#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT) + + +// Register BDMA_CFG_DST_ADDR_LOW_0 +#define BDMA_CFG_DST_ADDR_LOW_0 _MK_ADDR_CONST(0x10008) +#define BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_DST_ADDR_LOW_0_V32_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT) + + +// Register BDMA_CFG_DST_ADDR_HIGH_0 +#define BDMA_CFG_DST_ADDR_HIGH_0 _MK_ADDR_CONST(0x1000c) +#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_DST_ADDR_HIGH_0_V8_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT) + + +// Register BDMA_CFG_LINE_0 +#define BDMA_CFG_LINE_0 _MK_ADDR_CONST(0x10010) +#define BDMA_CFG_LINE_0_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_LINE_0_SIZE_FIELD _MK_FIELD_CONST(0x1fff, BDMA_CFG_LINE_0_SIZE_SHIFT) + + +// Register BDMA_CFG_CMD_0 +#define BDMA_CFG_CMD_0 _MK_ADDR_CONST(0x10014) +#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT) +#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_CVSRAM _MK_ENUM_CONST(0x0) +#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_MC _MK_ENUM_CONST(0x1) +#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT _MK_SHIFT_CONST(1) +#define BDMA_CFG_CMD_0_DST_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT) +#define BDMA_CFG_CMD_0_DST_RAM_TYPE_CVSRAM _MK_ENUM_CONST(0x0) +#define BDMA_CFG_CMD_0_DST_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register BDMA_CFG_LINE_REPEAT_0 +#define BDMA_CFG_LINE_REPEAT_0 _MK_ADDR_CONST(0x10018) +#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_LINE_REPEAT_0_NUMBER_FIELD _MK_FIELD_CONST(0xffffff, BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT) + + +// Register BDMA_CFG_SRC_LINE_0 +#define BDMA_CFG_SRC_LINE_0 _MK_ADDR_CONST(0x1001c) +#define BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_SRC_LINE_0_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT) + + +// Register BDMA_CFG_DST_LINE_0 +#define BDMA_CFG_DST_LINE_0 _MK_ADDR_CONST(0x10020) +#define BDMA_CFG_DST_LINE_0_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_DST_LINE_0_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_LINE_0_STRIDE_SHIFT) + + +// Register BDMA_CFG_SURF_REPEAT_0 +#define BDMA_CFG_SURF_REPEAT_0 _MK_ADDR_CONST(0x10024) +#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_SURF_REPEAT_0_NUMBER_FIELD _MK_FIELD_CONST(0xffffff, BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT) + + +// Register BDMA_CFG_SRC_SURF_0 +#define BDMA_CFG_SRC_SURF_0 _MK_ADDR_CONST(0x10028) +#define BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_SRC_SURF_0_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT) + + +// Register BDMA_CFG_DST_SURF_0 +#define BDMA_CFG_DST_SURF_0 _MK_ADDR_CONST(0x1002c) +#define BDMA_CFG_DST_SURF_0_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_DST_SURF_0_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_SURF_0_STRIDE_SHIFT) + + +// Register BDMA_CFG_OP_0 +#define BDMA_CFG_OP_0 _MK_ADDR_CONST(0x10030) +#define BDMA_CFG_OP_0_EN_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_OP_0_EN_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_OP_0_EN_SHIFT) +#define BDMA_CFG_OP_0_EN_DISABLE _MK_ENUM_CONST(0x0) +#define BDMA_CFG_OP_0_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register BDMA_CFG_LAUNCH0_0 +#define BDMA_CFG_LAUNCH0_0 _MK_ADDR_CONST(0x10034) +#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT) +#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_NO _MK_ENUM_CONST(0x0) +#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_YES _MK_ENUM_CONST(0x1) + + +// Register BDMA_CFG_LAUNCH1_0 +#define BDMA_CFG_LAUNCH1_0 _MK_ADDR_CONST(0x10038) +#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT) +#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_NO _MK_ENUM_CONST(0x0) +#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_YES _MK_ENUM_CONST(0x1) + + +// Register BDMA_CFG_STATUS_0 +#define BDMA_CFG_STATUS_0 _MK_ADDR_CONST(0x1003c) +#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT) +#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_NO _MK_ENUM_CONST(0x0) +#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_YES _MK_ENUM_CONST(0x1) + + +// Register BDMA_STATUS_0 +#define BDMA_STATUS_0 _MK_ADDR_CONST(0x10040) +#define BDMA_STATUS_0_FREE_SLOT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_0_FREE_SLOT_FIELD _MK_FIELD_CONST(0xff, BDMA_STATUS_0_FREE_SLOT_SHIFT) +#define BDMA_STATUS_0_IDLE_SHIFT _MK_SHIFT_CONST(8) +#define BDMA_STATUS_0_IDLE_FIELD _MK_FIELD_CONST(0x1, BDMA_STATUS_0_IDLE_SHIFT) +#define BDMA_STATUS_0_IDLE_NO _MK_ENUM_CONST(0x0) +#define BDMA_STATUS_0_IDLE_YES _MK_ENUM_CONST(0x1) +#define BDMA_STATUS_0_GRP0_BUSY_SHIFT _MK_SHIFT_CONST(9) +#define BDMA_STATUS_0_GRP0_BUSY_FIELD _MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP0_BUSY_SHIFT) +#define BDMA_STATUS_0_GRP0_BUSY_NO _MK_ENUM_CONST(0x0) +#define BDMA_STATUS_0_GRP0_BUSY_YES _MK_ENUM_CONST(0x1) +#define BDMA_STATUS_0_GRP1_BUSY_SHIFT _MK_SHIFT_CONST(10) +#define BDMA_STATUS_0_GRP1_BUSY_FIELD _MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP1_BUSY_SHIFT) +#define BDMA_STATUS_0_GRP1_BUSY_NO _MK_ENUM_CONST(0x0) +#define BDMA_STATUS_0_GRP1_BUSY_YES _MK_ENUM_CONST(0x1) + + +// Register BDMA_STATUS_GRP0_READ_STALL_0 +#define BDMA_STATUS_GRP0_READ_STALL_0 _MK_ADDR_CONST(0x10044) +#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT) + + +// Register BDMA_STATUS_GRP0_WRITE_STALL_0 +#define BDMA_STATUS_GRP0_WRITE_STALL_0 _MK_ADDR_CONST(0x10048) +#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT) + + +// Register BDMA_STATUS_GRP1_READ_STALL_0 +#define BDMA_STATUS_GRP1_READ_STALL_0 _MK_ADDR_CONST(0x1004c) +#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT) + + +// Register BDMA_STATUS_GRP1_WRITE_STALL_0 +#define BDMA_STATUS_GRP1_WRITE_STALL_0 _MK_ADDR_CONST(0x10050) +#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register RBK_S_STATUS_0 +#define RBK_S_STATUS_0 _MK_ADDR_CONST(0x11000) +#define RBK_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define RBK_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_0_SHIFT) +#define RBK_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define RBK_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define RBK_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define RBK_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define RBK_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_1_SHIFT) +#define RBK_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define RBK_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define RBK_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register RBK_S_POINTER_0 +#define RBK_S_POINTER_0 _MK_ADDR_CONST(0x11004) +#define RBK_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define RBK_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, RBK_S_POINTER_0_PRODUCER_SHIFT) +#define RBK_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define RBK_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define RBK_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define RBK_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, RBK_S_POINTER_0_CONSUMER_SHIFT) +#define RBK_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define RBK_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register RBK_D_OP_ENABLE_0 +#define RBK_D_OP_ENABLE_0 _MK_ADDR_CONST(0x11008) +#define RBK_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, RBK_D_OP_ENABLE_0_OP_EN_SHIFT) +#define RBK_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define RBK_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register RBK_D_MISC_CFG_0 +#define RBK_D_MISC_CFG_0 _MK_ADDR_CONST(0x1100c) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_FIELD _MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_CONTRACT _MK_ENUM_CONST(0x0) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_SPLIT _MK_ENUM_CONST(0x1) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE _MK_ENUM_CONST(0x2) +#define RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT _MK_SHIFT_CONST(8) +#define RBK_D_MISC_CFG_0_IN_PRECISION_FIELD _MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT) +#define RBK_D_MISC_CFG_0_IN_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define RBK_D_MISC_CFG_0_IN_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define RBK_D_MISC_CFG_0_IN_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + +// Register RBK_D_DAIN_RAM_TYPE_0 +#define RBK_D_DAIN_RAM_TYPE_0 _MK_ADDR_CONST(0x11010) +#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT) +#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF _MK_ENUM_CONST(0x0) +#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF _MK_ENUM_CONST(0x1) + + +// Register RBK_D_DATAIN_SIZE_0_0 +#define RBK_D_DATAIN_SIZE_0_0 _MK_ADDR_CONST(0x11014) +#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT) +#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT _MK_SHIFT_CONST(16) +#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT) + + +// Register RBK_D_DATAIN_SIZE_1_0 +#define RBK_D_DATAIN_SIZE_1_0 _MK_ADDR_CONST(0x11018) +#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT) + + +// Register RBK_D_DAIN_ADDR_HIGH_0 +#define RBK_D_DAIN_ADDR_HIGH_0 _MK_ADDR_CONST(0x1101c) +#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT) + + +// Register RBK_D_DAIN_ADDR_LOW_0 +#define RBK_D_DAIN_ADDR_LOW_0 _MK_ADDR_CONST(0x11020) +#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT) + + +// Register RBK_D_DAIN_LINE_STRIDE_0 +#define RBK_D_DAIN_LINE_STRIDE_0 _MK_ADDR_CONST(0x11024) +#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT) + + +// Register RBK_D_DAIN_SURF_STRIDE_0 +#define RBK_D_DAIN_SURF_STRIDE_0 _MK_ADDR_CONST(0x11028) +#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT) + + +// Register RBK_D_DAIN_PLANAR_STRIDE_0 +#define RBK_D_DAIN_PLANAR_STRIDE_0 _MK_ADDR_CONST(0x1102c) +#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT) + + +// Register RBK_D_DAOUT_RAM_TYPE_0 +#define RBK_D_DAOUT_RAM_TYPE_0 _MK_ADDR_CONST(0x11030) +#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT) +#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_CVIF _MK_ENUM_CONST(0x0) +#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_MCIF _MK_ENUM_CONST(0x1) + + +// Register RBK_D_DATAOUT_SIZE_1_0 +#define RBK_D_DATAOUT_SIZE_1_0 _MK_ADDR_CONST(0x11034) +#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT) + + +// Register RBK_D_DAOUT_ADDR_HIGH_0 +#define RBK_D_DAOUT_ADDR_HIGH_0 _MK_ADDR_CONST(0x11038) +#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT) + + +// Register RBK_D_DAOUT_ADDR_LOW_0 +#define RBK_D_DAOUT_ADDR_LOW_0 _MK_ADDR_CONST(0x1103c) +#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT) + + +// Register RBK_D_DAOUT_LINE_STRIDE_0 +#define RBK_D_DAOUT_LINE_STRIDE_0 _MK_ADDR_CONST(0x11040) +#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT) + + +// Register RBK_D_CONTRACT_STRIDE_0_0 +#define RBK_D_CONTRACT_STRIDE_0_0 _MK_ADDR_CONST(0x11044) +#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT) + + +// Register RBK_D_CONTRACT_STRIDE_1_0 +#define RBK_D_CONTRACT_STRIDE_1_0 _MK_ADDR_CONST(0x11048) +#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT) + + +// Register RBK_D_DAOUT_SURF_STRIDE_0 +#define RBK_D_DAOUT_SURF_STRIDE_0 _MK_ADDR_CONST(0x1104c) +#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT) + + +// Register RBK_D_DAOUT_PLANAR_STRIDE_0 +#define RBK_D_DAOUT_PLANAR_STRIDE_0 _MK_ADDR_CONST(0x11050) +#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT) + + +// Register RBK_D_DECONV_STRIDE_0 +#define RBK_D_DECONV_STRIDE_0 _MK_ADDR_CONST(0x11054) +#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_FIELD _MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT) +#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT _MK_SHIFT_CONST(16) +#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_FIELD _MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT) + + +// Register RBK_D_PERF_ENABLE_0 +#define RBK_D_PERF_ENABLE_0 _MK_ADDR_CONST(0x11058) +#define RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_PERF_ENABLE_0_PERF_EN_FIELD _MK_FIELD_CONST(0x1, RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT) + + +// Register RBK_D_PERF_READ_STALL_0 +#define RBK_D_PERF_READ_STALL_0 _MK_ADDR_CONST(0x1105c) +#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_FIELD _MK_FIELD_CONST(0xffffffff, RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT) + + +// Register RBK_D_PERF_WRITE_STALL_0 +#define RBK_D_PERF_WRITE_STALL_0 _MK_ADDR_CONST(0x11060) +#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_FIELD _MK_FIELD_CONST(0xffffffff, RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_NVDLA_CFGROM 0x0 +#define BASE_ADDRESS_NVDLA_GLB 0x1000 +#define BASE_ADDRESS_NVDLA_MCIF 0x2000 +#define BASE_ADDRESS_NVDLA_CDMA 0x3000 +#define BASE_ADDRESS_NVDLA_CSC 0x4000 +#define BASE_ADDRESS_NVDLA_CMAC_A 0x5000 +#define BASE_ADDRESS_NVDLA_CMAC_B 0x6000 +#define BASE_ADDRESS_NVDLA_CACC 0x7000 +#define BASE_ADDRESS_NVDLA_SDP_RDMA 0x8000 +#define BASE_ADDRESS_NVDLA_SDP 0x9000 +#define BASE_ADDRESS_NVDLA_PDP_RDMA 0xa000 +#define BASE_ADDRESS_NVDLA_PDP 0xb000 +#define BASE_ADDRESS_NVDLA_CDP_RDMA 0xc000 +#define BASE_ADDRESS_NVDLA_CDP 0xd000 +#define BASE_ADDRESS_NVDLA_GEC 0xe000 +#define BASE_ADDRESS_NVDLA_CVIF 0xf000 +#define BASE_ADDRESS_NVDLA_BDMA 0x10000 +#define BASE_ADDRESS_NVDLA_RBK 0x11000 + +#endif From 33e83e06448517ed80b72ace90b993d871f0b86c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 13:08:57 -0700 Subject: [PATCH 086/153] [dromajo] separate documentation | move header file gen to tcip --- docs/Advanced-Concepts/Debugging-BOOM.rst | 30 +++++++++++++++++++ docs/Advanced-Concepts/Debugging-RTL.rst | 23 -------------- docs/Advanced-Concepts/index.rst | 1 + docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/Subsystem.scala | 27 +++-------------- generators/testchipip | 2 +- 7 files changed, 38 insertions(+), 49 deletions(-) create mode 100644 docs/Advanced-Concepts/Debugging-BOOM.rst diff --git a/docs/Advanced-Concepts/Debugging-BOOM.rst b/docs/Advanced-Concepts/Debugging-BOOM.rst new file mode 100644 index 0000000000..1e61804c58 --- /dev/null +++ b/docs/Advanced-Concepts/Debugging-BOOM.rst @@ -0,0 +1,30 @@ +Debugging BOOM +====================== + +In addition to the default debugging techniques specified in :ref:`Debugging RTL`, +single-core BOOM designs can utilize the Dromajo co-simulator (see :ref:`Dromajo`) +to verify functionality. + +.. warning:: Dromajo currently only works in single-core BOOM systems without accelerators. + +.. warning:: Dromajo currently only works in VCS simulation and FireSim. + +Setting up Dromajo Co-simulation +-------------------------------------- + +Dromajo co-simulation is setup to work when two config fragments are added to a BOOM config. +First, a ``chipyard.config.WithTraceIO`` config fragment must be added so that BOOM's traceport is enabled. +Second, a ``chipyard.iobinders.WithSimDromajoBridge`` config fragment must be added to +connect the Dromajo co-simulator to the traceport. +Once both config fragments are added Dromajo should be enabled. + +To build/run Dromajo with a BOOM design, run your configuration the following make commands: + +.. code-block:: shell + + # build the default Dromajo BOOM config without waveform dumps + # replace "DromajoBoomConfig" with your particular config + make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 + + # run a simulation with Dromajo + make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY= run-binary diff --git a/docs/Advanced-Concepts/Debugging-RTL.rst b/docs/Advanced-Concepts/Debugging-RTL.rst index 86e5ced30f..6831cc4acd 100644 --- a/docs/Advanced-Concepts/Debugging-RTL.rst +++ b/docs/Advanced-Concepts/Debugging-RTL.rst @@ -86,29 +86,6 @@ identical program behavior. The torture utility can also be configured to run continuously for stress-testing. The torture utility exists within the ``utilities`` directory. -Dromajo Co-simulation for BOOM designs --------------------------------------- -Dromajo co-simulation is setup to work when two config. fragments are added to a BOOM config. -First, a ``chipyard.config.WithTraceIO`` config. fragment must be added so that BOOM's traceport is enabled. -Second, a ``chipyard.iobinders.WithSimDromajoBridge`` config. fragment must be added to -connect the Dromajo co-simulator to the traceport. -Once both config. fragments are added Dromajo should be enabled. - -To build/run Dromajo with a BOOM design, run your configuration the following make commands: - -.. code-block:: shell - - # build the default Dromajo BOOM config. without waveform dumps - # replace "DromajoBoomConfig" with your particular config - make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 - - # run a simulation with Dromajo - make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY= run-binary - -.. warning:: Dromajo currently only works in single-core BOOM systems without accelerators. - -.. warning:: Dromajo currently only works in VCS simulation and FireSim. - Firesim Debugging --------------------------- Chisel printfs, asserts, Dromajo co-simulation, and waveform generation are also available in FireSim diff --git a/docs/Advanced-Concepts/index.rst b/docs/Advanced-Concepts/index.rst index c13e569b0c..12b1271629 100644 --- a/docs/Advanced-Concepts/index.rst +++ b/docs/Advanced-Concepts/index.rst @@ -11,6 +11,7 @@ They expect you to know about Chisel, Parameters, configs, etc. Top-Testharness Chip-Communication Debugging-RTL + Debugging-BOOM Resources CDEs diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 7a89e93a80..c24f81ed8a 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -80,7 +80,7 @@ Tools A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). **Dromajo** - A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technology. + A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technologies. See :ref:`Dromajo` for more information. Toolchains diff --git a/generators/boom b/generators/boom index 8c4ac6fd40..2668248c5c 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 8c4ac6fd40b455387cec369080b9b47d6fd1466e +Subproject commit 2668248c5c673037f5cb7a8bc2a90c5fb0c019d9 diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 4dfa7d7382..99c31472e0 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -24,6 +24,8 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} +import testchipip.{DromajoHelper} + trait HasChipyardTiles extends HasTiles with CanHavePeripheryPLIC with CanHavePeripheryCLINT @@ -106,27 +108,6 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) // Generate C header with relevant information for Dromajo - // THIS IS INCLUDED IN THE `dromajo_params.h` header file - var dromajoParams: String = "" - dromajoParams += "#ifndef DROMAJO_PARAMS_H" - dromajoParams += "\n#define DROMAJO_PARAMS_H" - dromajoParams += "\n\n" + "#define DROMAJO_RESET_VECTOR " + "\"" + "0x" + f"${p(BootROMParams).hang}%X" + "\"" - dromajoParams += "\n" + "#define DROMAJO_MMIO_START " + "\"" + "0x" + f"${p(BootROMParams).address + p(BootROMParams).size}%X" + "\"" - p(ExtMem) map { eP => - dromajoParams += "\n" + "#define DROMAJO_MMIO_END " + "\"" + "0x" + f"${eP.master.base}%X" + "\"" - // dromajo memory is in MiB chunks - dromajoParams += "\n" + "#define DROMAJO_MEM_SIZE " + "\"" + "0x" + f"${eP.master.size >> 20}%X" + "\"" - } - p(PLICKey) map { pP => - dromajoParams += "\n" + "#define DROMAJO_PLIC_BASE " + "\"" + "0x" + f"${pP.baseAddress}%X" + "\"" - dromajoParams += "\n" + "#define DROMAJO_PLIC_SIZE " + "\"" + "0x" + f"${PLICConsts.size(pP.maxHarts)}%X" + "\"" - } - p(CLINTKey) map { cP => - dromajoParams += "\n" + "#define DROMAJO_CLINT_BASE " + "\"" + "0x" + f"${cP.baseAddress}%X" + "\"" - dromajoParams += "\n" + "#define DROMAJO_CLINT_SIZE " + "\"" + "0x" + f"${CLINTConsts.size}%X" + "\"" - } - dromajoParams += "\n\n#endif" - - ElaborationArtefacts.add("""dromajo_params.h""", dromajoParams) - + // This is included in the `dromajo_params.h` header file + DromajoHelper.addArtefacts } diff --git a/generators/testchipip b/generators/testchipip index e43e818f44..8ce64295f2 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e43e818f443764cb1a1bdaa243b5adc795083217 +Subproject commit 8ce64295f2c1f6b927145527538988809a03a057 From ca3c557fe29c45dc9be9589bae8bd84f4c853378 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 13:43:14 -0700 Subject: [PATCH 087/153] [dromajo] change dromajo url | small cleanup --- .gitmodules | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index cae791ddc2..aab9a8f784 100644 --- a/.gitmodules +++ b/.gitmodules @@ -127,4 +127,4 @@ url = https://github.com/ucb-bar/nvdla-workload.git [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src - url = https://github.com/abejgonzalez/dromajo.git + url = https://github.com/riscv-boom/dromajo.git diff --git a/generators/testchipip b/generators/testchipip index 8ce64295f2..342d1d7098 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8ce64295f2c1f6b927145527538988809a03a057 +Subproject commit 342d1d70985797381985ea0a47e668961ceb0c3d From 9dda27f20cc1afbcb4b0d3f088e95963e923bced Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 14:47:15 -0700 Subject: [PATCH 088/153] [traceio] wdata: use option instead of 1.B wire --- generators/boom | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 2668248c5c..f0caca8d6b 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 2668248c5c673037f5cb7a8bc2a90c5fb0c019d9 +Subproject commit f0caca8d6bc98f3ccc7d8b9391b7f7c8efb2f879 diff --git a/generators/testchipip b/generators/testchipip index 342d1d7098..72cafd8c86 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 342d1d70985797381985ea0a47e668961ceb0c3d +Subproject commit 72cafd8c867f3a1a6decac62e6e77b9b6de02be7 From d88627e913a97ee10c3cded3f33bdef9f6d54c3a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 14:51:27 -0700 Subject: [PATCH 089/153] [traceio] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4e94c1a013..724a66b0f4 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4e94c1a0131dc673f894c62f9a110637844a806a +Subproject commit 724a66b0f4430b02d7d5e83b419916250978ee01 From 73f8ec5017c2f19e76a8c03aea364a77de826274 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 16 May 2020 22:46:39 +0000 Subject: [PATCH 090/153] [stage] Make config concatenation actually work --- .../src/main/scala/stage/ChipyardAnnotations.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala index dfee15961c..d75c11a1a7 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -11,7 +11,12 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio override val options = Seq( new ShellOption[String]( longOption = "legacy-configs", - toAnnotationSeq = a => Seq(new ConfigsAnnotation(a.split("_"))), + toAnnotationSeq = a => { + val split = a.split('.') + val packageName = split.init.mkString(".") + val configs = split.last.split("_") + Seq(new ConfigsAnnotation(configs map { config => s"${packageName}.${config}" } )) + }, helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).", shortOption = Some("LC") ) From 8d5927913f0411ada620fe6084fa7f9060c6aa52 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 16 May 2020 22:48:42 +0000 Subject: [PATCH 091/153] [stage] Support using Chipyard's stage for non-processor designs --- .../src/main/scala/stage/phases/AddDefaultTests.scala | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index fce5d43294..27ff2b25e4 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -16,6 +16,7 @@ import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} import freechips.rocketchip.util.HasRocketChipStageUtils +import freechips.rocketchip.tile.XLen import chipyard.TestSuiteHelper @@ -30,9 +31,13 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { val annotations = mutable.ArrayBuffer[Annotation]() val suiteHelper = new TestSuiteHelper - suiteHelper.addRocketTestSuites - suiteHelper.addBoomTestSuites - suiteHelper.addArianeTestSuites + // Use Xlen as a proxy for detecting if we are a processor-like target + // The underlying test suites expect this field to be defined + if (p.lift(XLen).nonEmpty) { + suiteHelper.addRocketTestSuites + suiteHelper.addBoomTestSuites + suiteHelper.addArianeTestSuites + } // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From e913ddbbbe407272b60527f683322ff996200b2e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 16:45:50 -0700 Subject: [PATCH 092/153] [traceio] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 72cafd8c86..cf536b685d 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 72cafd8c867f3a1a6decac62e6e77b9b6de02be7 +Subproject commit cf536b685dba3063b623ccffeaf68517e234966b From 99846c1ccbf48709d266680b94c8cdc3d1832398 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 17 May 2020 00:18:17 +0000 Subject: [PATCH 093/153] [firechip] Use the standard Chipyard generator --- .../firechip/src/main/scala/Generator.scala | 73 ------------------- .../src/test/scala/ScalaTestSuite.scala | 39 +++------- sims/firesim | 2 +- 3 files changed, 13 insertions(+), 101 deletions(-) delete mode 100644 generators/firechip/src/main/scala/Generator.scala diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala deleted file mode 100644 index 01747bb320..0000000000 --- a/generators/firechip/src/main/scala/Generator.scala +++ /dev/null @@ -1,73 +0,0 @@ -//See LICENSE for license details. - -package firesim.firesim - -import java.io.{File, FileWriter} - -import chisel3.RawModule -import chisel3.internal.firrtl.{Circuit, Port} - -import freechips.rocketchip.diplomacy.{ValName, AutoBundle} -import freechips.rocketchip.devices.debug.DebugIO -import freechips.rocketchip.util.{ElaborationArtefacts} -import freechips.rocketchip.system.DefaultTestSuites._ -import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.subsystem.RocketTilesKey -import freechips.rocketchip.tile.XLen - -import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities} - -import scala.util.Try - -import chipyard.TestSuiteHelper - -trait HasTestSuites { - def addTestSuites(targetName: String, params: Parameters) { - val suiteHelper = new TestSuiteHelper - suiteHelper.addRocketTestSuites(params) - suiteHelper.addBoomTestSuites(params) - suiteHelper.addArianeTestSuites(params) - TestGeneration.addSuites(suiteHelper.suites.values.toSeq) - TestGeneration.addSuite(FastBlockdevTests) - TestGeneration.addSuite(SlowBlockdevTests) - if (!targetName.contains("NoNIC")) - TestGeneration.addSuite(NICLoopbackTests) - - import hwacha.HwachaTestSuites._ - if (Try(params(hwacha.HwachaNLanes)).getOrElse(0) > 0) { - TestGeneration.addSuites(rv64uv.map(_("p"))) - TestGeneration.addSuites(rv64uv.map(_("vp"))) - TestGeneration.addSuite(rv64sv("p")) - TestGeneration.addSuite(hwachaBmarks) - } - } -} - -// Mixed into an App or into a TestSuite -trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites { - /** Output software test Makefrags, which provide targets for integration testing. */ - def generateTestSuiteMakefrags { - addTestSuites(names.topModuleClass, targetParams) - writeOutputFile(s"$longName.d", TestGeneration.generateMakeFrag) // Subsystem-specific test suites - } - - // Output miscellaneous files produced as a side-effect of elaboration - def generateArtefacts { - // generate RC's artefacts - ElaborationArtefacts.files.foreach { case (extension, contents) => - writeOutputFile(s"${longName}.${extension}", contents ()) - } - } -} - -object FireSimGenerator extends App with IsFireSimGeneratorLike { - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - lazy val generatorArgs = GeneratorArgs(args) - lazy val genDir = new File(names.targetDir) - // The only reason this is not generateFirrtl; generateAnno is that we need to use a different - // JsonProtocol to properly write out the annotations. Fix once the generated are unified - elaborate - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 3ab4162ce8..1e83271c6f 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -12,38 +12,27 @@ import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite} import freechips.rocketchip.system.TestGeneration._ import freechips.rocketchip.system.DefaultTestSuites._ -import firesim.util.GeneratorArgs - abstract class FireSimTestSuite( topModuleClass: String, targetConfigs: String, platformConfigs: String, N: Int = 8 - ) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { + ) extends firesim.TestSuiteCommon { import scala.concurrent.duration._ import ExecutionContext.Implicits.global - val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - - lazy val generatorArgs = GeneratorArgs( - midasFlowKind = "midas", - targetDir = "generated-src", - topModuleProject = "firesim.firesim", - topModuleClass = topModuleClass, - targetConfigProject = "firesim.firesim", - targetConfigs = targetConfigs ++ "_WithScalaTestFeatures", - platformConfigProject = "firesim.firesim", - platformConfigs = platformConfigs) + val topModuleProject = "firesim.firesim" - // From HasFireSimGeneratorUtilities - // For the firesim utilities to use the same directory as the test suite - override lazy val testDir = genDir + val chipyardLongName = topModuleProject + "." + topModuleClass + "." + targetConfigs // From TestSuiteCommon - val targetTuple = generatorArgs.tupleName - val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", - s"TARGET_CONFIG=${generatorArgs.targetConfigs}", - s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") + val targetTuple = s"$topModuleClass-$targetConfigs-$platformConfigs" + val commonMakeArgs = Seq(s"DESIGN=${topModuleClass}", + s"TARGET_CONFIG=${targetConfigs}", + s"PLATFORM_CONFIG=${platformConfigs}") + + override lazy val genDir = new File(firesimDir, s"generated-src/${chipyardLongName}") + def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"), @@ -127,20 +116,16 @@ abstract class FireSimTestSuite( } clean - mkdirs - elaborate - generateTestSuiteMakefrags - generateArtefacts runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) - runSuite("verilator")(FastBlockdevTests) + //runSuite("verilator")(FastBlockdevTests) } class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { - runSuite("verilator")(NICLoopbackTests) + //runSuite("verilator")(NICLoopbackTests) } //class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { // runSuite("verilator")(NICLoopbackTests) diff --git a/sims/firesim b/sims/firesim index 4e94c1a013..11cce04c53 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4e94c1a0131dc673f894c62f9a110637844a806a +Subproject commit 11cce04c538cd805d8d23d15f0b6231846bec1ce From 96e838c773c8a32de55f0636ee46bc5d7e73e556 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 17 May 2020 00:18:54 +0000 Subject: [PATCH 094/153] [firechip] Set the cover property library in FireSim Harnesses --- generators/firechip/src/main/scala/FireSim.scala | 1 + generators/firechip/src/main/scala/FireSimMulticlockPOC.scala | 1 + 2 files changed, 2 insertions(+) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 50f6f658fe..a4cea5ec1a 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -29,6 +29,7 @@ object NodeIdx { } class FireSim(implicit val p: Parameters) extends RawModule { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge) val clock = clockBridge.io.clocks.head val reset = WireInit(false.B) diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index 758cb05539..1f1ae06ac1 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -84,6 +84,7 @@ class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.Digita // Harness Definition class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) val refClock = clockBridge.io.clocks.head val reset = WireInit(false.B) From 465e96a5ca3b5198434bb983fab9bb7af8d6f2d2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 18 May 2020 12:21:17 -0700 Subject: [PATCH 095/153] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index cf536b685d..b02bd8eaca 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cf536b685dba3063b623ccffeaf68517e234966b +Subproject commit b02bd8eacaffe425811bd3fd8ef7d30772ae3cb7 From db65105163b3728fe89121d4feb73e091936c140 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 18 May 2020 19:23:16 +0000 Subject: [PATCH 096/153] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 11cce04c53..3f36872cdd 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 11cce04c538cd805d8d23d15f0b6231846bec1ce +Subproject commit 3f36872cdd5aec2ac28c7e3879e0a2e41eb00f57 From fa2d620fb2367712ef2aa4c5ac43b3e32f2f052f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 19 May 2020 00:50:14 +0000 Subject: [PATCH 097/153] Remove commented code in ScalaTests --- .../src/test/scala/ScalaTestSuite.scala | 77 +++---------------- 1 file changed, 10 insertions(+), 67 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 1e83271c6f..f92a7960ed 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -6,6 +6,7 @@ import java.io.File import scala.concurrent.{Future, Await, ExecutionContext} import scala.sys.process.{stringSeqToProcess, ProcessLogger} import scala.io.Source +import org.scalatest.Suites import freechips.rocketchip.diplomacy._ import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite} @@ -50,12 +51,6 @@ abstract class FireSimTestSuite( } } - //def runReplay(backend: String, replayBackend: String, name: String) = { - // val dir = (new File(outDir, backend)).getAbsolutePath - // (Seq("make", s"replay-$replayBackend", - // s"SAMPLE=${dir}/${name}.sample", s"output_dir=$dir") ++ makeArgs).! - //} - def runSuite(backend: String, debug: Boolean = false)(suite: RocketTestSuite) { // compile emulators behavior of s"${suite.makeTargetName} running on $backend" @@ -72,20 +67,6 @@ abstract class FireSimTestSuite( results.flatten foreach { case (name, exitcode) => it should s"pass $name" in { assert(exitcode == 0) } } - //replayBackends foreach { replayBackend => - // if (platformParams(midas.EnableSnapshot) && isCmdAvailable("vcs")) { - // assert((Seq("make", s"vcs-$replayBackend") ++ makeArgs).! == 0) // compile vcs - // suite.names foreach { name => - // it should s"replay $name in $replayBackend" in { - // assert(runReplay(backend, replayBackend, s"$name$postfix") == 0) - // } - // } - // } else { - // suite.names foreach { name => - // ignore should s"replay $name in $backend" - // } - // } - //} } else { ignore should s"pass $backend" } @@ -117,61 +98,23 @@ abstract class FireSimTestSuite( clean runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) - //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) - //runSuite("verilator")(FastBlockdevTests) } class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") -class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { - //runSuite("verilator")(NICLoopbackTests) -} -//class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { -// runSuite("verilator")(NICLoopbackTests) -//} -// Disabled until RAM optimizations re-enabled in multiclock -//class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") -//class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") - +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") // Multiclock tests class RocketMulticlockF1Tests extends FireSimTestSuite( "FireSimMulticlockPOC", "FireSimQuadRocketMulticlockConfig", "WithSynthAsserts_BaseF1Config") -// Jerry broke these -- damn it Jerry. -//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) -// extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { -// val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs -// -// lazy val generatorArgs = GeneratorArgs( -// midasFlowKind = "midas", -// targetDir = "generated-src", -// topModuleProject = "firesim.firesim", -// topModuleClass = "FireSimTraceGen", -// targetConfigProject = "firesim.firesim", -// targetConfigs = targetConfig ++ "_WithScalaTestFeatures", -// platformConfigProject = "firesim.firesim", -// platformConfigs = platformConfig) -// -// // From HasFireSimGeneratorUtilities -// // For the firesim utilities to use the same directory as the test suite -// override lazy val testDir = genDir -// -// // From TestSuiteCommon -// val targetTuple = generatorArgs.tupleName -// val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", -// s"TARGET_CONFIG=${generatorArgs.targetConfigs}", -// s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") -// -// it should "pass" in { -// assert(make("fsim-tracegen") == 0) -// } -//} -// -//class FireSimLLCTraceGenTest extends FireSimTraceGenTest( -// "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config") -// -//class FireSimL2TraceGenTest extends FireSimTraceGenTest( -// "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config") +class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") + +// This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call. +class CITests extends Suites( + new RocketF1Tests, + new BoomF1Tests, + new RocketNICF1Tests, + new RocketMulticlockF1Tests) From 7f3ae32e33b2e782da4dc4f8948b8927f4b3cc54 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 19 May 2020 01:00:25 +0000 Subject: [PATCH 098/153] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 3f36872cdd..a6911eca08 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3f36872cdd5aec2ac28c7e3879e0a2e41eb00f57 +Subproject commit a6911eca084608965c00d79931d208188e70d8cb From 0fc5a5409636646cd607a9e85cd46f198d629881 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 12:10:11 -0700 Subject: [PATCH 099/153] small cleanup to issues [ci skip] --- .github/ISSUE_TEMPLATE/bug-report.md | 12 +++++------- .github/ISSUE_TEMPLATE/question.md | 5 +++++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 4da4667edb..959b6306f0 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -8,16 +8,14 @@ labels: bug **Impact**: rtl | software | unknown | other +**Tell us about your environment:** +*Chipyard Version:* +*OS:* +*Other:* + **What is the current behavior?** **What is the expected behavior?** -**Please tell us about your environment:** - - **Other information** diff --git a/.github/ISSUE_TEMPLATE/question.md b/.github/ISSUE_TEMPLATE/question.md index b8c3f48294..f1b4e218f9 100644 --- a/.github/ISSUE_TEMPLATE/question.md +++ b/.github/ISSUE_TEMPLATE/question.md @@ -5,6 +5,11 @@ labels: question --- + + From dfc6c9ae5d475117bde6b8e0b582aa573c5f1cb7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 16:20:48 -0700 Subject: [PATCH 100/153] bump nvdla workload for one less submodule [ci skip] --- software/nvdla-workload | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/nvdla-workload b/software/nvdla-workload index 02faf59692..88b09e0171 160000 --- a/software/nvdla-workload +++ b/software/nvdla-workload @@ -1 +1 @@ -Subproject commit 02faf59692f88b66f8720d4eefa85aae385288a0 +Subproject commit 88b09e0171bdf6b3a77f711c2c8015dc727e460b From 9c73037e93be4dbea93ee9738ef9fb530287a226 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 19 May 2020 19:09:53 -0700 Subject: [PATCH 101/153] Version Upgrade Docs Notes (#545) * version upgrade notes * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez Co-authored-by: Abraham Gonzalez --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 08930f503d..88c8b21e99 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -86,3 +86,28 @@ This depends on what you are planning to do with Chipyard. * If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. * If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. + +Upgrading Chipyard Release Versions +------------------------------------------- + +In order to upgrade between Chipyard versions, we recommend using a fresh clone of the repository (or your fork, with the new release merged into it). + + +Chipyard is a complex framework that depends on a mix of build systems and scripts. Specifically, it relies on git submodules, on sbt build files, and on custom written bash scripts and generated files. +For this reason, upgrading between Chipyard versions is **not** as trivial as just running ``git submodule update -recursive``. This will result in recursive cloning of large submodules that are not necessarily used within your specific Chipyard environments. Furthermore, it will not resolve the status of stale state generated files which may not be compatible between release versions. + + +If you are an advanced git user, an alternative approach to a fresh repository clone may be to run ``git clean -dfx``, and then run the standard Chipyard setup sequence. This approach is dangerous, and **not-recommended** for users who are not deeply familiar with git, since it "blows up" the repository state and removes all untracked and modified files without warning. Hence, if you were working on custom un-committed changes, you would lose them. + +If you would still like to try to perform an in-place manual version upgrade (**not-recommended**), we recommend at least trying to resolve stale state in the following areas: + +* Delete stale ``target`` directories generated by sbt. + +* Delete jar collateral generated by FIRRTL (``lib/firrtl.jar``) + +* Re-generate generated scripts and source files (for example, ``env.sh``) + +* Re-generating/deleting target software state (Linux kernel binaries, Linux images) within FireMarshal + + +This is by no means a comprehensive list of potential stale state within Chipyard. Hence, as mentioned earlier, the recommended method for a Chipyard version upgrade is a fresh clone (or a merge, and then a fresh clone). From 0d087b6d3257da270c7d6ae08944c325f6afe310 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 18:54:37 -0700 Subject: [PATCH 102/153] add auto-gen comments | git init dromajo dir --- scripts/build-toolchains.sh | 3 +++ scripts/init-submodules-no-riscv-tools-nolog.sh | 1 + 2 files changed, 4 insertions(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index cbe1516182..fa24214cac 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -131,12 +131,14 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu # make Dromajo +git submodule --init $CHIPYARD_DIR/tools/dromajo/dromajo-src make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src cd "$RDIR" # create specific env.sh { + echo "# auto-generated by build-toolchains.sh" echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" echo "export RISCV=$(printf '%q' "$RISCV")" echo "export PATH=\${RISCV}/bin:\${PATH}" @@ -144,5 +146,6 @@ cd "$RDIR" } > env-$TOOLCHAIN.sh # create general env.sh +echo "# line auto-generated by build-toolchains.sh" >> env.sh echo "source \$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/env-$TOOLCHAIN.sh" >> env.sh echo "Toolchain Build Complete!" diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 888feb0ef1..f8ff84ee7e 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -73,4 +73,5 @@ git submodule update --init software/firemarshal if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml fi +echo "# line auto-generated by init-submodules-no-riscv-tools.sh" >> $RDIR/env.sh echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh From d2060947b6cf3da18e8abae90b076c78acc10708 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 19:44:35 -0700 Subject: [PATCH 103/153] bump toolchain version | fix git submodule update --- .circleci/config.yml | 2 +- scripts/build-toolchains.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 5361a9449b..03943fa85e 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -6,7 +6,7 @@ version: 2.1 parameters: tools-cache-version: type: string - default: "v4" + default: "v5" # default execution env.s executors: diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index fa24214cac..62a2f74b35 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -131,7 +131,7 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu # make Dromajo -git submodule --init $CHIPYARD_DIR/tools/dromajo/dromajo-src +git submodule update --init $CHIPYARD_DIR/tools/dromajo/dromajo-src make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src cd "$RDIR" From bbe296be51db298fce4fda2bf3fe992387db4714 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 20 May 2020 09:32:54 -0700 Subject: [PATCH 104/153] Force power to depend on sim-par, bump hammer for saif trigger Dependency is to have the power rerun on sim include the right yaml --- vlsi/Makefile | 4 ++-- vlsi/hammer | 2 +- vlsi/hammer-synopsys-plugins | 2 +- vlsi/power.mk | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index cbeceb3eb1..6eea3c6405 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -67,8 +67,8 @@ include $(base_dir)/common.mk ######################################################################################### # srams ######################################################################################### -SRAM_GENERATOR_CONF = $(build_dir)/sram_generator-input.yml -SRAM_CONF=$(build_dir)/sram_generator-output.json +SRAM_GENERATOR_CONF = $(OBJ_DIR)/sram_generator-input.yml +SRAM_CONF=$(OBJ_DIR)/sram_generator-output.json ## SRAM Generator .PHONY: sram_generator srams diff --git a/vlsi/hammer b/vlsi/hammer index e9232084e7..ec0171a889 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit e9232084e7682cd263dab9d887d59900b4242379 +Subproject commit ec0171a88950414f4d6dc59407cc3493f2705d9d diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index f8579e55b9..b2d4233f4f 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit f8579e55b96208758c0ed43f3bdba0bbc67ef6b5 +Subproject commit b2d4233f4f6ca9df776931dc32c15c69c48bd93e diff --git a/vlsi/power.mk b/vlsi/power.mk index a5e1633b02..f394ced738 100644 --- a/vlsi/power.mk +++ b/vlsi/power.mk @@ -1,5 +1,5 @@ .PHONY: $(POWER_CONF) -power: $(POWER_CONF) +power: $(POWER_CONF) sim-par power: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) redo-power: $(POWER_CONF) redo-power: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) From 7208ab0b68afa1af2140bfb721a3aaea13be000d Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Fri, 15 May 2020 10:26:37 -0700 Subject: [PATCH 105/153] Don't try to init nonexistent midas submodule --- scripts/init-submodules-no-riscv-tools-nolog.sh | 5 ----- 1 file changed, 5 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index f8ff84ee7e..70b504b420 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -59,11 +59,6 @@ git submodule update --init generators/sha3 git config --unset submodule.sims/firesim.update # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim -( - cd sims/firesim - # Initialize dependencies for MIDAS-level RTL simulation - git submodule update --init sim/midas -) git config submodule.sims/firesim.update none # Only shallow clone needed for basic SW tests From 5407018bb4aebcdbddfa6309d6f19aadd7449a58 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 21 May 2020 12:26:45 -0700 Subject: [PATCH 106/153] Respond to PR comments clean up usage of vcs.mk Bump hammer and plugins for updated API --- sims/vcs/Makefile | 31 +----------------- vcs.mk | 8 +++-- vlsi/Makefile | 62 +++++++++++++----------------------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 6 files changed, 32 insertions(+), 75 deletions(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index e8a30b0c5e..6b388164b7 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -41,36 +41,7 @@ include $(base_dir)/common.mk ######################################################################################### VCS = vcs -full64 -VCS_CC_OPTS = \ - -CC "-I$(VCS_HOME)/include" \ - -CC "-I$(RISCV)/include" \ - -CC "-std=c++11" \ - $(RISCV)/lib/libfesvr.a - -VCS_NONCC_OPTS = \ - +lint=all,noVCDE,noONGS,noUI \ - -error=PCWM-L \ - -timescale=1ns/10ps \ - -quiet \ - -q \ - +rad \ - +v2k \ - +vcs+lic+wait \ - +vc+list \ - -f $(sim_common_files) \ - -sverilog \ - +incdir+$(build_dir) \ - +define+CLOCK_PERIOD=1.0 \ - $(sim_vsrcs) \ - +define+PRINTF_COND=$(TB).printf_cond \ - +define+STOP_COND=!$(TB).reset \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN \ - +libext+.v - -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) ######################################################################################### # vcs simulator rules diff --git a/vcs.mk b/vcs.mk index c0450da5c3..fb1e6781e1 100644 --- a/vcs.mk +++ b/vcs.mk @@ -3,8 +3,10 @@ PERMISSIVE_OFF=+permissive-off WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +CLOCK_PERIOD ?= 1.0 +RESET_DELAY ?= 777.7 + VCS_CC_OPTS = \ - -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ -CC "-std=c++11" @@ -21,12 +23,14 @@ VCS_NONCC_OPTS = \ +vc+list \ -f $(sim_common_files) \ -sverilog \ + -debug_pp \ +incdir+$(build_dir) \ $(sim_vsrcs) \ +libext+.v VCS_DEFINE_OPTS = \ - +define+CLOCK_PERIOD=1.0 \ + +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ + +define+RESET_DELAY=$(RESET_DELAY) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ diff --git a/vlsi/Makefile b/vlsi/Makefile index 6eea3c6405..533a459865 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -106,41 +106,28 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " input_files_meta: 'append'" >> $@ echo " timescale: '1ns/10ps'" >> $@ - echo " options: [" >> $@ - echo " '$(RISCV)/lib/libfesvr.a'," >> $@ - echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ - echo " '-error=PCWM-L'," >> $@ - echo " '-quiet'," >> $@ - echo " '-q'," >> $@ - echo " '+rad'," >> $@ - echo " '+v2k'," >> $@ - echo " '+vcs+lic+wait'," >> $@ - echo " '+vc+list'," >> $@ - echo " '-f $(sim_common_files)'," >> $@ - echo " '-sverilog'," >> $@ - echo " '-debug_pp']" >> $@ + echo " options:" >> $@ + for x in $(VCS_NONCC_OPTS); do \ + echo ' - "'$$x'"' >> $@; \ + done echo " options_meta: 'append'" >> $@ - echo " defines: [" >> $@ - echo " 'CLOCK_PERIOD=1.0'," >> $@ - echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ - echo " 'STOP_COND=!$(TB).reset'," >> $@ - echo " 'RANDOMIZE_MEM_INIT'," >> $@ - echo " 'RANDOMIZE_REG_INIT'," >> $@ - echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ - echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " defines:" >> $@ + for x in $(VCS_DEFINE_OPTS); do \ + echo ' - "'$$x'"' >> $@; \ + done echo " defines_meta: 'append'" >> $@ - echo " compiler_opts: [" >> $@ - echo " '-I$(RISCV)/include'," >> $@ - echo " '-std=c++11']" >> $@ + echo " compiler_opts:" >> $@ + for x in $(filter-out -CC,$(VCS_CC_OPTS)); do \ + echo ' - "'$$x'"' >> $@; \ + done echo " compiler_opts_meta: 'append'" >> $@ echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ - echo " execution_flags: [" >> $@ - echo " '+max-cycles=$(timeout_cycles)'," >> $@ + echo " execution_flags:" >> $@ + echo " - '+max-cycles=$(timeout_cycles)'" >> $@ for x in $(SIM_FLAGS); do \ - echo ' "'$$x'",' >> $@; \ + echo ' - "'$$x'"' >> $@; \ done - echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ echo " benchmarks: ['$(BINARY)']" >> $@ echo " tb_dut: 'testHarness.top'" >> $@ @@ -148,22 +135,19 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ - echo " defines: [" >> $@ - echo " 'DEBUG']" >> $@ + echo " defines: ['DEBUG']" >> $@ echo " defines_meta: 'append'" >> $@ - echo " execution_flags: [" >> $@ + echo " execution_flags:" >> $@ for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ - echo ' "'$$x'",' >> $@; \ + echo ' - "'$$x'"' >> $@; \ done - echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ - echo " defines: [" >> $@ - echo " 'NTC']" >> $@ + echo " defines: ['NTC']" >> $@ echo " defines_meta: 'append'" >> $@ echo " timing_annotated: 'true'" >> $@ @@ -179,13 +163,11 @@ $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_fi echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@ echo " ]" >> $@ echo " waveforms: [" >> $@ - echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@ - echo " ]" >> $@ - echo " start_times: [" >> $@ - echo " 0" >> $@ + #echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@ echo " ]" >> $@ + echo " start_times: ['0ns']" >> $@ echo " end_times: [" >> $@ - echo " 15000" >> $@ #timeout_cycles * clock_period + echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ echo " ]" >> $@ ######################################################################################### diff --git a/vlsi/hammer b/vlsi/hammer index ec0171a889..41feaed2d4 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit ec0171a88950414f4d6dc59407cc3493f2705d9d +Subproject commit 41feaed2d42e59280538a4dc041af625f88a0edc diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 6715c3deb0..cf2304c211 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 6715c3deb074a90860fb151564e83e04bbd24e44 +Subproject commit cf2304c21166cea140cc8e039824feeb51c89e0d diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index b2d4233f4f..451e072193 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit b2d4233f4f6ca9df776931dc32c15c69c48bd93e +Subproject commit 451e072193f13f4a25cfa891426a52dbd7556c03 From 6ec2fb0de5ebbbea2be0a69628afdf23ae08926a Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 22 May 2020 16:25:06 -0700 Subject: [PATCH 107/153] Remove +define+ from front of defines since sim plugin does that already --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 533a459865..5138c48d07 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -112,7 +112,7 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " options_meta: 'append'" >> $@ echo " defines:" >> $@ - for x in $(VCS_DEFINE_OPTS); do \ + for x in $(subst +define+,,$(VCS_DEFINE_OPTS)); do \ echo ' - "'$$x'"' >> $@; \ done echo " defines_meta: 'append'" >> $@ From 106165e278d707f954bc43e55acda89be319fc78 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sat, 23 May 2020 20:29:50 -0700 Subject: [PATCH 108/153] Also clean up new generated yamls. Bump hammer for new makefile --- vlsi/Makefile | 2 +- vlsi/hammer | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 5138c48d07..d41a66ee0c 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -213,4 +213,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) ######################################################################################### .PHONY: clean clean: - rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) + rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF) diff --git a/vlsi/hammer b/vlsi/hammer index 41feaed2d4..d5b522ad1a 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 41feaed2d42e59280538a4dc041af625f88a0edc +Subproject commit d5b522ad1aace2a534c677bdca7b16f473efe217 From 0b1707c117c599777ee22f7ae7928bedf1c67fcd Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sat, 23 May 2020 23:27:01 -0700 Subject: [PATCH 109/153] Filter out cc files and SimDRAM.v from hammer syn inputs This should probably be handled in a more generic way. I'm not sure why the SimDRAM stuff is showing up anywhere but the harness file includes --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index d41a66ee0c..4c637fdba1 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -190,7 +190,7 @@ $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(VLSI_RTL) `cat $(VLSI_BB)`; do \ + for x in $(VLSI_RTL) $(filter-out %SimDRAM.v,$(filter-out %.cc,$(shell cat $(VLSI_BB)))); do \ echo ' - "'$$x'"' >> $@; \ done From 29664cdf6a575b580714daaa2a2871cedd502733 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sun, 24 May 2020 09:29:22 -0700 Subject: [PATCH 110/153] Upgrade verilator to support permissive args in the same way as vcs It previously only supported them as the last argument. Supporting them in this case would have removed some of the DRY code that is able to handle both simulators. --- .../src/main/resources/csrc/emulator.cc | 41 ++++++++++++------- sims/verilator/Makefile | 4 +- 2 files changed, 29 insertions(+), 16 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 6ff63d3ead..1a5a7ac3a5 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -126,27 +126,30 @@ int main(int argc, char** argv) int verilog_plusargs_legal = 1; dramsim = 0; + opterr = 1; while (1) { static struct option long_options[] = { - {"cycle-count", no_argument, 0, 'c' }, - {"help", no_argument, 0, 'h' }, - {"max-cycles", required_argument, 0, 'm' }, - {"seed", required_argument, 0, 's' }, - {"rbb-port", required_argument, 0, 'r' }, - {"verbose", no_argument, 0, 'V' }, - {"dramsim", no_argument, 0, 'D' }, + {"cycle-count", no_argument, 0, 'c' }, + {"help", no_argument, 0, 'h' }, + {"max-cycles", required_argument, 0, 'm' }, + {"seed", required_argument, 0, 's' }, + {"rbb-port", required_argument, 0, 'r' }, + {"verbose", no_argument, 0, 'V' }, + {"dramsim", no_argument, 0, 'D' }, + {"permissive", no_argument, 0, 'p' }, + {"permissive-off", no_argument, 0, 'o' }, #if VM_TRACE - {"vcd", required_argument, 0, 'v' }, - {"dump-start", required_argument, 0, 'x' }, + {"vcd", required_argument, 0, 'v' }, + {"dump-start", required_argument, 0, 'x' }, #endif HTIF_LONG_OPTIONS }; int option_index = 0; #if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:Dpo", long_options, &option_index); #else - int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:VDpo", long_options, &option_index); #endif if (c == -1) break; retry: @@ -160,6 +163,8 @@ int main(int argc, char** argv) case 'r': rbb_port = atoi(optarg); break; case 'V': verbose = true; break; case 'D': dramsim = 1; break; + case 'p': opterr = 0; break; + case 'o': opterr = 1; break; #if VM_TRACE case 'v': { vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); @@ -195,6 +200,10 @@ int main(int argc, char** argv) c = 'c'; else if (arg == "+dramsim") c = 'D'; + else if (arg == "+permissive") + c = 'p'; + else if (arg == "+permissive-off") + c = 'o'; // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { @@ -226,9 +235,13 @@ int main(int argc, char** argv) } htif_option++; } - std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" - << arg << "\"\n"; - c = '?'; + if(opterr) { + std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" + << arg << "\"\n"; + c = '?'; + } else { + c = 'p'; + } } goto retry; } diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9d99f78cc7..d9ee5dc563 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,8 +28,8 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON= -PERMISSIVE_OFF= +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off WAVEFORM_FLAG=-v$(sim_out_name).vcd From a7119fb5ed080a846cdf3a061cd06e38230e85ec Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sun, 24 May 2020 10:31:24 -0700 Subject: [PATCH 111/153] Hoist permissive settings out of inner makefiles --- sims/vcs/Makefile | 3 --- sims/verilator/Makefile | 3 --- variables.mk | 2 ++ 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 80e5a1a8e7..a3ff6504b9 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,9 +25,6 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd .PHONY: default debug diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index d9ee5dc563..1b9276acc9 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,9 +28,6 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - WAVEFORM_FLAG=-v$(sim_out_name).vcd .PHONY: default debug diff --git a/variables.mk b/variables.mk index ad981245f9..4d49d5fef7 100644 --- a/variables.mk +++ b/variables.mk @@ -136,6 +136,8 @@ output_dir=$(sim_dir)/output/$(long_name) ######################################################################################### # helper variables to run binaries ######################################################################################### +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off BINARY ?= override SIM_FLAGS += +dramsim +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose From ae1aa31fce04db79789bfe8a9a61071ce588e436 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 20:23:19 +0000 Subject: [PATCH 112/153] Incorporate feedback --- docs/Customization/Dsptools-Blocks.rst | 31 +++++++++---- .../chipyard/src/main/scala/DigitalTop.scala | 4 +- .../src/main/scala/config/RocketConfigs.scala | 44 +++++++++++++++---- .../scala/example/dsptools/GenericFIR.scala | 12 ++--- ...rough.scala => StreamingPassthrough.scala} | 4 +- 5 files changed, 68 insertions(+), 27 deletions(-) rename generators/chipyard/src/main/scala/example/dsptools/{Passthrough.scala => StreamingPassthrough.scala} (97%) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 228f5f91b4..ba189ac5c0 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -1,11 +1,24 @@ .. _dsptools-blocks: +Dsptools is a Chisel library that aids in writing custom signal processing accelerators. It does this by: +* Giving types and helpers that allow you to express mathematical operations more directly. +* Typeclasses that let you write polymorphic generators, for example an FIR filter generator that works for both real- and complex-valued filters. +* Structures for packaging DSP blocks and integrating them into a rocketchip-based SoC. +* Test harnesses for testing DSP circuits, as well as VIP-style drivers and monitors for DSP blocks. + +The `Dsptools `_ repository has more documentation. + + Dsptools Blocks =============== +A ``DspBlock`` is the basic unit of signal processing functionality that can be integrated into an SoC. +It has a AXI4-stream interface and an optional memory interface. +The idea idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. +A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case the streaming interfaces are connected serially into a pipeline, and a bus is instatiated and connected to every block with a memory interface. -Another way to create a MMIO peripheral is to use the Dsptools library for Chisel. In this method, a memory interface is created by creating a "chain". This chain consists of a custom module placed inside a ``DspBlock``, which is then sandwiched between a ``ReadQueue`` and ``WriteQueue``. Those queues then act as memory mapped interfaces to the Rocket Chip SoCs. This section will again primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. +This project has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. -For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/example/src/main/scala/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO +For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/example/src/main/scala/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type generic, which means that they can be instantiated for any datatype that implements ``Ring`` operations per the specifications on ``T``. @@ -56,10 +69,10 @@ As in the previous MMIO example, we use a cake pattern to hook up our module to .. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala :language: scala - :start-after: DOC include start: CanHavePeripheryUIntTestFIR chisel - :end-before: DOC include end: CanHavePeripheryUIntTestFIR chisel + :start-after: DOC include start: CanHavePeripheryFIR chisel + :end-before: DOC include end: CanHavePeripheryFIR chisel -Note that this is the point at which we decide the datatype for our FIR. It is also possible with some reworking to push the datatype selection out to the top level. +Note that this is the point at which we decide the datatype for our FIR. Our module does not need to be connected to concrete IOs or wires, so we do not need to create a concrete trait. @@ -73,12 +86,12 @@ Once again following the path of the previous MMIO example, we now want to mix o :start-after: DOC include start: Top :end-before: DOC include end: Top -Finally, we create the configuration class in ``generators/example/src/main/scala/RocketConfigs.scala`` that uses the ``WithUIntTestFIR`` mixin defined in ``generators/example/src/main/scala/ConfigMixins.scala``. +Finally, we create the configuration class in ``generators/example/src/main/scala/RocketConfigs.scala`` that uses the ``WithFIR`` mixin defined in ``generators/example/src/main/scala/ConfigMixins.scala``. .. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala :language: scala - :start-after: DOC include start: WithTestFIR - :end-before: DOC include end: WithTestFIR + :start-after: DOC include start: WithFIR + :end-before: DOC include end: WithFIR .. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala :language: scala @@ -88,7 +101,7 @@ Finally, we create the configuration class in ``generators/example/src/main/scal Testing ------- -We can now test that the FIR is working. The test program is found in ``tests/gcd.c``. +We can now test that the FIR is working. The test program is found in ``tests/fir.c``. .. literalinclude:: ../../tests/fir.c :language: c diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index a31079e68b..0866676b58 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -23,8 +23,8 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryUIntTestFIR // Enables optionally adding the FIR example widget - with chipyard.example.CanHavePeripheryUIntStreamingPassthrough // Enables optionally adding the passthrough example widget + with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the FIR example widget + with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { override lazy val module = new DigitalTopModule(this) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 4bc3a6d542..a55718ffac 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -426,16 +426,44 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket -class UIntStreamingPassthroughRocketConfig extends Config( - new chipyard.example.WithUIntStreamingPassthrough ++ // use top with tilelink-controlled passthrough - new RocketConfig -) +class StreamingPassthroughRocketConfig extends Config( + new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include start: FIRRocketConfig -class UIntTestFIRRocketConfig extends Config ( - new chipyard.example.WithUIntTestFIR ++ // use top with tilelink-controlled FIR - new RocketConfig -) +class FIRRocketConfig extends Config ( + new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include end: FIRRocketConfig class SmallNVDLARocketConfig extends Config( diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 45093f9a6d..6a18af1a5f 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -200,8 +200,8 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], para } // DOC include end: TLGenericFIRChain chisel -// DOC include start: CanHavePeripheryUIntTestFIR chisel -trait CanHavePeripheryUIntTestFIR extends BaseSubsystem { +// DOC include start: CanHavePeripheryFIR chisel +trait CanHavePeripheryFIR extends BaseSubsystem { val fir = p(GenericFIRKey) match { case Some(params) => { val fir = LazyModule(new TLGenericFIRChain( @@ -216,13 +216,13 @@ trait CanHavePeripheryUIntTestFIR extends BaseSubsystem { case None => None } } -// DOC include end: CanHavePeripheryUIntTestFIR chisel +// DOC include end: CanHavePeripheryFIR chisel /** * Mixin to add FIR to rocket config */ -// DOC include start: WithTestFIR -class WithUIntTestFIR extends Config((site, here, up) => { +// DOC include start: WithFIR +class WithFIR extends Config((site, here, up) => { case GenericFIRKey => Some(GenericFIRParams(depth = 8)) }) -// DOC include end: WithTestFIR +// DOC include end: WithFIR diff --git a/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala similarity index 97% rename from generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala rename to generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 1d953b83bd..87f977607e 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -133,7 +133,7 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara lazy val module = new LazyModuleImp(this) } -trait CanHavePeripheryUIntStreamingPassthrough { this: BaseSubsystem => +trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { val passthrough = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) @@ -150,7 +150,7 @@ trait CanHavePeripheryUIntStreamingPassthrough { this: BaseSubsystem => /** * Mixin to add passthrough to rocket config */ -class WithUIntStreamingPassthrough extends Config((site, here, up) => { +class WithStreamingPassthrough extends Config((site, here, up) => { case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8)) }) From e678e01c0a865c1774f2705f5a519ed84036e74d Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 20:26:18 +0000 Subject: [PATCH 113/153] Bump dsptools --- tools/dsptools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dsptools b/tools/dsptools index 63ac4b941b..7c40829718 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 63ac4b941bc711a0c7efd48b6418c86756b403ad +Subproject commit 7c40829718592fc99b011d53595f01b00a3d68cf From 7c074661d5a832105a07b3cc1dc3217336eadb54 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 20:27:58 +0000 Subject: [PATCH 114/153] Add CI for dsptools examples --- .circleci/config.yml | 38 ++++++++++++++++++++++++++++++++++++++ .circleci/defaults.sh | 2 ++ .circleci/run-tests.sh | 8 ++++++++ 3 files changed, 48 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index 03943fa85e..1d205ee971 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -204,6 +204,16 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-sha3" + prepare-chipyard-fir: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-fir" + prepare-chipyard-passthrough: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-passthrough" prepare-chipyard-hetero: executor: main-env steps: @@ -287,6 +297,16 @@ jobs: steps: - run-tests: project-key: "chipyard-sha3" + chipyard-fir-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-fir" + chipyard-passthrough-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-passthrough" chipyard-hetero-run-tests: executor: main-env steps: @@ -439,6 +459,16 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-fir: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-passthrough: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-hetero: requires: - install-riscv-toolchain @@ -525,6 +555,14 @@ workflows: requires: - prepare-chipyard-sha3 + - chipyard-fir-run-tests: + requires: + - prepare-chipyard-fir + + - chipyard-passthrough-run-tests: + requires: + - prepare-chipyard-passthrough + - chipyard-hetero-run-tests: requires: - prepare-chipyard-hetero diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index d9699df8e5..6225ad9571 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -46,6 +46,8 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim declare -A mapping mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" +mapping["chipyard-fir"]="SUB_PROJECT=chipyard CONFIG=FIRRocketConfig" +mapping["chipyard-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig" mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 19a0e566c6..f319880b34 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -62,6 +62,14 @@ case $1 in (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv ;; + chipyard-passthrough) + make -C $LOCAL_CHIPYARD_DIR/tests + $LOCAL_SIM_DIR/simulator-chipyard-StreamingPassthroughRocketConfig $LOCAL_CHIPYARD_DIR/tests/passthrough.riscv + ;; + chipyard-fir) + make -C $LOCAL_CHIPYARD_DIR/tests + $LOCAL_SIM_DIR/simulator-chipyard-FIRRocketConfig $LOCAL_CHIPYARD_DIR/tests/fir.riscv + ;; chipyard-spiflashread) make -C $LOCAL_CHIPYARD_DIR/tests make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary From 863b3a7bc324548ac09806fa79515b98ac56eadf Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:08:30 -0700 Subject: [PATCH 115/153] Fix doc references --- docs/Customization/Dsptools-Blocks.rst | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index ba189ac5c0..45053bfaf7 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -18,16 +18,16 @@ A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case th This project has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. -For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/example/src/main/scala/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. +For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type generic, which means that they can be instantiated for any datatype that implements ``Ring`` operations per the specifications on ``T``. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: GenericFIR chisel :end-before: DOC include end: GenericFIR chisel -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: GenericFIRDirectCell chisel :end-before: DOC include end: GenericFIRDirectCell chisel @@ -42,7 +42,7 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an 3. Cast the module input data to the input type of ``GenericFIR`` (``GenericFIRBundle``) and attach. 4. Cast the output of ``GenericFIR`` to ``UInt`` and attach to the module output. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: GenericFIRBlock chisel :end-before: DOC include end: GenericFIRBlock chisel @@ -51,14 +51,14 @@ Connecting by TileLink ---------------------- With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: TLGenericFIRBlock chisel :end-before: DOC include end: TLGenericFIRBlock chisel -We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/example/src/main/scala/dsptools/DspBlocks.scala``. Inside our chain, we construct an instance of each queue as well as our ``TLGenericFIRBlock``. We then take the ``steamnode`` from each module and wire them all together to link the chain. +We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala``. Inside our chain, we construct an instance of each queue as well as our ``TLGenericFIRBlock``. We then take the ``steamnode`` from each module and wire them all together to link the chain. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: TLGenericFIRChain chisel :end-before: DOC include end: TLGenericFIRChain chisel @@ -67,7 +67,7 @@ Top Level Traits ---------------- As in the previous MMIO example, we use a cake pattern to hook up our module to our SoC. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: CanHavePeripheryFIR chisel :end-before: DOC include end: CanHavePeripheryFIR chisel @@ -79,21 +79,21 @@ Our module does not need to be connected to concrete IOs or wires, so we do not Constructing the Top and Config ------------------------------- -Once again following the path of the previous MMIO example, we now want to mix our traits into the system as a whole. The code is from ``generators/example/src/main/scala/Top.scala`` +Once again following the path of the previous MMIO example, we now want to mix our traits into the system as a whole. The code is from ``generators/chipyard/src/main/scala/DigitalTop.scala`` -.. literalinclude:: ../../generators/example/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala :start-after: DOC include start: Top :end-before: DOC include end: Top -Finally, we create the configuration class in ``generators/example/src/main/scala/RocketConfigs.scala`` that uses the ``WithFIR`` mixin defined in ``generators/example/src/main/scala/ConfigMixins.scala``. +Finally, we create the configuration class in ``generators/chipyard/src/main/scala/config/RocketConfigs.scala`` that uses the ``WithFIR`` mixin defined in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: WithFIR :end-before: DOC include end: WithFIR -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: FIRRocketConfig :end-before: DOC include end: FIRRocketConfig From f619b69e330e9751fac6cb373d5b866d8beeec12 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:11:02 -0700 Subject: [PATCH 116/153] Update docs/Customization/Dsptools-Blocks.rst Co-authored-by: alonamid --- docs/Customization/Dsptools-Blocks.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 45053bfaf7..1f7dcfde61 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -13,7 +13,7 @@ Dsptools Blocks =============== A ``DspBlock`` is the basic unit of signal processing functionality that can be integrated into an SoC. It has a AXI4-stream interface and an optional memory interface. -The idea idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. +The idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case the streaming interfaces are connected serially into a pipeline, and a bus is instatiated and connected to every block with a memory interface. This project has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. From 0cdc8fe244a507ac7fe886572f3a6e2c23415a2e Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:13:15 -0700 Subject: [PATCH 117/153] Remove comments for non-unique portions of config fragment --- .../src/main/scala/config/RocketConfigs.scala | 66 +++++++++---------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index a55718ffac..76ed912f90 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -427,43 +427,43 @@ class RingSystemBusRocketConfig extends Config( // DOC include end: RingSystemBusRocket class StreamingPassthroughRocketConfig extends Config( - new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) // DOC include start: FIRRocketConfig class FIRRocketConfig extends Config ( new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) // DOC include end: FIRRocketConfig class SmallNVDLARocketConfig extends Config( From 77a624f4883eef706ee03aba57793c7b560d0f66 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:19:52 -0700 Subject: [PATCH 118/153] Fix bad capitalization in doc reference --- .../chipyard/src/main/scala/example/dsptools/GenericFIR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 6a18af1a5f..a2d2ad0509 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -174,7 +174,7 @@ abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] } // DOC include end: GenericFIRBlock chisel -// DOC include start: TLGenericFIRBLock chisel +// DOC include start: TLGenericFIRBlock chisel class TLGenericFIRBlock[T<:Data:Ring] ( val genIn: T, From c4d791d3239f1fe305bd8898b7214f9ec8472cb2 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:22:39 -0700 Subject: [PATCH 119/153] Update reference to DigitalTop in doc --- docs/Customization/Dsptools-Blocks.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 1f7dcfde61..edad9ae059 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -83,8 +83,8 @@ Once again following the path of the previous MMIO example, we now want to mix o .. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop Finally, we create the configuration class in ``generators/chipyard/src/main/scala/config/RocketConfigs.scala`` that uses the ``WithFIR`` mixin defined in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. From 1157c6f93dae747335c6a59cc0d0088c1a302738 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:26:17 -0700 Subject: [PATCH 120/153] Resolve duplicate label --- docs/Customization/Dsptools-Blocks.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index edad9ae059..28f4ced1c4 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -47,7 +47,7 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an :start-after: DOC include start: GenericFIRBlock chisel :end-before: DOC include end: GenericFIRBlock chisel -Connecting by TileLink +Connecting DspBlock by TileLink ---------------------- With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. From 3d4a6d4ea672e2d6495117b27fbc95bb70f4c69a Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:28:32 -0700 Subject: [PATCH 121/153] Ugh restructured text sucks --- docs/Customization/Dsptools-Blocks.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 28f4ced1c4..f8808cd39b 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -48,7 +48,7 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an :end-before: DOC include end: GenericFIRBlock chisel Connecting DspBlock by TileLink ----------------------- +------------------------------- With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala From f24fd2a1137a235381596c61b60ade84208671ba Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 25 May 2020 14:29:07 -0700 Subject: [PATCH 122/153] update mem docs | add l1 scratchpad config --- docs/Customization/Memory-Hierarchy.rst | 15 ++++++++-- .../src/main/scala/config/RocketConfigs.scala | 29 ++++++++++++++++--- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 733e70c6e8..554b6d5fdc 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -31,8 +31,8 @@ Note that these configurations fully remove the L2 cache and mbus. .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala - :start-after: DOC include start: scratchpadrocket - :end-before: DOC include end: scratchpadrocket + :start-after: DOC include start: l1scratchpadrocket + :end-before: DOC include end: l1scratchpadrocket This configuration fully removes the L2 cache and memory bus by setting the @@ -94,11 +94,20 @@ number of DRAM channels is restricted to powers of two. new freechips.rocketchip.subsystem.WithNMemoryChannels(2) - In VCS and Verilator simulation, the DRAM is simulated using the ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each memory channel. +Instead of connecting to off-chip DRAM, you can instead connect a scratchpad +and remove the off-chip link. This is done by adding a fragment like +``testchipip.WithBackingScratchpad`` to your configuration and removing the +memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala + :language: scala + :start-after: DOC include start: mbusscratchpadrocket + :end-before: DOC include end: mbusscratchpadrocket + If you want a more realistic memory simulation, you can use FireSim, which can simulate the timing of DDR3 controllers. More documentation on FireSim memory models is available in the `FireSim docs `_. diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f29c5804f7..32077ad844 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -384,14 +384,35 @@ class LoopbackNICRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include start: scratchpadrocket -class ScratchpadRocketConfig extends Config( +// DOC include start: l1scratchpadrocket +class L1ScratchpadSmallRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new testchipip.WithBackingScratchpad ++ // add backing scratchpad + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) +// DOC include end: l1scratchpadrocket + +// DOC include start: mbusscratchpadrocket +class MbusScratchpadRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -403,7 +424,7 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include end: scratchpadrocket +// DOC include end: mbusscratchpadrocket // DOC include start: RingSystemBusRocket class RingSystemBusRocketConfig extends Config( From 541d037c5d6931640ff868a1f9255c081d0c9497 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:33:00 -0700 Subject: [PATCH 123/153] Remove another duplicate label --- docs/Customization/Dsptools-Blocks.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index f8808cd39b..ebebd12b4f 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -98,8 +98,8 @@ Finally, we create the configuration class in ``generators/chipyard/src/main/sca :start-after: DOC include start: FIRRocketConfig :end-before: DOC include end: FIRRocketConfig -Testing -------- +FIR Testing +----------- We can now test that the FIR is working. The test program is found in ``tests/fir.c``. From 7a0d8ea772f6e3e4f1a6fd246f901c6f569f73b7 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 17:19:48 -0700 Subject: [PATCH 124/153] Update generators/chipyard/src/main/scala/DigitalTop.scala Co-authored-by: alonamid --- generators/chipyard/src/main/scala/DigitalTop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 0866676b58..0824b6a9e7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -24,7 +24,7 @@ class DigitalTop(implicit p: Parameters) extends System with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the FIR example widget - with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the passthrough example widget + with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { override lazy val module = new DigitalTopModule(this) From a6e96b649685bd3266d47841511d0f73d1a15ee1 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 17:19:56 -0700 Subject: [PATCH 125/153] Update generators/chipyard/src/main/scala/DigitalTop.scala Co-authored-by: alonamid --- generators/chipyard/src/main/scala/DigitalTop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 0824b6a9e7..7db9f7f3d6 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -23,7 +23,7 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the FIR example widget + with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { From 461f24c86e3d626ff6613b728adfe178e07ff954 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 26 May 2020 08:27:34 -0700 Subject: [PATCH 126/153] Update publications in README with SonicBOOM and IEEE Micro (#570) --- README.md | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 5d44edb375..c2feb678b8 100644 --- a/README.md +++ b/README.md @@ -29,13 +29,28 @@ Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb * See [CONTRIBUTING.md](/CONTRIBUTING.md) -## Chipyard-related Publications +## Attribution and Chipyard-related Publications -These publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs. +If used for research, please cite Chipyard by the following publication: + +``` +@article{chipyard, + author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje}, + journal={IEEE Micro}, + title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs}, + year={2020}, + pages={}, + doi={10.1109/MM.2020.2996616}, + ISSN={1937-4143}, +} +``` + +These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs. * **Generators** * **Rocket Chip**: K. Asanovic, et al., *UCB EECS TR*. [PDF](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf). * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://www.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf). + * **SonicBOOM (BOOMv3): J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf). * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf). * **Gemmini**: H. Genc, et al., *arXiv*. [PDF](https://arxiv.org/pdf/1911.09925). * **Sims** From 0a954ae4cc0b30db929f6d90ab20a0c5bc62a4b6 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 26 May 2020 10:03:13 -0700 Subject: [PATCH 127/153] Move all non-synthesizable constructs into the test harness --- .../chipyard/src/main/scala/IOBinders.scala | 68 ++++++++++++++++--- .../src/main/scala/config/RocketConfigs.scala | 20 +++++- 2 files changed, 76 insertions(+), 12 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 4c27a65aca..94fb50f4d9 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters} import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ @@ -182,6 +183,20 @@ object AddIOCells { port.suggestName("serial") (port, ios) } + + def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { + io.zip(node.in).map{ case (mem_axi4, (_, edge)) => { + val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some("iocell_mem_axi4")) + port.suggestName("mem_axi4") + (port, edge, ios) + }} + } + + def blockDev(bdev: BlockDeviceIO): (BlockDeviceIO, Seq[IOCell]) = { + val (port, ios) = IOCell.generateIOFromSignal(bdev, Some("iocell_bdev")) + port.suggestName("bdev") + (port, ios) + } } // DOC include start: WithGPIOTiedOff @@ -211,11 +226,25 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ }) class WithSimBlockDevice extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectSimBlockDevice(system.clock, system.reset.asBool); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => + val (port, ios) = AddIOCells.blockDev(bdev) + val harnessFn = (th: chipyard.TestHarness) => { + SimBlockDevice.connect(th.clock, th.reset.asBool, Some(port))(system.p) + Nil + } + Seq((Seq(port), ios, Some(harnessFn))) + }.getOrElse(Nil) }) class WithBlockDeviceModel extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectBlockDeviceModel(); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => + val (port, ios) = AddIOCells.blockDev(bdev) + val harnessFn = (th: chipyard.TestHarness) => { + BlockDeviceModel.connect(Some(port))(system.p) + Nil + } + Seq((Seq(port), ios, Some(harnessFn))) + }.getOrElse(Nil) }) class WithLoopbackNIC extends OverrideIOBinder({ @@ -232,21 +261,38 @@ class WithSimNIC extends OverrideIOBinder({ // accessible to the IOBinder // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => SimAXIMem.connectMem(system)(system.p); Nil + (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { + val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node) + // TODO: we are inlining the connectMem method of SimAXIMem because + // it takes in a dut rather than seq of axi4 ports + val harnessFn = (th: chipyard.TestHarness) => { + peiTuples.map { case (port, edge, ios) => + val mem = LazyModule(new SimAXIMem(edge, size = system.p(ExtMem).get.master.size)(system.p)) + Module(mem.module).suggestName("mem") + mem.io_axi4.head <> port + } + Nil + } + Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) + } }) // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { - (system.mem_axi4 zip system.memAXI4Node.in).foreach { case (io, (_, edge)) => - val memSize = system.p(ExtMem).get.master.size - val lineSize = system.p(CacheBlockBytes) - val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) - mem.io.axi <> io - mem.io.clock := system.module.clock - mem.io.reset := system.module.reset + val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node) + val harnessFn = (th: chipyard.TestHarness) => { + peiTuples.map { case (port, edge, ios) => + val memSize = system.p(ExtMem).get.master.size + val lineSize = system.p(CacheBlockBytes) + val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) + mem.io.axi <> port + mem.io.clock := th.clock + mem.io.reset := th.reset + } + Nil } - Nil + Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) } }) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f29c5804f7..3d973a5e5b 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Config} class RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -205,6 +205,24 @@ class SmallSPIFlashRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) +class SimAXIRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ From 422e7fd4e6aadba94016be3a0b8f3fa0156ac2cd Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 26 May 2020 13:36:13 -0700 Subject: [PATCH 128/153] Bump hammer for last pre-merge fixes, update make target names --- vlsi/Makefile | 1 + vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- vlsi/power.mk | 8 ++++---- vlsi/sim.mk | 16 ++++++++-------- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 4c637fdba1..cd2d3d913a 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -179,6 +179,7 @@ ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif +#TODO: remove filter-out once PR#572 is merged $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) mkdir -p $(dir $@) echo "sim.inputs:" > $@ diff --git a/vlsi/hammer b/vlsi/hammer index d5b522ad1a..c917e9386f 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit d5b522ad1aace2a534c677bdca7b16f473efe217 +Subproject commit c917e9386f1005bd5307bd45acd58f4a5fe27aab diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index cf2304c211..427e5ca305 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit cf2304c21166cea140cc8e039824feeb51c89e0d +Subproject commit 427e5ca3057dd56ab2282a1ec5e45e912dffd7fb diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index 451e072193..b76ed57f2a 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit 451e072193f13f4a25cfa891426a52dbd7556c03 +Subproject commit b76ed57f2ab2fa43dfe58d0f5c9a4d4748bf59c1 diff --git a/vlsi/power.mk b/vlsi/power.mk index f394ced738..d1c56e2c7a 100644 --- a/vlsi/power.mk +++ b/vlsi/power.mk @@ -1,6 +1,6 @@ .PHONY: $(POWER_CONF) -power: $(POWER_CONF) sim-par -power: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -redo-power: $(POWER_CONF) -redo-power: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) +power-par: $(POWER_CONF) sim-par +power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) +redo-power-par: $(POWER_CONF) +redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) $(OBJ_DIR)/power-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 71b05ae780..6abd799592 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -1,9 +1,9 @@ .PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) # Update hammer top-level sim targets to include our generated sim configs -redo-sim: $(SIM_CONF) -redo-sim: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) -redo-sim-debug: $(SIM_DEBUG_CONF) redo-sim -redo-sim-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +redo-sim-rtl: $(SIM_CONF) +redo-sim-rtl: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-rtl-debug: $(SIM_DEBUG_CONF) redo-sim-rtl +redo-sim-rtl-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-syn: $(SIM_CONF) redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) @@ -17,10 +17,10 @@ redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-par-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug redo-sim-par-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF) -sim: $(SIM_CONF) -sim: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) -sim-debug: $(SIM_DEBUG_CONF) sim -sim-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +sim-rtl: $(SIM_CONF) +sim-rtl: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-rtl-debug: $(SIM_DEBUG_CONF) sim-rtl +sim-rtl-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) $(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) sim-syn: $(SIM_CONF) From d1875224400e70c39e619859f30d8d3184f82515 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 26 May 2020 15:51:00 -0700 Subject: [PATCH 129/153] Bump hammer post merge --- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vlsi/hammer b/vlsi/hammer index c917e9386f..9d83bbadc0 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit c917e9386f1005bd5307bd45acd58f4a5fe27aab +Subproject commit 9d83bbadc0caaa7f81b4929c4e32333fc5a8d900 diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 427e5ca305..f644138bab 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 427e5ca3057dd56ab2282a1ec5e45e912dffd7fb +Subproject commit f644138bab11075f267a3f1d72108da13c8a05ab diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index b76ed57f2a..ef163445ee 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit b76ed57f2ab2fa43dfe58d0f5c9a4d4748bf59c1 +Subproject commit ef163445eec6362fa6a9bf6be0bd18a5d36c707e From e6984e412b136e9a5b9fea6a088045c15a03180e Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Tue, 26 May 2020 23:00:37 +0000 Subject: [PATCH 130/153] Use Chain for dsptools example. Rename examples, bump dsptools to master, and incorporate feedback. --- .circleci/config.yml | 28 +++++----- .circleci/defaults.sh | 4 +- .circleci/run-tests.sh | 8 +-- docs/Customization/Dsptools-Blocks.rst | 26 +++++----- .../chipyard/src/main/scala/DigitalTop.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 8 +-- .../scala/example/dsptools/DspBlocks.scala | 52 ++++++++++++------- .../scala/example/dsptools/GenericFIR.scala | 31 +++++------ .../dsptools/StreamingPassthrough.scala | 28 ++++------ scripts/tutorial-patches/build.sbt.patch | 8 +-- tests/Makefile | 2 +- tests/{fir.c => streaming-fir.c} | 0 ...{passthrough.c => streaming-passthrough.c} | 0 tools/dsptools | 2 +- 14 files changed, 103 insertions(+), 96 deletions(-) rename tests/{fir.c => streaming-fir.c} (100%) rename tests/{passthrough.c => streaming-passthrough.c} (100%) diff --git a/.circleci/config.yml b/.circleci/config.yml index 1d205ee971..ab7006e12f 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -204,16 +204,16 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-sha3" - prepare-chipyard-fir: + prepare-chipyard-streaming-fir: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-fir" - prepare-chipyard-passthrough: + project-key: "chipyard-streaming-fir" + prepare-chipyard-streaming-passthrough: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-passthrough" + project-key: "chipyard-streaming-passthrough" prepare-chipyard-hetero: executor: main-env steps: @@ -297,16 +297,16 @@ jobs: steps: - run-tests: project-key: "chipyard-sha3" - chipyard-fir-run-tests: + chipyard-streaming-fir-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-fir" - chipyard-passthrough-run-tests: + project-key: "chipyard-streaming-fir" + chipyard-streaming-passthrough-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-passthrough" + project-key: "chipyard-streaming-passthrough" chipyard-hetero-run-tests: executor: main-env steps: @@ -459,12 +459,12 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-chipyard-fir: + - prepare-chipyard-streaming-fir: requires: - install-riscv-toolchain - install-verilator - - prepare-chipyard-passthrough: + - prepare-chipyard-streaming-passthrough: requires: - install-riscv-toolchain - install-verilator @@ -555,13 +555,13 @@ workflows: requires: - prepare-chipyard-sha3 - - chipyard-fir-run-tests: + - chipyard-streaming-fir-run-tests: requires: - - prepare-chipyard-fir + - prepare-chipyard-streaming-fir - - chipyard-passthrough-run-tests: + - chipyard-streaming-passthrough-run-tests: requires: - - prepare-chipyard-passthrough + - prepare-chipyard-streaming-passthrough - chipyard-hetero-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 6225ad9571..dcdd1e7bfd 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -46,8 +46,8 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim declare -A mapping mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" -mapping["chipyard-fir"]="SUB_PROJECT=chipyard CONFIG=FIRRocketConfig" -mapping["chipyard-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig" +mapping["chipyard-streaming-fir"]="SUB_PROJECT=chipyard CONFIG=StreamingFIRRocketConfig" +mapping["chipyard-streaming-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig" mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index f319880b34..1dc67b1680 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -62,13 +62,13 @@ case $1 in (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv ;; - chipyard-passthrough) + chipyard-streaming-passthrough) make -C $LOCAL_CHIPYARD_DIR/tests - $LOCAL_SIM_DIR/simulator-chipyard-StreamingPassthroughRocketConfig $LOCAL_CHIPYARD_DIR/tests/passthrough.riscv + $LOCAL_SIM_DIR/simulator-chipyard-StreamingPassthroughRocketConfig $LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv ;; - chipyard-fir) + chipyard-streaming-fir) make -C $LOCAL_CHIPYARD_DIR/tests - $LOCAL_SIM_DIR/simulator-chipyard-FIRRocketConfig $LOCAL_CHIPYARD_DIR/tests/fir.riscv + $LOCAL_SIM_DIR/simulator-chipyard-StreamingFIRRocketConfig $LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv ;; chipyard-spiflashread) make -C $LOCAL_CHIPYARD_DIR/tests diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index ebebd12b4f..8f8d2d2d55 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -15,8 +15,8 @@ A ``DspBlock`` is the basic unit of signal processing functionality that can be It has a AXI4-stream interface and an optional memory interface. The idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case the streaming interfaces are connected serially into a pipeline, and a bus is instatiated and connected to every block with a memory interface. - -This project has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. + +Chipyard has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. @@ -49,7 +49,7 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an Connecting DspBlock by TileLink ------------------------------- -With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. +With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala @@ -69,8 +69,8 @@ As in the previous MMIO example, we use a cake pattern to hook up our module to .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala - :start-after: DOC include start: CanHavePeripheryFIR chisel - :end-before: DOC include end: CanHavePeripheryFIR chisel + :start-after: DOC include start: CanHavePeripheryStreamingFIR chisel + :end-before: DOC include end: CanHavePeripheryStreamingFIR chisel Note that this is the point at which we decide the datatype for our FIR. @@ -90,29 +90,29 @@ Finally, we create the configuration class in ``generators/chipyard/src/main/sca .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala - :start-after: DOC include start: WithFIR - :end-before: DOC include end: WithFIR + :start-after: DOC include start: WithStreamingFIR + :end-before: DOC include end: WithStreamingFIR .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala - :start-after: DOC include start: FIRRocketConfig - :end-before: DOC include end: FIRRocketConfig + :start-after: DOC include start: StreamingFIRRocketConfig + :end-before: DOC include end: StreamingFIRRocketConfig FIR Testing ----------- -We can now test that the FIR is working. The test program is found in ``tests/fir.c``. +We can now test that the FIR is working. The test program is found in ``tests/streaming-fir.c``. -.. literalinclude:: ../../tests/fir.c +.. literalinclude:: ../../tests/streaming-fir.c :language: c The test feed a series of values into the fir and compares the output to a golden model of computation. The base of the module's MMIO write region is at 0x2000 and the base of the read region is at 0x2100 by default. -Compiling this program with ``make`` produces a ``fir.riscv`` executable. +Compiling this program with ``make`` produces a ``streaming-fir.riscv`` executable. Now we can run our simulation. .. code-block:: shell cd sims/verilator - make CONFIG=GCDTLRocketConfig BINARY=../../tests/fir.riscv run-binary + make CONFIG=StreamingFIRRocketConfig BINARY=../../tests/streaming-fir.riscv run-binary diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 7db9f7f3d6..ae363539a2 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -23,7 +23,7 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the DSPTools FIR example widget + with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 76ed912f90..0555966218 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -427,7 +427,7 @@ class RingSystemBusRocketConfig extends Config( // DOC include end: RingSystemBusRocket class StreamingPassthroughRocketConfig extends Config( - new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough + new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -445,9 +445,9 @@ class StreamingPassthroughRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include start: FIRRocketConfig -class FIRRocketConfig extends Config ( - new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR +// DOC include start: StreamingFIRRocketConfig +class StreamingFIRRocketConfig extends Config ( + new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithBlackBoxSimMem ++ diff --git a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala index ad4c585ebf..b51e2223bb 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala @@ -18,11 +18,11 @@ import freechips.rocketchip.subsystem._ * @param streamParameters parameters for the stream node * @param p */ -abstract class WriteQueue +abstract class WriteQueue[D, U, E, O, B <: Data] ( - val depth: Int = 8, + val depth: Int, val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters() -)(implicit p: Parameters) extends LazyModule with HasCSR { +)(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { // stream node, output only val streamNode = AXI4StreamMasterNode(streamParameters) @@ -58,12 +58,10 @@ abstract class WriteQueue * @param beatBytes beatBytes of TL interface * @param p */ -class TLWriteQueue -( - depth: Int = 8, - csrAddress: AddressSet = AddressSet(0x2000, 0xff), - beatBytes: Int = 8, -)(implicit p: Parameters) extends WriteQueue(depth) with TLHasCSR { +class TLWriteQueue (depth: Int, csrAddress: AddressSet, beatBytes: Int) +(implicit p: Parameters) extends WriteQueue[ + TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle +](depth) with TLHasCSR { val devname = "tlQueueIn" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { @@ -76,6 +74,17 @@ class TLWriteQueue override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) } +object TLWriteQueue { + def apply( + depth: Int = 8, + csrAddress: AddressSet = AddressSet(0x2000, 0xff), + beatBytes: Int = 8, + )(implicit p: Parameters) = { + val writeQueue = LazyModule(new TLWriteQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) + writeQueue + } +} + /** * The streaming interface adds elements into the queue. * The memory interface can read elements out of the queue. @@ -83,11 +92,11 @@ class TLWriteQueue * @param streamParameters parameters for the stream node * @param p */ -abstract class ReadQueue +abstract class ReadQueue[D, U, E, O, B <: Data] ( - val depth: Int = 8, + val depth: Int, val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters() -)(implicit p: Parameters) extends LazyModule with HasCSR { +)(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { val streamNode = AXI4StreamSlaveNode(streamParameters) lazy val module = new LazyModuleImp(this) { @@ -126,12 +135,10 @@ abstract class ReadQueue * @param beatBytes beatBytes of TL interface * @param p */ -class TLReadQueue -( - depth: Int = 8, - csrAddress: AddressSet = AddressSet(0x2100, 0xff), - beatBytes: Int = 8 -)(implicit p: Parameters) extends ReadQueue(depth) with TLHasCSR { +class TLReadQueue( depth: Int, csrAddress: AddressSet, beatBytes: Int) +(implicit p: Parameters) extends ReadQueue[ + TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle +](depth) with TLHasCSR { val devname = "tlQueueOut" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { @@ -142,5 +149,14 @@ class TLReadQueue } // make diplomatic TL node for regmap override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) +} +object TLReadQueue { + def apply( + depth: Int = 8, + csrAddress: AddressSet = AddressSet(0x2100, 0xff), + beatBytes: Int = 8)(implicit p: Parameters) = { + val readQueue = LazyModule(new TLReadQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) + readQueue + } } diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index a2d2ad0509..e0041192d4 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -188,30 +188,27 @@ GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEd // DOC include start: TLGenericFIRChain chisel class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters) - extends LazyModule { - val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))) - val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs)) - val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))) - - // connect streamNodes of queues and FIR - readQueue.streamNode := fir.streamNode := writeQueue.streamNode - - lazy val module = new LazyModuleImp(this) -} + extends TLChain(Seq( + TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_), + { implicit p: Parameters => + val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs)) + fir + }, + TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_) + )) // DOC include end: TLGenericFIRChain chisel // DOC include start: CanHavePeripheryFIR chisel -trait CanHavePeripheryFIR extends BaseSubsystem { - val fir = p(GenericFIRKey) match { +trait CanHavePeripheryStreamingFIR extends BaseSubsystem { + val streamingFIR = p(GenericFIRKey) match { case Some(params) => { - val fir = LazyModule(new TLGenericFIRChain( + val streamingFIR = LazyModule(new TLGenericFIRChain( genIn = FixedPoint(8.W, 3.BP), genOut = FixedPoint(8.W, 3.BP), coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)), params = params)) - - pbus.toVariableWidthSlave(Some("firWrite")) { fir.writeQueue.mem.get } - pbus.toVariableWidthSlave(Some("firRead")) { fir.readQueue.mem.get } + pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() } + Some(streamingFIR) } case None => None } @@ -222,7 +219,7 @@ trait CanHavePeripheryFIR extends BaseSubsystem { * Mixin to add FIR to rocket config */ // DOC include start: WithFIR -class WithFIR extends Config((site, here, up) => { +class WithStreamingFIR extends Config((site, here, up) => { case GenericFIRKey => Some(GenericFIRParams(depth = 8)) }) // DOC include end: WithFIR diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 87f977607e..923f12e2d2 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -121,27 +121,21 @@ with TLDspBlock * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal */ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughParams, proto: T)(implicit p: Parameters) - extends LazyModule { - // instantiate lazy modules - val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))) - val passthrough = LazyModule(new TLStreamingPassthroughBlock(proto)) - val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))) - - // connect streamNodes of queues and passthrough - readQueue.streamNode := passthrough.streamNode := writeQueue.streamNode - - lazy val module = new LazyModuleImp(this) -} + extends TLChain(Seq( + TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_), + { implicit p: Parameters => { + val streamingPassthrough = LazyModule(new TLStreamingPassthroughBlock(proto)) + streamingPassthrough + }}, + TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_) + )) trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { - val passthrough = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) - - pbus.toVariableWidthSlave(Some("passthroughWrite")) { passthrough.writeQueue.mem.get } - pbus.toVariableWidthSlave(Some("passthroughRead")) { passthrough.readQueue.mem.get } - - Some(passthrough) + val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) + pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() } + Some(streamingPassthroughChain) } case None => None } diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 40e773fe6e..6c1e3007ba 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,17 +1,17 @@ diff --git a/build.sbt b/build.sbt -index 0c4581f..ff0597c 100644 +index 5d642c1..56f6fda 100644 --- a/build.sbt +++ b/build.sbt -@@ -128,7 +128,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) +@@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches + dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, ariane, nvdla) .settings(commonSettings) - -@@ -155,9 +155,9 @@ lazy val ariane = (project in file("generators/ariane")) +@@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/tests/Makefile b/tests/Makefile index 299b7c02cf..ca8268eaf0 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -6,7 +6,7 @@ LDFLAGS= -static include libgloss.mk PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \ - passthrough fir nvdla spiflashread spiflashwrite + streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite spiflash.img: spiflash.py python3 $< diff --git a/tests/fir.c b/tests/streaming-fir.c similarity index 100% rename from tests/fir.c rename to tests/streaming-fir.c diff --git a/tests/passthrough.c b/tests/streaming-passthrough.c similarity index 100% rename from tests/passthrough.c rename to tests/streaming-passthrough.c diff --git a/tools/dsptools b/tools/dsptools index 7c40829718..211166e635 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 7c40829718592fc99b011d53595f01b00a3d68cf +Subproject commit 211166e635861fb1937828aee38c166baf0840b5 From 312700e9da1e0780f1b157a5bd14477beba5ac6d Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Tue, 26 May 2020 18:24:46 -0700 Subject: [PATCH 131/153] Fix some doc references --- .../src/main/scala/example/dsptools/GenericFIR.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index e0041192d4..ed16b25d1e 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -198,7 +198,7 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], para )) // DOC include end: TLGenericFIRChain chisel -// DOC include start: CanHavePeripheryFIR chisel +// DOC include start: CanHavePeripheryStreamingFIR chisel trait CanHavePeripheryStreamingFIR extends BaseSubsystem { val streamingFIR = p(GenericFIRKey) match { case Some(params) => { @@ -213,13 +213,13 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem { case None => None } } -// DOC include end: CanHavePeripheryFIR chisel +// DOC include end: CanHavePeripheryStreamingFIR chisel /** * Mixin to add FIR to rocket config */ -// DOC include start: WithFIR +// DOC include start: WithStreamingFIR class WithStreamingFIR extends Config((site, here, up) => { case GenericFIRKey => Some(GenericFIRParams(depth = 8)) }) -// DOC include end: WithFIR +// DOC include end: WithStreamingFIR From cdcaf5c57471f59f5e430e65209038fb2aafe7ee Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Tue, 26 May 2020 22:29:50 -0700 Subject: [PATCH 132/153] Missed an include end --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 0555966218..b1001c596a 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -464,7 +464,7 @@ class StreamingFIRRocketConfig extends Config ( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include end: FIRRocketConfig +// DOC include end: StreamingFIRRocketConfig class SmallNVDLARocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ From b5a067b9553fe75371603a1c5c4ead83327079a5 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 27 May 2020 07:57:25 -0700 Subject: [PATCH 133/153] [skip ci] Update comment on SimAXIMem --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 3d973a5e5b..58fefd460d 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -208,7 +208,7 @@ class SmallSPIFlashRocketConfig extends Config( class SimAXIRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ From 7e0e4555f92c57338391747dc48e48c6b9ec1ac5 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 27 May 2020 10:50:53 -0700 Subject: [PATCH 134/153] Remove redundancy in flags after merge --- vcs.mk | 3 --- vlsi/Makefile | 1 - 2 files changed, 4 deletions(-) diff --git a/vcs.mk b/vcs.mk index 5851e98caa..96cd0636f6 100644 --- a/vcs.mk +++ b/vcs.mk @@ -1,6 +1,3 @@ -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd CLOCK_PERIOD ?= 1.0 diff --git a/vlsi/Makefile b/vlsi/Makefile index cd2d3d913a..668138710b 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -124,7 +124,6 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags:" >> $@ - echo " - '+max-cycles=$(timeout_cycles)'" >> $@ for x in $(SIM_FLAGS); do \ echo ' - "'$$x'"' >> $@; \ done From b67c58ed1514317a14728b2520e78a6866263fe4 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 27 May 2020 11:07:41 -0700 Subject: [PATCH 135/153] ChipTop is now synthesizeable again :tada: --- vlsi/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 668138710b..a724f6f1b8 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -178,7 +178,6 @@ ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif -#TODO: remove filter-out once PR#572 is merged $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) mkdir -p $(dir $@) echo "sim.inputs:" > $@ @@ -190,7 +189,7 @@ $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(VLSI_RTL) $(filter-out %SimDRAM.v,$(filter-out %.cc,$(shell cat $(VLSI_BB)))); do \ + for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \ echo ' - "'$$x'"' >> $@; \ done From 4e696b6a0a16bd50863a6205e17f6d656017ca9c Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Wed, 27 May 2020 11:21:39 -0700 Subject: [PATCH 136/153] Add block diagram, clean up docs more --- docs/Customization/Dsptools-Blocks.rst | 29 ++++++++++++++--------- docs/_static/images/fir-block-diagram.svg | 1 + 2 files changed, 19 insertions(+), 11 deletions(-) create mode 100644 docs/_static/images/fir-block-diagram.svg diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 8f8d2d2d55..bdf68fc1c2 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -6,7 +6,7 @@ Dsptools is a Chisel library that aids in writing custom signal processing accel * Structures for packaging DSP blocks and integrating them into a rocketchip-based SoC. * Test harnesses for testing DSP circuits, as well as VIP-style drivers and monitors for DSP blocks. -The `Dsptools `_ repository has more documentation. +The `Dsptools repository `_ has more documentation. Dsptools Blocks @@ -16,11 +16,16 @@ It has a AXI4-stream interface and an optional memory interface. The idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case the streaming interfaces are connected serially into a pipeline, and a bus is instatiated and connected to every block with a memory interface. -Chipyard has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. +Chipyard has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock`` [#]_. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. -For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. +.. figure:: ../_static/images/fir-block-diagram.svg + :align: center + :alt: Block diagram showing how FIR is integrated with rocket. + :width: 400px -The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type generic, which means that they can be instantiated for any datatype that implements ``Ring`` operations per the specifications on ``T``. +For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral as shown in the figure above. The full code can be found in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. + +The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type-generic, which means that they can be instantiated for any datatype ``T`` that implements ``Ring`` operations (e.g. addition, multiplication, identities). .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala @@ -32,10 +37,10 @@ The module ``GenericFIR`` is the overall wrapper of our FIR module. This module :start-after: DOC include start: GenericFIRDirectCell chisel :end-before: DOC include end: GenericFIRDirectCell chisel -Creating a DspBlock Extension ------------------------------ +Creating a DspBlock +------------------- -The first step in attaching the FIR filter as a MMIO peripheral is to create an abstract extension of ``DspBlock`` the wraps around the ``GenericFIR`` module. The main steps of this process are as follows. +The first step in attaching the FIR filter as a MMIO peripheral is to create an abstract subclass of ``DspBlock`` the wraps around the ``GenericFIR`` module. Streaming outputs and inputs are packed and unpacked into ``UInt`` s. If there were control signals, this is where they'd go from raw IOs to memory mapped. The main steps of this process are as follows. 1. Instantiate a ``GenericFIR`` within ``GenericFIRBlock``. 2. Attach the ready and valid signals from the in and out connections. @@ -47,6 +52,8 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an :start-after: DOC include start: GenericFIRBlock chisel :end-before: DOC include end: GenericFIRBlock chisel +Note that at this point the ``GenericFIRBlock`` does not have a type of memory interface specified. This abstract class can be used to create different flavors that use AXI-4, TileLink, AHB, or whatever other memory interface you like like. + Connecting DspBlock by TileLink ------------------------------- With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. @@ -56,7 +63,7 @@ With these classes implemented, you can begin to construct the chain by extendin :start-after: DOC include start: TLGenericFIRBlock chisel :end-before: DOC include end: TLGenericFIRBlock chisel -We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala``. Inside our chain, we construct an instance of each queue as well as our ``TLGenericFIRBlock``. We then take the ``steamnode`` from each module and wire them all together to link the chain. +We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala``. The chain is created by passing a list of factory functions to the constructor of ``TLChain``. The constructor then automatically instantiates these ``DspBlocks``, connects their stream nodes in order, creates a bus, and connects any ``DspBlocks`` that have memory interfaces to the bus. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala @@ -72,9 +79,7 @@ As in the previous MMIO example, we use a cake pattern to hook up our module to :start-after: DOC include start: CanHavePeripheryStreamingFIR chisel :end-before: DOC include end: CanHavePeripheryStreamingFIR chisel -Note that this is the point at which we decide the datatype for our FIR. - -Our module does not need to be connected to concrete IOs or wires, so we do not need to create a concrete trait. +Note that this is the point at which we decide the datatype for our FIR. You could create different configs that use different types for the FIR, for example a config that instantiates a complex-valued FIR filter. Constructing the Top and Config ------------------------------- @@ -116,3 +121,5 @@ Now we can run our simulation. cd sims/verilator make CONFIG=StreamingFIRRocketConfig BINARY=../../tests/streaming-fir.riscv run-binary + +.. [#] ``ReadQueue`` and ``WriteQueue`` are good illustrations of how to write a ``DspBlock`` and how they can be integrated into rocket, but in a real design a DMA engine would be preferred. ``ReadQueue`` will stall the processor if you try to read an empty queue, and ``WriteQueue`` will stall if you try to write to a full queue, which a DMA engine can more elegantly avoid. Furthermore, a DMA engine can do the work of moving data, freeing the processor to do other useful work (or sleep). diff --git a/docs/_static/images/fir-block-diagram.svg b/docs/_static/images/fir-block-diagram.svg new file mode 100644 index 0000000000..c56379e5cd --- /dev/null +++ b/docs/_static/images/fir-block-diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file From e712f5f51ef5166fe1e588b69f11e416fc5717c2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 27 May 2020 22:05:09 -0700 Subject: [PATCH 137/153] bump boom/firesim/firemarshal/spec2017 --- generators/boom | 2 +- sims/firesim | 2 +- software/firemarshal | 2 +- software/spec2017 | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/boom b/generators/boom index f0caca8d6b..f1a20b1b3e 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f0caca8d6bc98f3ccc7d8b9391b7f7c8efb2f879 +Subproject commit f1a20b1b3ea7f47a4bb530d4fc44091519249731 diff --git a/sims/firesim b/sims/firesim index a6911eca08..3143253dda 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit a6911eca084608965c00d79931d208188e70d8cb +Subproject commit 3143253dda0292643f2953087638ae43e98559f4 diff --git a/software/firemarshal b/software/firemarshal index a40f0252c4..141a3d366f 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit a40f0252c4e426e794313ba02b0015e5f22133f4 +Subproject commit 141a3d366f4ff9ce245192c23e5cc2ad8897bc19 diff --git a/software/spec2017 b/software/spec2017 index a4333f243c..8f2812bebc 160000 --- a/software/spec2017 +++ b/software/spec2017 @@ -1 +1 @@ -Subproject commit a4333f243cef6bfff08bcbb08f3ec467b4c720d0 +Subproject commit 8f2812bebc15ae36f15cb8b80f4b50aa7d342b46 From 136315f29787f982e7ae96fed8f50d528c8101fb Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 27 May 2020 23:58:06 -0700 Subject: [PATCH 138/153] bump esp-isa-sim to gemmini v0.3 --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 3c930b4031..13384cac1e 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 3c930b403140ac0cd1fc5578a21998f6875459c6 +Subproject commit 13384cac1e54828200067ff890f564a505a4ebb3 From 9fad8aa8ba090c22c85dbf6cefcd1ceb190984b8 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 28 May 2020 00:09:11 -0700 Subject: [PATCH 139/153] bump gemmini v0.3 --- docs/Generators/Gemmini.rst | 10 +++++++++- generators/gemmini | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index b2257b1f0a..c8618d4eb9 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -36,12 +36,18 @@ Major parameters of interest include: * Scratchpad and accumulator memory parameters (``sp_banks``, ``sp_capacity``, ``acc_capacity``): Determine the properties of the Gemmini scratchpad memory: overall capacity of the scratchpad or accumulators (in KiB), and the number of banks the scratchpad is divided into. -* Type parameters (``inputType``, ``outputType``, ``accType``): Determine the data-types flowing through different parts of a Gemmini accelerator. For example, ``inputType`` may be an 8-bit fixed-point number, while ``accType``, which determines the type of partial accumulations in a matrix multiplication, may be a 32-bit integer. ``outputType`` only determines the type of the data passed between two processing elements (PEs); for example, an 8-bit multiplication may produce a 16-bit result which must be shared between PEs in a systolic array. +* Type parameters (``inputType``, ``outputType``, ``accType``): Determine the data-types flowing through different parts of a Gemmini accelerator. For example, ``inputType`` may be an 8-bit fixed-point number, while ``accType``, which determines the type of partial accumulations in a matrix multiplication, may be a 32-bit integer. ``outputType`` only determines the type of the data passed between two processing elements (PEs); for example, an 8-bit multiplication may produce a 16-bit result which must be shared between PEs in a systolic array. If your datatype is a floating-point number, then you might also want to change the ``pe_latency`` parameter, which specifies how many shift registers to add inside the PEs. This might be necessary if your datatype cannot complete a multiply-accumulate operation within a single cycle. * Access-execute queue parameters (``ld_queue_length``, ``st_queue_length``, ``ex_queue_length``, ``rob_entries``): To implement access-execute decoupling, a Gemmini accelerator has a load instruction queue, a store instruction queue, and an execute instruction queue. The relative sizes of these queue determine the level of access-execute decoupling. Gemmini also implements a reorder buffer (ROB) - the number of entries in the ROB determines possible dependency management limitations. * DMA parameters (``dma_maxbytes``, ``dma_buswidth``, ``mem_pipeline``): Gemmini implements a DMA to move data from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory. The size of these DMA transactions is determined by the DMA parameters. These DMA parameters are tightly coupled with Rocket Chip SoC system parameters: in particular ``dma_buswidth`` is associated with the ``SystemBusKey`` ``beatBytes`` parameter, and ``dma_maxbytes`` is associated with ``cacheblockbytes`` Rocket Chip parameters. +There are also optional features, which can be either enabled or left out of Gemmini at elaboration-time. For example: + +Scaling during "move-in" operations (``mvin_scale_args``, ``mvin_scale_acc_args``): When data is being moved in from DRAM or main memory into Gemmini's local scratchpad memory, it can optionally be multiplied by a scaling factor. These parameters specify what the datatype of the scaling factor is, and how the scaling is actually done. If these are set to ``None``, then this optional feature will be disabled at elaboration time. If both the scratchpad inputs are accumulator inputs are to be scaled in the same say, then the ``mvin_scale_shared`` parameter can be set to ``true`` so that the multipliers and functional units are shared. + + + Gemmini Software ------------------ @@ -55,6 +61,8 @@ The ``software`` directory of the generator includes the aforementioned library The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` +Gemmini can also be used to run ONNX-specified neural-networks through a port of Microsoft's ONNX-Runtime framework. The port is included as the `onnxruntime-riscv`__ repository submoduled in the `software` directory. The port is under development, and usage documentation can be found `within its repository `__. + Build and Run Gemmini Tests ^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/generators/gemmini b/generators/gemmini index d6f36d37d1..9797e80404 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit d6f36d37d1e10b7fd514e6680b1eaea032cee628 +Subproject commit 9797e804044f93bb5b1f572952d1a83354701dbd From cd80c64a7270bbdf2263f41843ea88a7df1e3bc6 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 28 May 2020 00:59:19 -0700 Subject: [PATCH 140/153] abe nit --- docs/Generators/Gemmini.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index c8618d4eb9..c48daeda53 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -57,9 +57,9 @@ The ISA includes configuration instructions, data movement instructions (from ma Since Gemmini instructions are not exposed through the GNU binutils assembler, several C macros are provided in order to construct the instruction encodings to call these instructions. The Gemmini generator includes a C matrix multiplication library which wraps the calls to the custom Gemmini instructions. -The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/gemmini.h`` file. +The ``software`` directory of the generator (within the generator repository in ``generators/gemmini/software``) includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``generators/gemmini/software/gemmini-rocc-tests/include/gemmini.h`` file. -The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` +The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``generators/gemmini/software/gemmini-rocc-tests/include/gemmini_params.h`` Gemmini can also be used to run ONNX-specified neural-networks through a port of Microsoft's ONNX-Runtime framework. The port is included as the `onnxruntime-riscv`__ repository submoduled in the `software` directory. The port is under development, and usage documentation can be found `within its repository `__. From 930f03cf68ad66fedd7366f10c0bed3f0d84ba22 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 28 May 2020 12:54:19 -0700 Subject: [PATCH 141/153] Do not initialize gemmini's onnx-runtime --- generators/gemmini | 2 +- scripts/init-submodules-no-riscv-tools-nolog.sh | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 9797e80404..caaf781ec9 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 9797e804044f93bb5b1f572952d1a83354701dbd +Subproject commit caaf781ec9d69e45443e496046bc6ab439e3e54f diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 70b504b420..c645b38877 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -29,6 +29,7 @@ git config submodule.toolchains/qemu.update none # Don't automatically initialize generators with big submodules (e.g. linux source) git config submodule.generators/sha3.update none +git config submodule.generators/gemmini.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none @@ -51,11 +52,16 @@ git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update git config --unset submodule.generators/sha3.update +git config --unset submodule.generators/gemmini.update git config --unset submodule.software/firemarshal.update # Non-recursive clone to exclude riscv-linux git submodule update --init generators/sha3 +# Non-recursive clone to exclude gemmini-software +git submodule update --init generators/gemmini +git submodule update --init --recursive generators/gemmini/software/gemmini-rocc-tests + git config --unset submodule.sims/firesim.update # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim From bbc03f62358442cc1c632439f4e08f7d7a573a7e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 13:28:34 -0700 Subject: [PATCH 142/153] cleanup old folders in ci | add coursier cache export --- .circleci/build-toolchains.sh | 2 +- .circleci/clean-old-files.sh | 4 ++-- .circleci/defaults.sh | 9 ++++++--- .circleci/do-rtl-build.sh | 3 ++- .circleci/install-verilator.sh | 4 +++- .circleci/run-tests.sh | 6 +++--- 6 files changed, 17 insertions(+), 11 deletions(-) diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index b43d2eda6b..160b6f5a1d 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -14,5 +14,5 @@ if [ ! -d "$HOME/$1-install" ]; then cd $HOME # init all submodules including the tools - CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=2 $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 + CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=$CI_MAKE_NPROC $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 fi diff --git a/.circleci/clean-old-files.sh b/.circleci/clean-old-files.sh index 96fcf8d79b..5824c4b74f 100755 --- a/.circleci/clean-old-files.sh +++ b/.circleci/clean-old-files.sh @@ -1,6 +1,6 @@ #!/bin/bash -# clean directories that are older than 30 days +# clean directories that are older than 14 days # argument is used as the directory to look in age () { @@ -20,7 +20,7 @@ age () { for d in $1/*/ ; do DIR_AGE="$(age $d)" - if [ $DIR_AGE -ge 30 ]; then + if [ $DIR_AGE -ge 14 ]; then echo "Deleting $d since is it $DIR_AGE old" rm -rf $d else diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index d9699df8e5..cdb2c37bbb 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -18,13 +18,16 @@ clean () { } # make parallelism -NPROC=8 +CI_MAKE_NPROC=8 +# chosen based on a 24c system shared with 1 other project +REMOTE_MAKE_NPROC=4 # verilator version VERILATOR_VERSION=v4.034 # remote variables -REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB +REMOTE_PREFIX=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH +REMOTE_WORK_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-$CIRCLE_JOB REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard @@ -32,7 +35,7 @@ REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" -REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install +REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) LOCAL_CHECKOUT_DIR=$HOME/project diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 52c920f5ad..54996f54ac 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -58,7 +58,8 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - make -j$NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ + make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build diff --git a/.circleci/install-verilator.sh b/.circleci/install-verilator.sh index 86d1ae045b..2170768ab8 100755 --- a/.circleci/install-verilator.sh +++ b/.circleci/install-verilator.sh @@ -9,7 +9,9 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh +# clean older directories (delete prior directories related to this branch also) run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR +run "rm -rf $REMOTE_PREFIX*" # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" @@ -20,4 +22,4 @@ run "git clone http://git.veripool.org/git/verilator $REMOTE_VERILATOR_DIR; \ autoconf; \ export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; \ ./configure; \ - make -j$NPROC;" + make -j$REMOTE_MAKE_NPROC;" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 19a0e566c6..387f9b687c 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -10,11 +10,11 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh run_bmark () { - make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ + make run-bmark-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $@ } run_asm () { - make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ + make run-asm-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $@ } run_both () { @@ -45,7 +45,7 @@ case $1 in export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH - make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR ${mapping[$1]} + make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR ${mapping[$1]} ;; chipyard-gemmini) export RISCV=$LOCAL_ESP_DIR From 4972866b402ccd8429dfc8b347fc4a5d16ccbd23 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 13:50:19 -0700 Subject: [PATCH 143/153] add coursier cache to firesim/midas tests --- .circleci/run-firesim-scala-tests.sh | 1 + .circleci/run-midasexamples-tests.sh | 1 + 2 files changed, 2 insertions(+) diff --git a/.circleci/run-firesim-scala-tests.sh b/.circleci/run-firesim-scala-tests.sh index 3e2bb87f76..8080a484c0 100755 --- a/.circleci/run-firesim-scala-tests.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -48,4 +48,5 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export FIRESIM_ENV_SOURCED=1; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}" diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh index 092d011ee9..fecfcab2de 100755 --- a/.circleci/run-midasexamples-tests.sh +++ b/.circleci/run-midasexamples-tests.sh @@ -46,4 +46,5 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export FIRESIM_ENV_SOURCED=1; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" TARGET_PROJECT=midasexamples test" From 96e253feb51416f1365314233c6f17d8399e16d4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 14:20:04 -0700 Subject: [PATCH 144/153] documentation fix --- docs/Generators/Gemmini.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index c48daeda53..34fc728bea 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -61,7 +61,7 @@ The ``software`` directory of the generator (within the generator repository in The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``generators/gemmini/software/gemmini-rocc-tests/include/gemmini_params.h`` -Gemmini can also be used to run ONNX-specified neural-networks through a port of Microsoft's ONNX-Runtime framework. The port is included as the `onnxruntime-riscv`__ repository submoduled in the `software` directory. The port is under development, and usage documentation can be found `within its repository `__. +Gemmini can also be used to run ONNX-specified neural-networks through a port of Microsoft's ONNX-Runtime framework. The port is included as the `onnxruntime-riscv `__ repository submoduled in the `software` directory. The port is under development, and usage documentation can be found `within its repository `__. Build and Run Gemmini Tests ^^^^^^^^^^^^^^^^^^^^^^^^^^^ From a06c90cdac43d4ae422336cd659131f0c79c2504 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 15:43:52 -0700 Subject: [PATCH 145/153] fix submodule update --- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index c645b38877..d91e89b9b0 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -60,7 +60,7 @@ git submodule update --init generators/sha3 # Non-recursive clone to exclude gemmini-software git submodule update --init generators/gemmini -git submodule update --init --recursive generators/gemmini/software/gemmini-rocc-tests +git -C generators/gemmini/ submodule update --init --recursive software/gemmini-rocc-tests git config --unset submodule.sims/firesim.update # Minimal non-recursive clone to initialize sbt dependencies From 61f92cd102defe18275ecfc60696597c805f9c9d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 16:11:51 -0700 Subject: [PATCH 146/153] bump ariane/hwacha/sha3/testchipip/libgloss --- generators/ariane | 2 +- generators/hwacha | 2 +- generators/sha3 | 2 +- generators/testchipip | 2 +- toolchains/libgloss | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/ariane b/generators/ariane index d914fc8f03..651134f3c4 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit d914fc8f0320ba5b087d515b25baf98959b0facb +Subproject commit 651134f3c43ff8c0fa55a0f65faeb12b9500fcfa diff --git a/generators/hwacha b/generators/hwacha index 2706502daf..a989b69759 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 2706502daf862c9a7a39126eb7e7209eaf984f76 +Subproject commit a989b69759137802b4c39e9ddebb90427455fb79 diff --git a/generators/sha3 b/generators/sha3 index cec8db9d6b..a94dcf3ae0 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit cec8db9d6b3a602771cae63eaf6705baa3492f6a +Subproject commit a94dcf3ae0a0440aade96bcdaa4da685352ae704 diff --git a/generators/testchipip b/generators/testchipip index b02bd8eaca..4b15061b6f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b02bd8eacaffe425811bd3fd8ef7d30772ae3cb7 +Subproject commit 4b15061b6fe77f6793603f799751f1f988144ef7 diff --git a/toolchains/libgloss b/toolchains/libgloss index a88e50f2e1..04b249764b 160000 --- a/toolchains/libgloss +++ b/toolchains/libgloss @@ -1 +1 @@ -Subproject commit a88e50f2e1b0411e0a7d5e5c29d5b40117560912 +Subproject commit 04b249764b1bc0b784b9f7ff422084f4b53a07ef From 4e09d91faa0f5742bdb496481cd0dce102036cf9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 16:27:58 -0700 Subject: [PATCH 147/153] bump firemarshal/hammer-mentor-plugins | add submodules to check script --- .circleci/check-commit.sh | 11 ++++++++--- software/firemarshal | 2 +- vlsi/hammer-mentor-plugins | 2 +- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 3c57d64c34..98c770ad24 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("boom" "hwacha" "icenet" "sha3" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip" "gemmini") +submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then @@ -80,12 +80,12 @@ dir="toolchains" branches=("master") search -submodules=("spec2017" "coremark") +submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017") dir="software" branches=("master") search -submodules=("axe" "barstools" "torture" "dsptools" "chisel-testers" "treadle" "firrtl-interpreter") +submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "firrtl-interpreter" "torture" "treadle") dir="tools" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then @@ -95,6 +95,11 @@ else fi search +submodules=("dromajo-src") +dir="tools/dromajo" +branches=("master") +search + submodules=("firesim") dir="sims" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] diff --git a/software/firemarshal b/software/firemarshal index 141a3d366f..6c6a08f979 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 141a3d366f4ff9ce245192c23e5cc2ad8897bc19 +Subproject commit 6c6a08f9790c660823e9f858ca87f93b2502fa44 diff --git a/vlsi/hammer-mentor-plugins b/vlsi/hammer-mentor-plugins index 33ccdccf2c..67f57f1200 160000 --- a/vlsi/hammer-mentor-plugins +++ b/vlsi/hammer-mentor-plugins @@ -1 +1 @@ -Subproject commit 33ccdccf2c04a26cceeeb03a29b9cfad38908328 +Subproject commit 67f57f120031e8c23d3d165f56c3a3c7a4064aa4 From a9c4983c71bbb39bf2db1a6604f05e41d2339e5b Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 29 May 2020 08:11:55 -0700 Subject: [PATCH 148/153] Add dramsim_lib as a dependency of hammer sims Fix small issues with hammer-sim dut name and flags. It would be cool to only build dramsim when our config includes dramsim but this matches the way the other simulators handle this in chipyard. We also strip out empty CC flags because hammer doesn't prune these. Its unclear whether the hammer should handle this itself or not, if it eventually does we can remove this check. --- vlsi/Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index a724f6f1b8..7fbfcc2ca9 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -32,6 +32,7 @@ ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= example.yml HAMMER_EXEC ?= ./example-vlsi VLSI_TOP ?= $(TOP) +VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build ifneq ($(CUSTOM_VLOG), ) OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) @@ -96,7 +97,7 @@ SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk -$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) +$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) mkdir -p $(dir $@) echo "sim.inputs:" > $@ echo " top_module: $(VLSI_TOP)" >> $@ @@ -117,7 +118,7 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " defines_meta: 'append'" >> $@ echo " compiler_opts:" >> $@ - for x in $(filter-out -CC,$(VCS_CC_OPTS)); do \ + for x in $(filter-out "",$(filter-out -CC,$(VCS_CC_OPTS))); do \ echo ' - "'$$x'"' >> $@; \ done echo " compiler_opts_meta: 'append'" >> $@ @@ -129,7 +130,7 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " execution_flags_meta: 'append'" >> $@ echo " benchmarks: ['$(BINARY)']" >> $@ - echo " tb_dut: 'testHarness.top'" >> $@ + echo " tb_dut: 'testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) @@ -152,11 +153,10 @@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_comm POWER_CONF = $(OBJ_DIR)/power-inputs.yml include $(vlsi_dir)/power.mk -LOWER_VLSI_TOP = $(shell echo $(VLSI_TOP) | tr A-Z a-z) $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "power.inputs:" > $@ - echo " tb_dut: 'testHarness/$(LOWER_VLSI_TOP)'" >> $@ + echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ echo " saifs: [" >> $@ echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@ From e4037303150641ce98cbc890df59db1a98b5dfc6 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 29 May 2020 15:13:37 -0700 Subject: [PATCH 149/153] More fixes for post-syn/par hammer simulations Symlink dramsim2 into hammer-sims rundirs update some hammer generated makefile targets that were missed before bump barstools to get an iocell fix --- tools/barstools | 2 +- vlsi/Makefile | 2 ++ vlsi/power.mk | 2 +- vlsi/sim.mk | 8 +++++++- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/tools/barstools b/tools/barstools index c4e5f66c5e..b1c1f01c90 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit c4e5f66c5e795c744b7f3be2780f7f2bb15e9e23 +Subproject commit b1c1f01c906dbc38183b993fd05ac2889b2cc8e4 diff --git a/vlsi/Makefile b/vlsi/Makefile index 7fbfcc2ca9..b7e76c507d 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -99,6 +99,8 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) mkdir -p $(dir $@) + mkdir -p $(OBJ_DIR)/$(HAMMER_SIM_RUN_DIR)/$(notdir $(BINARY)) + ln -sf $(base_dir)/generators/testchipip/src/main/resources/dramsim2_ini $(OBJ_DIR)/$(HAMMER_SIM_RUN_DIR)/$(notdir $(BINARY))/dramsim2_ini echo "sim.inputs:" > $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ diff --git a/vlsi/power.mk b/vlsi/power.mk index d1c56e2c7a..383da5f0dd 100644 --- a/vlsi/power.mk +++ b/vlsi/power.mk @@ -3,4 +3,4 @@ power-par: $(POWER_CONF) sim-par power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) redo-power-par: $(POWER_CONF) redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -$(OBJ_DIR)/power-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) +$(OBJ_DIR)/power-par-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 6abd799592..6de46a9026 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -2,16 +2,19 @@ # Update hammer top-level sim targets to include our generated sim configs redo-sim-rtl: $(SIM_CONF) redo-sim-rtl: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-rtl: override HAMMER_SIM_RUN_DIR = sim-rtl-rundir redo-sim-rtl-debug: $(SIM_DEBUG_CONF) redo-sim-rtl redo-sim-rtl-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-syn: $(SIM_CONF) redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-par: $(SIM_CONF) redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-par: override HAMMER_SIM_RUN_DIR = sim-par-rundir redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-par-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug @@ -19,18 +22,21 @@ redo-sim-par-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF) sim-rtl: $(SIM_CONF) sim-rtl: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-rtl: override HAMMER_SIM_RUN_DIR = sim-rtl-rundir sim-rtl-debug: $(SIM_DEBUG_CONF) sim-rtl sim-rtl-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) +$(OBJ_DIR)/sim-rtl-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) sim-syn: $(SIM_CONF) sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) $(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) sim-par: $(SIM_CONF) sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-par: override HAMMER_SIM_RUN_DIR = sim-par-rundir sim-par-debug: $(SIM_DEBUG_CONF) sim-par sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) sim-par-timing-debug: $(SIM_TIMING_CONF) sim-par-debug From 6301c116b99e429b4f9579ecf5812ba75fd2c1d3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 29 May 2020 16:14:59 -0700 Subject: [PATCH 150/153] bump boom ci | bump nvdla sw [ci skip] --- generators/boom | 2 +- software/nvdla-workload | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index f1a20b1b3e..d77c2c3ff6 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f1a20b1b3ea7f47a4bb530d4fc44091519249731 +Subproject commit d77c2c3ff648bd5b18a932aa9f6b64dead7e3476 diff --git a/software/nvdla-workload b/software/nvdla-workload index 88b09e0171..30290c3ed8 160000 --- a/software/nvdla-workload +++ b/software/nvdla-workload @@ -1 +1 @@ -Subproject commit 88b09e0171bdf6b3a77f711c2c8015dc727e460b +Subproject commit 30290c3ed8014577fa2ad234fa1b731a082299fb From 12d211add03847fe94496da46d5acd91a9cd21cb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 31 May 2020 13:33:55 -0700 Subject: [PATCH 151/153] add changelog for 1.3.0 release --- CHANGELOG.md | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index f9447b0e67..c81e80b433 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,64 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.3.0] - 2020-05-31 + +A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/500 + +### Added +* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem. (#480) +* A new BuildSystem key has been added, which by default builds DigitalTop (#480) +* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions). (#480) +* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation. (#480) +* CI now checks documentation changes (#485) +* Support FireSim multi-clock (#468) +* Allows make variables to be injected into build system (#499) +* Various documentation/comment updates (#511,#517,#518,#537,#533,#542,#570,#569) +* DSPTools documentation and example (#457, #568) +* Support for no UART configs (#536) +* Assemble firrtl-test.jar (#551) +* Add SPI flash configurations (#546) +* Add Dromajo + FireSim Dromajo simulation support (#523, #553, #560) +* NVDLA integration (#505, #559, #580) +* Add support for Hammer Sim (#512,#581,#580,#582) + +### Changed +* Bump FireSim to version 1.10 (#574) +* Bump BOOM to version 3.0 (#523, #574,#580) +* Bump Gemmini to version 0.3 (#575, #579) +* Bump SPEC17 workload (#504, #574) +* Bump Hwacha for fixes (#580) +* Bump SHA3 for Linux 5.7rc3 support (#580) +* Bump Rocket Chip to commit 1872f5d (including stage/phase compilation) (#503,#544) +* Bump FireMarshal to version 1.9.0 (#574) +* Chisel 3.3 and FIRRTL 1.3 (#503,#544) +* BuildTop now builds a ChipTop dut module in the TestHarness by default (#480) +* The default for the TOP make variable is now ChipTop (was Top) (#480) +* Top has been renamed to DigitalTop (#480) +* Bump libgloss (#508, #516, #580) +* The default version of Verilator has changed to v4.034 (#547). Since this release adds enhanced support for Verilog timescales, the build detects if Verilator v4.034 or newer is visible in the build environment and sets default timescale flags appropriately. +* Use Scalatests for FireSim CI (#528) +* Cleanup Ariane pre-processing (#505) +* Modify Issue Template to be more explicit (#557) +* FireChip uses Chipyard generator (#554) +* Have all non-synthesizeable constructs in test harness (#572) + +### Fixed +* Aligned esp-tools spike with Gemmini (#509) +* Fix debug rule in Verilator (#513) +* Clean up SBT HTTP warnings (#526,#549) +* Artefacts dropped in FireSim (#534) +* Working IceNet + TestChipIP Unit Tests (#525) +* Don't initialize non-existent Midas submodule (#552) +* Verilator now supports +permissive similar to VCS (#565) + +### Deprecated +* N/A + +### Removed +* N/A + + ## [1.2.0] - 2020-03-14 A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/418 @@ -59,7 +117,7 @@ A more detailed account of everything included is included in the dev to master * FireSim release 1.8.0 * FireMarshal release 1.8.0 * BOOM release 2.2.3 (PR #397) -* baremetal software toolchains, using libgloss and newlib instead of in-house syscalls. +* baremetal software toolchains, using libgloss and newlib instead of in-house syscalls. * Add toolchain specific `env.sh` (PR #304) * `run-binary`-like interface now dumps `.log` (stdout) and `.out` (stderr) files (PR #308) * Split the VLSI build dir on type of design (PR #331) From cb4ac2a1d3eb2cbf6fb89617edaa572d5510af6d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 31 May 2020 14:34:06 -0700 Subject: [PATCH 152/153] bump firesim to 1.10.0 and barstools | update changelog --- CHANGELOG.md | 3 ++- sims/firesim | 2 +- tools/barstools | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index c81e80b433..38ea7e6e08 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -24,7 +24,7 @@ A more detailed account of everything included is included in the dev to master * Add support for Hammer Sim (#512,#581,#580,#582) ### Changed -* Bump FireSim to version 1.10 (#574) +* Bump FireSim to version 1.10 (#574,#586) * Bump BOOM to version 3.0 (#523, #574,#580) * Bump Gemmini to version 0.3 (#575, #579) * Bump SPEC17 workload (#504, #574) @@ -52,6 +52,7 @@ A more detailed account of everything included is included in the dev to master * Working IceNet + TestChipIP Unit Tests (#525) * Don't initialize non-existent Midas submodule (#552) * Verilator now supports +permissive similar to VCS (#565) +* Fix direction of IOCell OE (#586) ### Deprecated * N/A diff --git a/sims/firesim b/sims/firesim index 3143253dda..c2d8e3a46e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3143253dda0292643f2953087638ae43e98559f4 +Subproject commit c2d8e3a46e59222e115a1fdaa7267592e1d3c503 diff --git a/tools/barstools b/tools/barstools index b1c1f01c90..7e6e19b8ad 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit b1c1f01c906dbc38183b993fd05ac2889b2cc8e4 +Subproject commit 7e6e19b8adf3b625b31b09173ecae5f634c83e1b From 5c3a7c136b21aed9bf1b591de861b08b6b0c35fb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 31 May 2020 23:20:38 -0700 Subject: [PATCH 153/153] [ci] remove midas-examples ci --- .circleci/config.yml | 13 -------- .circleci/run-midasexamples-tests.sh | 50 ---------------------------- CHANGELOG.md | 2 +- 3 files changed, 1 insertion(+), 64 deletions(-) delete mode 100755 .circleci/run-midasexamples-tests.sh diff --git a/.circleci/config.yml b/.circleci/config.yml index ab7006e12f..ab1236614a 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -379,14 +379,6 @@ jobs: project-key: "firesim-multiclock" run-script: "run-firesim-scala-tests.sh" timeout: "20m" - midasexamples-run-tests: - executor: main-env - steps: - - setup-tools - - run: - name: Run midasexamples tests - command: .circleci/run-midasexamples-tests.sh - no_output_timeout: 20m chipyard-ariane-run-tests: executor: main-env steps: @@ -541,11 +533,6 @@ workflows: # Run the respective tests - # Run midasexamples test - - midasexamples-run-tests: - requires: - - install-riscv-toolchain - # Run the example tests - chipyard-rocket-run-tests: requires: diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh deleted file mode 100755 index fecfcab2de..0000000000 --- a/.circleci/run-midasexamples-tests.sh +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/bash - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# call clean on exit -trap clean EXIT - -cd $LOCAL_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh - -# build libdromajo_cosim -make -C $LOCAL_CHIPYARD_DIR/tools/dromajo/dromajo-src/src - -cd sims/firesim/sim/midas - -# set stricthostkeychecking to no (must happen before rsync) -run "echo \"Ping $SERVER\"" - -clean - -# copy over riscv-tools, and chipyard to remote -run "mkdir -p $REMOTE_CHIPYARD_DIR" -run "mkdir -p $REMOTE_RISCV_DIR" - -copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR -copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR - -# Copy ivy2 and sbt directories - -run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" -run "cp -r ~/.sbt $REMOTE_WORK_DIR" - -TOOLS_DIR=$REMOTE_RISCV_DIR -LD_LIB_DIR=$REMOTE_RISCV_DIR/lib - -# Run midasexamples test - -run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" -run "export RISCV=\"$TOOLS_DIR\"; \ - export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export FIRESIM_ENV_SOURCED=1; \ - export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ - export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" TARGET_PROJECT=midasexamples test" diff --git a/CHANGELOG.md b/CHANGELOG.md index 38ea7e6e08..7d06eda8d3 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -58,7 +58,7 @@ A more detailed account of everything included is included in the dev to master * N/A ### Removed -* N/A +* Removed MIDAS examples CI (until a better solution that is faster is found) (#589) ## [1.2.0] - 2020-03-14