From 0f49423eafe46f8da6b225fb29a21b22865b81cb Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Mon, 7 Feb 2022 15:04:12 -0800 Subject: [PATCH 01/17] skywater tutorial doc files --- docs/VLSI/Sky130-Tutorial.rst | 170 ++++++++++++++++++++++++++++++++++ docs/VLSI/index.rst | 1 + 2 files changed, 171 insertions(+) create mode 100644 docs/VLSI/Sky130-Tutorial.rst diff --git a/docs/VLSI/Sky130-Tutorial.rst b/docs/VLSI/Sky130-Tutorial.rst new file mode 100644 index 0000000000..4b6bbbf6a2 --- /dev/null +++ b/docs/VLSI/Sky130-Tutorial.rst @@ -0,0 +1,170 @@ +.. _sky130-tutorial: + +Sky130 Tutorial +=============== +The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. + +Project Structure +----------------- + +This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders: + +* Makefile, sim.mk, power.mk + + * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands. + +* build + + * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. + * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. + +* env.yml + + * A template file for tool environment configuration. Fill in the install and license server paths for your environment. + +* example-vlsi + + * Entry point to Hammer. Contains example placeholders for hooks. + +* example-sky130.yml, example-tools.yml + + * Hammer IR for this tutorial. + +* example-design.yml, example-nangate45.yml, example-tech.yml + + * Hammer IR not used for this tutorial but provided as templates. + +* generated-src + + * All of the elaborated Chisel and FIRRTL. + +* hammer, hammer--plugins, hammer--plugin + + * Core, tool, tech repositories. + +* view_gds.py + + * A convenience script to view a layout using gdspy. Note that this will be very slow for large layouts (e.g. a Rocket core)! + +Prerequisites +------------- + +* Python 3.4+ +* numpy package +* gdspy 1.4 package if using ``view_gds.py`` script +* Genus, Innovus, and Calibre licenses +* Sky130 PDK, install using `these directions `__ + +Initial Setup +------------- +In the Chipyard root, run: + +.. code-block:: shell + + ./scripts/init-vlsi.sh sky130 + +to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. + +Pull the Hammer environment into the shell: + +.. code-block:: shell + + cd vlsi + export HAMMER_HOME=$PWD/hammer + source $HAMMER_HOME/sourceme.sh + +Building the Design +-------------------- +To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow: + +.. code-block:: shell + + make buildfile CONFIG=TinyRocketConfig + +The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. + +For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. + +Running the VLSI Flow +--------------------- + +example-vlsi +^^^^^^^^^^^^ +This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. + + +example-sky130.yml +^^^^^^^^^^^^^^^^^^ +This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. + +First, set ``technology.sky130.sky130A`` to the absolute path to the ``sky130A`` directory containing the Sky130 PDK files. See the +`Sky130 Hammer plugin README `__ +for details about the PDK setup. + + +Synthesis +^^^^^^^^^ +.. code-block:: shell + + make syn CONFIG=TinyRocketConfig + +Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. + +Place-and-Route +^^^^^^^^^^^^^^^ +.. code-block:: shell + + make par CONFIG=TinyRocketConfig + +After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``. + +Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. + +Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. + +``gdspy`` can be used to `view the final layout `__, but it is somewhat crude and slow (wait a few minutes for it to load): + +.. code-block:: shell + + python3 view_gds.py build/chipyard.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds + +By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names. + +DRC & LVS +^^^^^^^^^ +To run DRC & LVS, and view the results in Calibre: + +.. code-block:: shell + + make drc CONFIG=TinyRocketConfig + ./build/drc-rundir/generated-scripts/view-drc + make lvs CONFIG=TinyRocketConfig + ./build/lvs-rundir/generated-scripts/view-lvs + +Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the +`Sky130 Hammer plugin README `__. +For this reason, the ``example-vlsi`` script black-boxes the SRAMs for DRC/LVS analysis. + +Simulation +^^^^^^^^^^ +Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and post-P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation: + +.. code-block:: shell + + make sim-rtl CONFIG=TinyRocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + +Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively. + +Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. + +Power/Rail Analysis +^^^^^^^^^^^^^^^^^^^ +Post-P&R power and rail (IR drop) analysis is supported with Voltus: + +.. code-block:: shell + + make power-par CONFIG=TinyRocketConfig + +If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim--debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform. + +To bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Static and active (vectorless) power & IR drop will be reported. diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 56e807e87e..5f812395e2 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -12,4 +12,5 @@ In particular, we aim to support the Hammer physical design generator flow. Hammer Basic-Flow Tutorial + Sky130-Tutorial Advanced-Usage From f54f78504bf4d67d9c90f07eea30e8093da5a451 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Wed, 9 Feb 2022 13:10:44 -0800 Subject: [PATCH 02/17] sky130 tutorial initial modifications --- scripts/init-vlsi.sh | 2 +- vlsi/Makefile | 10 +- vlsi/example-sky130.yml | 194 +++++++++++++++++++++++++++++++++++++++ vlsi/example-vlsi-sky130 | 98 ++++++++++++++++++++ 4 files changed, 300 insertions(+), 4 deletions(-) create mode 100644 vlsi/example-sky130.yml create mode 100755 vlsi/example-vlsi-sky130 diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh index bbc562d4c0..51184e58d8 100755 --- a/scripts/init-vlsi.sh +++ b/scripts/init-vlsi.sh @@ -10,6 +10,6 @@ git submodule update --init --recursive vlsi/hammer-synopsys-plugins git submodule update --init --recursive vlsi/hammer-mentor-plugins # Initialize HAMMER tech plugin -if [[ $1 != *asap7* ]]; then +if [[ $1 != *asap7* ]] && [[ $1 != *sky130* ]]; then git submodule update --init --recursive vlsi/hammer-$1-plugin fi diff --git a/vlsi/Makefile b/vlsi/Makefile index e2a9186518..3aaebf3b9c 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -19,7 +19,7 @@ include $(base_dir)/variables.mk ######################################################################################### sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 -tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ +tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\ $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \ $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json @@ -36,8 +36,12 @@ ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= example-tools.yml \ $(if $(filter $(tech_name),nangate45),\ example-nangate45.yml,\ - example-asap7.yml) -HAMMER_EXEC ?= ./example-vlsi + $(if $(filter $(tech_name),asap7),\ + example-asap7.yml,\ + example-sky130.yml)) +HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\ + ./example-vlsi-sky130,\ + ./example-vlsi) VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= chiptop # If overriding, this should be relative to $(vlsi_dir) diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml new file mode 100644 index 0000000000..8f5ec642ac --- /dev/null +++ b/vlsi/example-sky130.yml @@ -0,0 +1,194 @@ +# Technology Setup +# Technology used is Sky130 +vlsi.core.technology: sky130 + +vlsi.core.max_threads: 12 + +# Technology paths +technology.sky130: + # sky130_pdk: "path-to-skywater-pdk/" + sky130_nda: "path-to-skywater-src-nda/" + sky130A: "path-to-sky130A/" + openram_lib: "path-to-sky130_sram_macros/" + +# Mentor environment variables +mentor.extra_env_vars: + - PDK_HOME: "path-to-skywater-src-nda/s8/V2.0.1" +# General Hammer Inputs + +# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info +vlsi.inputs.power_spec_mode: "auto" +vlsi.inputs.power_spec_type: "cpf" + +# Specify clock signals +vlsi.inputs.clocks: [ + {name: "clock_clock", period: "20ns", uncertainty: "0.5ns"} +] + +# Generate Make include to aid in flow +vlsi.core.build_system: make + +# Power Straps +par.power_straps_mode: generate +par.generate_power_straps_method: by_tracks +par.blockage_spacing: 2.0 +par.generate_power_straps_options: + by_tracks: + strap_layers: + - met2 + - met3 + - met4 + - met5 + pin_layers: + - met5 + track_width: 6 + track_width_met5: 2 + track_spacing: 1 + track_start: 10 + power_utilization: 0.2 + power_utilization_met5: 1 + +# Placement Constraints +# For ASAP7, all numbers must be 4x larger than final GDS +vlsi.inputs.placement_constraints: + - path: "ChipTop" + type: toplevel + x: 0 + y: 0 + # width: 800 + # height: 500 + width: 4000 + height: 3000 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + type: hardmacro + x: 30 + y: 2190 + orientation: r0 + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + type: hardmacro + x: 30 + y: 1530 + orientation: mx + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0" + type: hardmacro + x: 30 + y: 1030 + orientation: mx + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0" + type: hardmacro + x: 30 + y: 530 + orientation: mx + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0" + type: hardmacro + x: 30 + y: 30 + orientation: mx + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0" + type: hardmacro + x: 1110 + y: 30 + orientation: mx + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0" + type: hardmacro + x: 2150 + y: 30 + orientation: mx + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0" + type: hardmacro + x: 2150 + y: 530 + orientation: mx + top_layer: "met4" + + + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 2150 + y: 1550 + orientation: mx + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0" + type: hardmacro + x: 2150 + y: 1030 + orientation: r0 + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" + type: hardmacro + x: 2350 + y: 2200 + orientation: r0 + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" + type: hardmacro + x: 3100 + y: 30 + orientation: "r0" + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1" + type: hardmacro + x: 3100 + y: 530 + orientation: "r0" + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2" + type: hardmacro + x: 3100 + y: 1030 + orientation: "r0" + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3" + type: hardmacro + x: 3100 + y: 1530 + orientation: "r0" + top_layer: "met4" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4" + type: hardmacro + x: 3100 + y: 2190 + orientation: "r0" + top_layer: "met4" + +# Pin placement constraints +vlsi.inputs.pin_mode: generated +vlsi.inputs.pin.generate_mode: semi_auto +vlsi.inputs.pin.assignments: [ + {pins: "*", layers: ["met2", "met4"], side: "bottom"} +] + +# SRAM Compiler compiler options +vlsi.core.sram_generator_tool: "sram_compiler" +# You should specify a location for the SRAM generator in the tech plugin +# vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"] +vlsi.core.sram_generator_tool_path: ["/tools/B/nayiri/test/hammer/src/hammer-vlsi/technology/sky130"] +vlsi.core.sram_generator_tool_path_meta: "append" diff --git a/vlsi/example-vlsi-sky130 b/vlsi/example-vlsi-sky130 new file mode 100755 index 0000000000..73fba53081 --- /dev/null +++ b/vlsi/example-vlsi-sky130 @@ -0,0 +1,98 @@ +#!/usr/bin/env python3 +# +# NOTE: the custom hooks are only used for sky130. + +import os + +import hammer_vlsi +from hammer_vlsi import CLIDriver, HammerToolHookAction + +from typing import Dict, Callable, Optional, List + +from technology.sky130 import SKY130Tech + +def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: + if x.get_setting("vlsi.core.technology") == "sky130": + x.append(''' +# TODO +# Place custom TCL here +''') + return True + +def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: + if x.get_setting("vlsi.core.technology") == "sky130": + x.append(''' +# TODO +# Place custom TCL here +''') + return True + +def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: + if x.get_setting("vlsi.core.technology") == "sky130": + x.append(''' +# TODO +# Place custom TCL here +set_db route_design_bottom_routing_layer 2 +set_db route_design_top_routing_layer 5 +''') + return True + +def drc_blackbox_openram_srams(x: hammer_vlsi.HammerTool) -> bool: + if x.get_setting("vlsi.core.technology") == "sky130": + drc_box = '' + for name in SKY130Tech().openram_sram_names(): + drc_box += f"\nEXCLUDE CELL {name}" + with open(x.drc_run_file, "a") as f: + f.write(drc_box) + return True + +def lvs_blackbox_openram_srams(x: hammer_vlsi.HammerTool) -> bool: + if x.get_setting("vlsi.core.technology") == "sky130": + lvs_box = '' + for name in SKY130Tech.openram_sram_names(): + lvs_box += f"\nLVS BOX {name}" + lvs_box += f"\nLVS FILTER {name} OPEN " + with open(x.lvs_run_file, "a") as f: + f.write(lvs_box) + return True + + +class ExampleDriver(CLIDriver): + def get_extra_par_hooks(self) -> List[HammerToolHookAction]: + extra_hooks = [ + + # Default set of steps can be found in the CAD tool plugin's __init__.py + + # make_pre_insertion_hook will execute the custom hook before the specified step + # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) + # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), + + # make_post_insertion_hook will execute the custom hook after the specified step + hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), + + # make_replacement_hook will replace the specified step with a custom hook + # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + + # make_removal_hook will remove the specified step from the flow + hammer_vlsi.HammerTool.make_removal_hook("place_bumps"), + + # The target step in any of the above calls may be a default step or another one of your custom hooks + ] + return extra_hooks + + def get_extra_drc_hooks(self) -> List[HammerToolHookAction]: + extra_hooks = [ + # This is an example of a technology-supplied hook + hammer_vlsi.HammerTool.make_post_insertion_hook("generate_drc_run_file", drc_blackbox_openram_srams), + ] + return extra_hooks + + def get_extra_lvs_hooks(self) -> List[HammerToolHookAction]: + extra_hooks = [ + # This is an example of a technology-supplied hook + hammer_vlsi.HammerTool.make_post_insertion_hook("generate_lvs_run_file", lvs_blackbox_openram_srams), + ] + return extra_hooks + +if __name__ == '__main__': + ExampleDriver().main() From ee465086fefb4a5cba5b130ae5cac187bf41f2e8 Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Fri, 11 Feb 2022 18:52:35 -0800 Subject: [PATCH 03/17] updating skywater tutorial docs --- docs/VLSI/Sky130-Tutorial.rst | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/docs/VLSI/Sky130-Tutorial.rst b/docs/VLSI/Sky130-Tutorial.rst index 4b6bbbf6a2..c07a19acec 100644 --- a/docs/VLSI/Sky130-Tutorial.rst +++ b/docs/VLSI/Sky130-Tutorial.rst @@ -42,16 +42,11 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * Core, tool, tech repositories. -* view_gds.py - - * A convenience script to view a layout using gdspy. Note that this will be very slow for large layouts (e.g. a Rocket core)! - Prerequisites ------------- * Python 3.4+ * numpy package -* gdspy 1.4 package if using ``view_gds.py`` script * Genus, Innovus, and Calibre licenses * Sky130 PDK, install using `these directions `__ @@ -79,7 +74,7 @@ To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build .. code-block:: shell - make buildfile CONFIG=TinyRocketConfig + make buildfile tech_name=sky130 CONFIG=TinyRocketConfig The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. @@ -106,7 +101,7 @@ Synthesis ^^^^^^^^^ .. code-block:: shell - make syn CONFIG=TinyRocketConfig + make syn tech_name=sky130 CONFIG=TinyRocketConfig Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. @@ -114,7 +109,7 @@ Place-and-Route ^^^^^^^^^^^^^^^ .. code-block:: shell - make par CONFIG=TinyRocketConfig + make par tech_name=sky130 CONFIG=TinyRocketConfig After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``. @@ -122,24 +117,16 @@ Intermediate database are written in ``build/par-rundir`` between each step of t Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. -``gdspy`` can be used to `view the final layout `__, but it is somewhat crude and slow (wait a few minutes for it to load): - -.. code-block:: shell - - python3 view_gds.py build/chipyard.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds - -By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names. - DRC & LVS ^^^^^^^^^ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell - make drc CONFIG=TinyRocketConfig - ./build/drc-rundir/generated-scripts/view-drc - make lvs CONFIG=TinyRocketConfig - ./build/lvs-rundir/generated-scripts/view-lvs + make drc tech_name=sky130 CONFIG=TinyRocketConfig + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc + make lvs tech_name=sky130 CONFIG=TinyRocketConfig + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. @@ -163,7 +150,7 @@ Post-P&R power and rail (IR drop) analysis is supported with Voltus: .. code-block:: shell - make power-par CONFIG=TinyRocketConfig + make power-par tech_name=sky130 CONFIG=TinyRocketConfig If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim--debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform. From 9aa7d7ee47a0490c3f33164a0a237d40cee3a939 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 11 Feb 2022 22:30:18 -0800 Subject: [PATCH 04/17] cleaned up file --- vlsi/example-sky130.yml | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 8f5ec642ac..cae98ebc31 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -7,13 +7,15 @@ vlsi.core.max_threads: 12 # Technology paths technology.sky130: # sky130_pdk: "path-to-skywater-pdk/" - sky130_nda: "path-to-skywater-src-nda/" - sky130A: "path-to-sky130A/" - openram_lib: "path-to-sky130_sram_macros/" + sky130_nda: "/tools/commercial/skywater/swtech130/skywater-src-nda" + sky130A: "/tools/commercial/skywater/swtech130/local/sky130A" + openram_lib: "/tools/commercial/skywater/swtech130/local/sky130_sram_macros" + # Mentor environment variables mentor.extra_env_vars: - - PDK_HOME: "path-to-skywater-src-nda/s8/V2.0.1" + - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" + # General Hammer Inputs # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info @@ -22,7 +24,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "20ns", uncertainty: "0.5ns"} + {name: "clock_clock", period: "200ns", uncertainty: "10ns"} ] # Generate Make include to aid in flow @@ -189,6 +191,5 @@ vlsi.inputs.pin.assignments: [ # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "sram_compiler" # You should specify a location for the SRAM generator in the tech plugin -# vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"] -vlsi.core.sram_generator_tool_path: ["/tools/B/nayiri/test/hammer/src/hammer-vlsi/technology/sky130"] +vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"] vlsi.core.sram_generator_tool_path_meta: "append" From ab9b0843415c063748445bfda307c2bb051d4e46 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 11 Feb 2022 22:33:05 -0800 Subject: [PATCH 05/17] fixing small bug --- vlsi/example-sky130.yml | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index cae98ebc31..f570b34934 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -6,15 +6,14 @@ vlsi.core.max_threads: 12 # Technology paths technology.sky130: - # sky130_pdk: "path-to-skywater-pdk/" - sky130_nda: "/tools/commercial/skywater/swtech130/skywater-src-nda" - sky130A: "/tools/commercial/skywater/swtech130/local/sky130A" - openram_lib: "/tools/commercial/skywater/swtech130/local/sky130_sram_macros" - + sky130_pdk: "path-to-skywater-pdk/" + sky130_nda: "path-to-skywater-src-nda/" + sky130A: "path-to-sky130A/" + openram_lib: "path-to-sky130_sram_macros/" # Mentor environment variables mentor.extra_env_vars: - - PDK_HOME: "/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.1" + - PDK_HOME: "path-to-skywater-src-nda/s8/V2.0.1" # General Hammer Inputs @@ -51,14 +50,11 @@ par.generate_power_straps_options: power_utilization_met5: 1 # Placement Constraints -# For ASAP7, all numbers must be 4x larger than final GDS vlsi.inputs.placement_constraints: - path: "ChipTop" type: toplevel x: 0 y: 0 - # width: 800 - # height: 500 width: 4000 height: 3000 margins: From 1945ca8e341c5c5992dde95013fe972056d017ef Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Mon, 14 Feb 2022 17:18:35 -0800 Subject: [PATCH 06/17] fixed name of entry script to example-vlsi-sky130 --- docs/VLSI/Sky130-Tutorial.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/VLSI/Sky130-Tutorial.rst b/docs/VLSI/Sky130-Tutorial.rst index c07a19acec..4c9ca4e13a 100644 --- a/docs/VLSI/Sky130-Tutorial.rst +++ b/docs/VLSI/Sky130-Tutorial.rst @@ -22,7 +22,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * A template file for tool environment configuration. Fill in the install and license server paths for your environment. -* example-vlsi +* example-vlsi-sky130 * Entry point to Hammer. Contains example placeholders for hooks. @@ -83,8 +83,8 @@ For the curious, ``make buildfile`` generates a set of Make targets in ``build/h Running the VLSI Flow --------------------- -example-vlsi -^^^^^^^^^^^^ +example-vlsi-sky130 +^^^^^^^^^^^^^^^^^^^ This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. @@ -130,7 +130,7 @@ To run DRC & LVS, and view the results in Calibre: Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. -For this reason, the ``example-vlsi`` script black-boxes the SRAMs for DRC/LVS analysis. +For this reason, the ``example-vlsi-sky130`` script black-boxes the SRAMs for DRC/LVS analysis. Simulation ^^^^^^^^^^ From 7442eda28261acc99b009482fc5ecbc2ddcc4f1c Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Tue, 15 Feb 2022 16:11:26 -0800 Subject: [PATCH 07/17] minor formatting fixes, changing name from Tutorial to ASAP7-Tutorial --- .../VLSI/{Tutorial.rst => ASAP7-Tutorial.rst} | 30 +++++++++---------- docs/VLSI/Building-A-Chip.rst | 2 +- docs/VLSI/Sky130-Tutorial.rst | 24 +++++++-------- docs/VLSI/index.rst | 2 +- 4 files changed, 29 insertions(+), 29 deletions(-) rename docs/VLSI/{Tutorial.rst => ASAP7-Tutorial.rst} (85%) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst similarity index 85% rename from docs/VLSI/Tutorial.rst rename to docs/VLSI/ASAP7-Tutorial.rst index ccf7eb3992..d881376a2f 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -9,40 +9,40 @@ Project Structure This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders: -* Makefile, sim.mk, power.mk +* ``Makefile``, ``sim.mk``, ``power.mk`` * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands. -* build +* ``build`` * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. -* env.yml +* ``env.yml`` * A template file for tool environment configuration. Fill in the install and license server paths for your environment. -* example-vlsi +* ``example-vlsi`` * Entry point to Hammer. Contains example placeholders for hooks. -* example-asap7.yml, example-tools.yml +* ``example-asap7.yml``, ``example-tools.yml`` * Hammer IR for this tutorial. -* example-design.yml, example-nangate45.yml, example-tech.yml +* ``example-design.yml``, ``example-nangate45.yml``, ``example-tech.yml`` * Hammer IR not used for this tutorial but provided as templates. -* generated-src +* ``generated-src`` * All of the elaborated Chisel and FIRRTL. -* hammer, hammer--plugins, hammer--plugin +* ``hammer``, ``hammer--plugins``, ``hammer--plugin`` * Core, tool, tech repositories. -* view_gds.py +* ``view_gds.py`` * A convenience script to view a layout using gdstk or gdspy. Only use this for small layouts (i.e. smaller than the TinyRocketConfig example) since the gdstk-produced SVG will be too big and gdspy's GUI is very slow for large layouts! @@ -65,7 +65,7 @@ In the Chipyard root, run: ./scripts/init-vlsi.sh asap7 -to pull the Hammer & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. +to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. Pull the Hammer environment into the shell: @@ -106,7 +106,7 @@ Synthesis make syn CONFIG=TinyRocketConfig -Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. +Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw quality of results data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a work in progress. Place-and-Route ^^^^^^^^^^^^^^^ @@ -144,15 +144,15 @@ Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not h Simulation ^^^^^^^^^^ -Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation: +Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and post-P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation: .. code-block:: shell make sim-rtl CONFIG=TinyRocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple -Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` targets, respectively. +Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively. -You can also append ``-debug`` and ``-debug-timing`` to the above sim targets, which will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. +Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. Power/Rail Analysis ^^^^^^^^^^^^^^^^^^^ @@ -164,4 +164,4 @@ Post-P&R power and rail (IR drop) analysis is supported with Voltus: If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim--debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform. -Note that power and rail analysis can also be run without gate-level simulation, but you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Only static and active (vectorless) power & IR drop will be reported. +To bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Static and active (vectorless) power & IR drop will be reported. diff --git a/docs/VLSI/Building-A-Chip.rst b/docs/VLSI/Building-A-Chip.rst index 3cd6273e83..4916702c6d 100644 --- a/docs/VLSI/Building-A-Chip.rst +++ b/docs/VLSI/Building-A-Chip.rst @@ -49,6 +49,6 @@ Running the VLSI tool flow -------------------------- For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. -For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/Tutorial:ASAP7 Tutorial`. +For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/ASAP7-Tutorial:ASAP7 Tutorial`. diff --git a/docs/VLSI/Sky130-Tutorial.rst b/docs/VLSI/Sky130-Tutorial.rst index 4c9ca4e13a..f004dec469 100644 --- a/docs/VLSI/Sky130-Tutorial.rst +++ b/docs/VLSI/Sky130-Tutorial.rst @@ -9,36 +9,36 @@ Project Structure This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders: -* Makefile, sim.mk, power.mk +* ``Makefile``, ``sim.mk``, ``power.mk`` * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands. -* build +* ``build`` * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. -* env.yml +* ``env.yml`` * A template file for tool environment configuration. Fill in the install and license server paths for your environment. -* example-vlsi-sky130 +* ``example-vlsi-sky130`` * Entry point to Hammer. Contains example placeholders for hooks. -* example-sky130.yml, example-tools.yml +* ``example-sky130.yml``, ``example-tools.yml`` * Hammer IR for this tutorial. -* example-design.yml, example-nangate45.yml, example-tech.yml +* ``example-design.yml``, ``example-nangate45.yml``, ``example-tech.yml`` * Hammer IR not used for this tutorial but provided as templates. -* generated-src +* ``generated-src`` * All of the elaborated Chisel and FIRRTL. -* hammer, hammer--plugins, hammer--plugin +* ``hammer``, ``hammer--plugins``, ``hammer--plugin`` * Core, tool, tech repositories. @@ -47,7 +47,7 @@ Prerequisites * Python 3.4+ * numpy package -* Genus, Innovus, and Calibre licenses +* Genus, Innovus, Voltus, VCS, and Calibre licenses * Sky130 PDK, install using `these directions `__ Initial Setup @@ -92,8 +92,8 @@ example-sky130.yml ^^^^^^^^^^^^^^^^^^ This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. -First, set ``technology.sky130.sky130A`` to the absolute path to the ``sky130A`` directory containing the Sky130 PDK files. See the -`Sky130 Hammer plugin README `__ +First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the +`Sky130 Hammer plugin README `__ for details about the PDK setup. @@ -103,7 +103,7 @@ Synthesis make syn tech_name=sky130 CONFIG=TinyRocketConfig -Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. +Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw quality of results data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a work in progress. Place-and-Route ^^^^^^^^^^^^^^^ diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 5f812395e2..1758a65a99 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -11,6 +11,6 @@ In particular, we aim to support the Hammer physical design generator flow. Building-A-Chip Hammer Basic-Flow - Tutorial + ASAP7-Tutorial Sky130-Tutorial Advanced-Usage From 4956a93c2711e553d47c7d52ec613dd7a58b3124 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 16:56:05 -0800 Subject: [PATCH 08/17] changing clock to clock_clock [skip ci] --- vlsi/example-asap7.yml | 2 +- vlsi/example-design.yml | 2 +- vlsi/example-nangate45.yml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 683edaae59..213f0b906b 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_clock", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index 43f54997b8..3c11cd11b6 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_clock", period: "2ns", uncertainty: "0.1ns"} ] # Specify pin properties diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index c1c3ba63d4..5b4a59ea27 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -22,7 +22,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "5ns", uncertainty: "0.5ns"} + {name: "clock_clock", period: "5ns", uncertainty: "0.5ns"} ] # Generate Make include to aid in flow From e9b1c4818c799b24ab3ff136f1810c41ea9fd2c7 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 16:56:41 -0800 Subject: [PATCH 09/17] removing extra space [skip ci] --- vlsi/example-vlsi | 1 - vlsi/example-vlsi-sky130 | 36 +----------------------------------- 2 files changed, 1 insertion(+), 36 deletions(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index bf280f0fc8..73f73ffedb 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -39,7 +39,6 @@ set_db route_design_top_routing_layer 7 class ExampleDriver(CLIDriver): def get_extra_par_hooks(self) -> List[HammerToolHookAction]: extra_hooks = [ - # Default set of steps can be found in the CAD tool plugin's __init__.py # make_pre_insertion_hook will execute the custom hook before the specified step diff --git a/vlsi/example-vlsi-sky130 b/vlsi/example-vlsi-sky130 index 73fba53081..b3bf94677b 100755 --- a/vlsi/example-vlsi-sky130 +++ b/vlsi/example-vlsi-sky130 @@ -32,35 +32,15 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here +# only route in met1 to met4 set_db route_design_bottom_routing_layer 2 set_db route_design_top_routing_layer 5 ''') return True -def drc_blackbox_openram_srams(x: hammer_vlsi.HammerTool) -> bool: - if x.get_setting("vlsi.core.technology") == "sky130": - drc_box = '' - for name in SKY130Tech().openram_sram_names(): - drc_box += f"\nEXCLUDE CELL {name}" - with open(x.drc_run_file, "a") as f: - f.write(drc_box) - return True - -def lvs_blackbox_openram_srams(x: hammer_vlsi.HammerTool) -> bool: - if x.get_setting("vlsi.core.technology") == "sky130": - lvs_box = '' - for name in SKY130Tech.openram_sram_names(): - lvs_box += f"\nLVS BOX {name}" - lvs_box += f"\nLVS FILTER {name} OPEN " - with open(x.lvs_run_file, "a") as f: - f.write(lvs_box) - return True - - class ExampleDriver(CLIDriver): def get_extra_par_hooks(self) -> List[HammerToolHookAction]: extra_hooks = [ - # Default set of steps can be found in the CAD tool plugin's __init__.py # make_pre_insertion_hook will execute the custom hook before the specified step @@ -79,20 +59,6 @@ class ExampleDriver(CLIDriver): # The target step in any of the above calls may be a default step or another one of your custom hooks ] return extra_hooks - - def get_extra_drc_hooks(self) -> List[HammerToolHookAction]: - extra_hooks = [ - # This is an example of a technology-supplied hook - hammer_vlsi.HammerTool.make_post_insertion_hook("generate_drc_run_file", drc_blackbox_openram_srams), - ] - return extra_hooks - - def get_extra_lvs_hooks(self) -> List[HammerToolHookAction]: - extra_hooks = [ - # This is an example of a technology-supplied hook - hammer_vlsi.HammerTool.make_post_insertion_hook("generate_lvs_run_file", lvs_blackbox_openram_srams), - ] - return extra_hooks if __name__ == '__main__': ExampleDriver().main() From dc17b85a396dbfa33cf507abbb946363e55fb529 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 16:57:17 -0800 Subject: [PATCH 10/17] bumping hammer cadence plugin to lastest master commit [skip ci] --- vlsi/hammer-cadence-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 84fe59682c..998b2021b0 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 84fe59682ce326fba27624a383d8b5c3ba0716af +Subproject commit 998b2021b028bedf7c45f7a32915b1831f842c9b From 488e25c001663ed2794eeb5d10343d0889d15694 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 18:01:53 -0800 Subject: [PATCH 11/17] modified power straps and floorplan to improve PnR results [skip ci] --- vlsi/example-sky130.yml | 132 ++++++++++++++++++---------------------- 1 file changed, 58 insertions(+), 74 deletions(-) diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index f570b34934..e8cae39aa4 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -7,14 +7,10 @@ vlsi.core.max_threads: 12 # Technology paths technology.sky130: sky130_pdk: "path-to-skywater-pdk/" - sky130_nda: "path-to-skywater-src-nda/" sky130A: "path-to-sky130A/" + sky130_nda: "path-to-skywater-src-nda/" openram_lib: "path-to-sky130_sram_macros/" -# Mentor environment variables -mentor.extra_env_vars: - - PDK_HOME: "path-to-skywater-src-nda/s8/V2.0.1" - # General Hammer Inputs # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info @@ -23,7 +19,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "200ns", uncertainty: "10ns"} + {name: "clock_clock", period: "130ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow @@ -33,21 +29,23 @@ vlsi.core.build_system: make par.power_straps_mode: generate par.generate_power_straps_method: by_tracks par.blockage_spacing: 2.0 +par.blockage_spacing_top_layer: met4 par.generate_power_straps_options: by_tracks: strap_layers: - - met2 - - met3 - met4 - met5 pin_layers: - met5 + blockage_spacing_met2: 4.0 track_width: 6 track_width_met5: 2 track_spacing: 1 track_start: 10 - power_utilization: 0.2 - power_utilization_met5: 1 + track_start_met5: 1 + power_utilization: 0.1 + power_utilization_met4: 0.3 + power_utilization_met5: 0.5 # Placement Constraints vlsi.inputs.placement_constraints: @@ -55,127 +53,113 @@ vlsi.inputs.placement_constraints: type: toplevel x: 0 y: 0 - width: 4000 - height: 3000 + width: 4500 + height: 2500 margins: left: 0 right: 0 top: 0 bottom: 0 + # Place data cache SRAM instances - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro - x: 30 - y: 2190 + x: 50 + y: 100 orientation: r0 - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" type: hardmacro - x: 30 - y: 1530 - orientation: mx - top_layer: "met4" + x: 50 + y: 700 + orientation: r0 - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0" type: hardmacro - x: 30 - y: 1030 - orientation: mx - top_layer: "met4" + x: 50 + y: 1300 + orientation: r0 - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0" type: hardmacro - x: 30 - y: 530 - orientation: mx - top_layer: "met4" + x: 50 + y: 1900 + orientation: r0 - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0" type: hardmacro - x: 30 - y: 30 - orientation: mx - top_layer: "met4" + x: 1000 + y: 1900 + orientation: r0 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0" type: hardmacro - x: 1110 - y: 30 - orientation: mx - top_layer: "met4" + x: 1000 + y: 1300 + orientation: r0 - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0" type: hardmacro - x: 2150 - y: 30 - orientation: mx - top_layer: "met4" - + x: 1000 + y: 700 + orientation: r0 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0" type: hardmacro - x: 2150 - y: 530 - orientation: mx - top_layer: "met4" - - + x: 1000 + y: 100 + orientation: r0 + # Place instruction cache SRAM instances - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro - x: 2150 - y: 1550 - orientation: mx - top_layer: "met4" - + x: 3700 + y: 100 + orientation: r0 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0" type: hardmacro - x: 2150 - y: 1030 + x: 3700 + y: 700 orientation: r0 - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" type: hardmacro - x: 2350 - y: 2200 + x: 3000 + y: 100 orientation: r0 - top_layer: "met4" - + + # Place L2 TLB SRAM instances - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" type: hardmacro - x: 3100 - y: 30 + x: 1900 + y: 1900 orientation: "r0" - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1" type: hardmacro - x: 3100 - y: 530 + x: 2600 + y: 1900 orientation: "r0" - top_layer: "met4" - + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2" type: hardmacro - x: 3100 - y: 1030 + x: 3300 + y: 1900 orientation: "r0" - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3" type: hardmacro - x: 3100 - y: 1530 + x: 3950 + y: 1900 orientation: "r0" - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4" type: hardmacro - x: 3100 - y: 2190 + x: 3950 + y: 1300 orientation: "r0" - top_layer: "met4" # Pin placement constraints vlsi.inputs.pin_mode: generated From cbf5f9fb6273c74e928de3fa7b2c39d99d9c6c2e Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Tue, 15 Feb 2022 18:17:47 -0800 Subject: [PATCH 12/17] adding FSDB note --- docs/VLSI/ASAP7-Tutorial.rst | 2 +- docs/VLSI/Sky130-Tutorial.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index d881376a2f..b147d6a5a6 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -152,7 +152,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively. -Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. +Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. Power/Rail Analysis ^^^^^^^^^^^^^^^^^^^ diff --git a/docs/VLSI/Sky130-Tutorial.rst b/docs/VLSI/Sky130-Tutorial.rst index f004dec469..2a9c19b1d7 100644 --- a/docs/VLSI/Sky130-Tutorial.rst +++ b/docs/VLSI/Sky130-Tutorial.rst @@ -142,7 +142,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively. -Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. +Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. Power/Rail Analysis ^^^^^^^^^^^^^^^^^^^ From 82d151c17a3308d9a9465f0fb614eee92ff68bcc Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 19:42:11 -0800 Subject: [PATCH 13/17] adding layer explanation [skip ci] --- vlsi/example-vlsi-sky130 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/example-vlsi-sky130 b/vlsi/example-vlsi-sky130 index b3bf94677b..8aef8ddc0a 100755 --- a/vlsi/example-vlsi-sky130 +++ b/vlsi/example-vlsi-sky130 @@ -32,7 +32,7 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here -# only route in met1 to met4 +# only route in met1 to met4 [metal layers: li1(1), met1(2), ..., met4(5), met5(6)] set_db route_design_bottom_routing_layer 2 set_db route_design_top_routing_layer 5 ''') From 30db79a7cedf591d26c113aed80664e1fa0c1ea5 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 19:43:14 -0800 Subject: [PATCH 14/17] bumping synopsys plugins submodule [skip ci] --- vlsi/hammer-synopsys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index e9355168f6..81720fdd5b 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit e9355168f636e5bc8e5d7df66b286993be817823 +Subproject commit 81720fdd5b7fd747f34606f09b8a7d0da438a3ef From cc777d1375445315747ccdc4170bbd1605ae2e9d Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 19:43:38 -0800 Subject: [PATCH 15/17] bumping hammer submodule to include sky130 changes [skip ci] --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 95428fb44f..52c9b0191f 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 95428fb44f3d8eda395b496dbdd4e04689e08acb +Subproject commit 52c9b0191fbc32dc40c62f3b75374b1f46f39f0f From fbca9eee1a648dc3ec2ba4cc10e694d4a4327a90 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 20:36:39 -0800 Subject: [PATCH 16/17] attempting to fix hammer conflict [skip ci] --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 52c9b0191f..353af21da3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 52c9b0191fbc32dc40c62f3b75374b1f46f39f0f +Subproject commit 353af21da3fe6f0c2e054ac513b5db583031b962 From 98e62b48f60d6b8d5dd555503462bf35e69a9316 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 21:22:19 -0800 Subject: [PATCH 17/17] attempting to fix hammer conflict [skip ci] --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 353af21da3..52c9b0191f 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 353af21da3fe6f0c2e054ac513b5db583031b962 +Subproject commit 52c9b0191fbc32dc40c62f3b75374b1f46f39f0f