From aa057239f2bc14d4001681ae01e4ea759e1b4c2e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 17 Oct 2023 14:38:28 -0700 Subject: [PATCH 01/17] Bump rocket-chip + submodules for new clustered-tile API --- fpga/fpga-shells | 2 +- generators/bar-fetchers | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/ChipTop.scala | 1 - .../chipyard/src/main/scala/DigitalTop.scala | 1 - .../chipyard/src/main/scala/SpikeTile.scala | 35 ++++++++++--------- .../chipyard/src/main/scala/Subsystem.scala | 28 ++++++++------- .../chipyard/src/main/scala/System.scala | 7 ---- .../chipyard/src/main/scala/TestSuites.scala | 2 +- .../main/scala/clocking/ClockBinders.scala | 25 ++----------- .../main/scala/clocking/HasChipyardPRCI.scala | 31 +++++----------- .../main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 8 +++++ .../main/scala/config/TracegenConfigs.scala | 2 +- .../config/fragments/ClockingFragments.scala | 4 +-- .../config/fragments/RoCCFragments.scala | 8 ++--- .../config/fragments/SubsystemFragments.scala | 4 +-- .../config/fragments/TileFragments.scala | 14 ++++---- .../src/main/scala/example/FlatChipTop.scala | 12 +------ .../chipyard/src/main/scala/example/GCD.scala | 2 +- .../src/main/scala/example/TutorialTile.scala | 19 +++++----- .../src/main/scala/iobinders/IOBinders.scala | 10 +++--- generators/cva6 | 2 +- .../firechip/src/main/scala/FireSim.scala | 8 ++--- generators/ibex | 2 +- generators/riscv-sodor | 2 +- generators/rocket-chip | 2 +- generators/shuttle | 2 +- generators/sifive-blocks | 2 +- generators/sifive-cache | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/Configs.scala | 18 +++++----- .../tracegen/src/main/scala/System.scala | 5 +-- 33 files changed, 116 insertions(+), 152 deletions(-) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 2ce3e6f3df..19e0e87ced 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 2ce3e6f3df06d64c858bc1073ba1c75e7eb71a07 +Subproject commit 19e0e87cedd438f8231bb7af420cc58792735473 diff --git a/generators/bar-fetchers b/generators/bar-fetchers index a5bd985d29..12d1506f61 160000 --- a/generators/bar-fetchers +++ b/generators/bar-fetchers @@ -1 +1 @@ -Subproject commit a5bd985d29b07940e326d78964b370fa1cefec71 +Subproject commit 12d1506f610048906d2407b40a706923cbe6571e diff --git a/generators/boom b/generators/boom index 96da674bc9..65b0d39b35 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 96da674bc97955e7fa068f0a9a1d0a7a479d1d0b +Subproject commit 65b0d39b35bb5dbb3deba826979c5145846648ae diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 150221b6b9..ec636dfb25 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -5,7 +5,6 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} -import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} import freechips.rocketchip.util.{ResetCatchAndSync} diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index d7263008a2..1dafe42deb 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -40,7 +40,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem } class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) - with testchipip.CanHaveTraceIOModuleImp with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index fc822c2272..7778deb6d5 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -77,14 +77,15 @@ case class SpikeTileAttachParams( } case class SpikeTileParams( - hartId: Int = 0, + tileId: Int = 0, val core: SpikeCoreParams = SpikeCoreParams(), icacheParams: ICacheParams = ICacheParams(nWays = 32), dcacheParams: DCacheParams = DCacheParams(nWays = 32), tcmParams: Option[MasterPortParams] = None // tightly coupled memory ) extends InstantiableTileParams[SpikeTile] { - val name = Some("spike_tile") + val baseName = "spike_tile" + val uniqueName = s"${baseName}_$tileId" val beuAddr = None val blockerCtrlAddr = None val btb = None @@ -92,7 +93,7 @@ case class SpikeTileParams( val dcache = Some(dcacheParams) val icache = Some(icacheParams) val clockSinkParams = ClockSinkParameters() - def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = { + def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = { new SpikeTile(this, crossing, lookup) } } @@ -106,11 +107,11 @@ class SpikeTile( with SourcesExternalNotifications { // Private constructor ensures altered LazyModule.p is used implicitly - def this(params: SpikeTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = + def this(params: SpikeTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) // Required TileLink nodes - val intOutwardNode = IntIdentityNode() + val intOutwardNode = Some(IntIdentityNode()) val masterNode = visibilityNode val slaveNode = TLIdentityNode() @@ -129,21 +130,21 @@ class SpikeTile( } ResourceBinding { - Resource(cpuDevice, "reg").bind(ResourceAddress(hartId)) + Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } val icacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( sourceId = IdRange(0, 1), - name = s"Core ${staticIdForMetadataUseOnly} ICache"))))) + name = s"Core ${tileId} ICache"))))) val dcacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( - name = s"Core ${staticIdForMetadataUseOnly} DCache", + name = s"Core ${tileId} DCache", sourceId = IdRange(0, tileParams.dcache.get.nMSHRs), supportsProbe = TransferSizes(p(CacheBlockBytes), p(CacheBlockBytes))))))) val mmioNode = TLClientNode((Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( - name = s"Core ${staticIdForMetadataUseOnly} MMIO", + name = s"Core ${tileId} MMIO", sourceId = IdRange(0, 1), requestFifo = true)))))) @@ -313,7 +314,7 @@ class SpikeBlackBox( } class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { - + val tileParams = outer.tileParams // We create a bundle here and decode the interrupt. val int_bundle = Wire(new TileInterrupts()) outer.decodeCoreInterrupts(int_bundle) @@ -337,7 +338,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { // then the DTM-based bringup with SimDTM will be used. This isn't required to be // true, but it usually is val useDTM = p(ExportDebug).protocols.contains(DMI) - val spike = Module(new SpikeBlackBox(hartId, isaDTS, tileParams.core.nPMPs, + val spike = Module(new SpikeBlackBox(outer.tileId, outer.isaDTS, tileParams.core.nPMPs, tileParams.icache.get.nSets, tileParams.icache.get.nWays, tileParams.dcache.get.nSets, tileParams.dcache.get.nWays, tileParams.dcache.get.nMSHRs, @@ -467,19 +468,21 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { } } -class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams(), - overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { +class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams() +) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { // Calculate the next available hart ID (since hart ID cannot be duplicated) val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) // Create TileAttachParams for every core to be instantiated (0 until n).map { i => SpikeTileAttachParams( - tileParams = tileParams.copy(hartId = i + idOffset) + tileParams = tileParams.copy(tileId = i + idOffset) ) } ++ prev } + case NumTiles => up(NumTiles) + n + }) class WithSpikeTCM extends Config((site, here, up) => { @@ -492,5 +495,5 @@ class WithSpikeTCM extends Config((site, here, up) => { ))) } case ExtMem => None - case BankedL2Key => up(BankedL2Key).copy(nBanks = 0) + case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey).copy(nBanks = 0) }) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index d25d4fa3f1..1a41ce8159 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -71,18 +71,24 @@ trait CanHaveChosenInDTS { this: BaseSubsystem => } class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem - with HasTiles - with HasPeripheryDebug - with CanHaveHTIF - with CanHaveChosenInDTS + with InstantiatesHierarchicalElements + with HasTileNotificationSinks + with HasTileInputConstants + with CanHavePeripheryCLINT + with CanHavePeripheryPLIC + with HasPeripheryDebug + with HasHierarchicalElementsRootContext + with HasHierarchicalElements + with CanHaveHTIF + with CanHaveChosenInDTS { - def coreMonitorBundles = tiles.map { + def coreMonitorBundles = totalTiles.values.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case b: BoomTile => b.module.core.coreMonitorBundle }.toList // No-tile configs have to be handled specially. - if (tiles.size == 0) { + if (totalTiles.size == 0) { // no PLIC, so sink interrupts to nowhere require(!p(PLICKey).isDefined) val intNexus = IntNexusNode(sourceFn = x => x.head, sinkFn = x => x.head) @@ -96,10 +102,6 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem tileHaltXbarNode := IntSourceNode(IntSourcePortSimple()) tileWFIXbarNode := IntSourceNode(IntSourcePortSimple()) tileCeaseXbarNode := IntSourceNode(IntSourcePortSimple()) - - // Sink reset vectors to nowhere - val resetVectorSink = BundleBridgeSink[UInt](Some(() => UInt(28.W))) - resetVectorSink := tileResetVectorNode } // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for @@ -107,7 +109,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem // ClockGroup. This makes it impossible to determine which clocks are driven // by which bus based on the member names, which is problematic when there is // a rational crossing between two buses. Instead, provide all bus clocks - // directly from the asyncClockGroupsNode in the subsystem to ensure bus + // directly from the allClockGroupsNode in the subsystem to ensure bus // names are always preserved in the top-level clock names. // // For example, using a RationalCrossing between the Sbus and Cbus, and @@ -116,12 +118,12 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem // Conversly, if an async crossing is used, they instead receive names of the // form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases. Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc => - tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode } + tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := allClockGroupsNode } } override lazy val module = new ChipyardSubsystemModuleImp(this) } class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasTilesModuleImp + with HasHierarchicalElementsRootContextModuleImp { } diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 5643e38067..b8a04eacdf 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -32,13 +32,6 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } - // If there is no bootrom, the tile reset vector bundle will be tied to zero - if (bootROM.isEmpty) { - val fakeResetVectorSourceNode = BundleBridgeSource[UInt]() - InModuleBody { fakeResetVectorSourceNode.bundle := 0.U } - tileResetVectorNexusNode := fakeResetVectorSourceNode - } - override lazy val module = new ChipyardSystemModule(this) } diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 0e4e33107d..2a88ebb2a2 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -65,7 +65,7 @@ class TestSuiteHelper */ def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = { val xlen = p(XLen) - tiles.find(_.hartId == 0).map { tileParams => + tiles.find(_.tileId == 0).map { tileParams => val coreParams = tileParams.core val vm = coreParams.useVM val env = if (vm) List("p","v") else List("p") diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 3ef8a61bdd..fa31163d70 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -18,16 +18,6 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { // Connect the implicit clock implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere) val baseAddress = system.prciParams.baseAddress val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) } @@ -38,7 +28,7 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } - system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode + system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode // Connect all other requested clocks val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) @@ -83,23 +73,12 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ // This passes all clocks through to the TestHarness class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { - // Connect the implicit clock implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } // This aggregate node should do nothing val clockGroupAggNode = ClockGroupAggregateNode("fake") val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode + system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode InModuleBody { val reset_io = IO(Input(AsyncReset())) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 356a04329d..a983280699 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -29,8 +29,8 @@ case class ChipyardPRCIControlParams( case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) -trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => - require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven") +trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElementss => + require(!p(SubsystemDriveDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) @@ -48,29 +48,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node - val allClockGroupsNode = ClockGroupEphemeralNode() - - // There are two "sets" of clocks which must be dealt with - - // 1. The implicit clock from the subsystem. RC is moving away from depending on this - // clock, but some modules still use it. Since the implicit clock sink node - // is created in the ChipTop (the hierarchy wrapping the subsystem), this function - // is provided to allow connecting that clock to the clock aggregator. This function - // should be called in the ChipTop context - def connectImplicitClockSinkNode(sink: ClockSinkNode) = { - val implicitClockGrouper = this { ClockGroup() } - (sink - := implicitClockGrouper - := aggregator) - } - // 2. The rest of the diplomatic clocks in the subsystem are routed to this asyncClockGroupsNode + // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() - (asyncClockGroupsNode + (allClockGroupsNode :*= clockNamePrefixer :*= aggregator) - // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) @@ -91,7 +75,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, - tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)) + tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get reset_setter } } @@ -115,11 +99,14 @@ RTL SIMULATORS, NAMELY VERILATOR. """ + Console.RESET) } + // The chiptopClockGroupsNode shouuld be what ClockBinders attach to + val chiptopClockGroupsNode = ClockGroupEphemeralNode() + (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) - := allClockGroupsNode) + := chiptopClockGroupsNode) } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index a08abb6d63..0891a21dbb 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -66,7 +66,7 @@ class AbstractConfig extends Config( new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks + new chipyard.config.WithNoSubsystemClockIO ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index c45fb6f236..a9f87b2819 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -2,6 +2,7 @@ package chipyard import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} +import freechips.rocketchip.subsystem.{InCluster} // -------------- // Rocket Configs @@ -110,3 +111,10 @@ class PrefetchingRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) + +class ClusteredRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(1)) ++ + new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(0)) ++ + new freechips.rocketchip.subsystem.WithCluster(1) ++ + new freechips.rocketchip.subsystem.WithCluster(0) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 55cce1b818..78c815fb99 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -14,7 +14,7 @@ class AbstractTraceGenConfig extends Config( new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++ new chipyard.config.WithTracegenSystem ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithNoSubsystemClockIO ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new chipyard.config.WithSystemBusFrequency(1000.0) ++ new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 2da9fbf283..8ccc8afac5 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -18,8 +18,8 @@ import chipyard.clocking._ // with the implicit clocks of Subsystem. Don't do that, instead we extend // the diplomacy graph upwards into the ChipTop, where we connect it to // our clock drivers -class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { - case SubsystemDriveAsyncClockGroupsKey => None +class WithNoSubsystemClockIO extends Config((site, here, up) => { + case SubsystemDriveClockGroupsFromIO => false }) /** diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala index 4680eeebf7..c9f7fcdbe1 100644 --- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -12,15 +12,15 @@ import gemmini._ import chipyard.{TestSuitesKey, TestSuiteHelper} /** - * Map from a hartId to a particular RoCC accelerator + * Map from a tileId to a particular RoCC accelerator */ case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) /** - * Config fragment to enable different RoCCs based on the hartId + * Config fragment to enable different RoCCs based on the tileId */ class WithMultiRoCC extends Config((site, here, up) => { - case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) + case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).tileId, Nil) }) /** @@ -39,7 +39,7 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) => * * For ex: * Core 0, 1, 2, 3 have been defined earlier - * with hartIds of 0, 1, 2, 3 respectively + * with tileIds of 0, 1, 2, 3 respectively * And you call WithMultiRoCCHwacha(0,1) * Then Core 0 and 1 will get a Hwacha * diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 40f18d5dc7..4416a572dc 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -1,12 +1,12 @@ package chipyard.config import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} +import freechips.rocketchip.subsystem.{SystemBusKey, SubsystemBankedCoherenceKey, CoherenceManagerWrapper} import freechips.rocketchip.diplomacy.{DTSTimebase} // Replaces the L2 with a broadcast manager for maintaining coherence class WithBroadcastManager extends Config((site, here, up) => { - case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) + case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) }) class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 17eaa3f063..db10486761 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -69,7 +69,7 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => { class WithRocketICacheScratchpad extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.hartId * 0x10000))) + icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.tileId * 0x10000))) )) } }) @@ -77,7 +77,7 @@ class WithRocketICacheScratchpad extends Config((site, here, up) => { class WithRocketDCacheScratchpad extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.hartId * 0x10000))) + dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.tileId * 0x10000))) )) } }) @@ -85,14 +85,14 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { class WithTilePrefetchers extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) } }) diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index a1a1aeaa2a..954deec86a 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -24,9 +24,6 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { //======================== // Diplomatic clock stuff //======================== - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere) val baseAddress = system.prciParams.baseAddress val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) } @@ -37,7 +34,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } - system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode + system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode // Connect all other requested clocks val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) @@ -61,13 +58,6 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { //========================= // Clock/reset //========================= - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - val clock_wire = Wire(Input(Clock())) val reset_wire = Wire(Input(AsyncReset())) val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index 5e6c5d67cd..a92beb5518 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -185,7 +185,7 @@ trait CanHavePeripheryGCD { this: BaseSubsystem => // DOC include end: GCD lazy trait // DOC include start: GCD imp trait -trait CanHavePeripheryGCDModuleImp extends LazyModuleImp { +trait CanHavePeripheryGCDModuleImp extends LazyRawModuleImp { val outer: CanHavePeripheryGCD val gcd_busy = outer.gcd match { case Some(gcd) => { diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 38c8577ad6..54be0f8a2e 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -82,7 +82,7 @@ case class MyTileAttachParams( case class MyTileParams( name: Option[String] = Some("my_tile"), - hartId: Int = 0, + tileId: Int = 0, trace: Boolean = false, val core: MyCoreParams = MyCoreParams() ) extends InstantiableTileParams[MyTile] @@ -94,9 +94,11 @@ case class MyTileParams( val dcache: Option[DCacheParams] = Some(DCacheParams()) val icache: Option[ICacheParams] = Some(ICacheParams()) val clockSinkParams: ClockSinkParameters = ClockSinkParameters() - def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { + def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { new MyTile(this, crossing, lookup) } + val baseName = name.getOrElse("my_tile") + val uniqueName = s"${baseName}_$tileId" } // DOC include start: Tile class @@ -111,11 +113,11 @@ class MyTile( { // Private constructor ensures altered LazyModule.p is used implicitly - def this(params: MyTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = + def this(params: MyTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) // Require TileLink nodes - val intOutwardNode = IntIdentityNode() + val intOutwardNode = Some(IntIdentityNode()) val masterNode = visibilityNode val slaveNode = TLIdentityNode() @@ -135,7 +137,7 @@ class MyTile( } ResourceBinding { - Resource(cpuDevice, "reg").bind(ResourceAddress(hartId)) + Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } // TODO: Create TileLink nodes and connections here. @@ -228,15 +230,15 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ } // DOC include start: Config fragment -class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { +class WithNMyCores(n: Int = 1) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { // Calculate the next available hart ID (since hart ID cannot be duplicated) val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) // Create TileAttachParams for every core to be instantiated (0 until n).map { i => MyTileAttachParams( - tileParams = MyTileParams(hartId = i + idOffset), + tileParams = MyTileParams(tileId = i + idOffset), crossingParams = RocketCrossingParams() ) } ++ prev @@ -245,5 +247,6 @@ class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Con case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8) // The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits. case XLen => 64 + case NumTiles => up(NumTiles) + n }) // DOC include end: Config fragment diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 773f3d3919..7fdc2a376e 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -453,14 +453,14 @@ class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({ } }) -class WithTraceIOPunchthrough extends OverrideIOBinder({ - (system: CanHaveTraceIOModuleImp) => { +class WithTraceIOPunchthrough extends OverrideLazyIOBinder({ + (system: CanHaveTraceIO) => InModuleBody { val ports: Option[TracePort] = system.traceIO.map { t => val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace") trace <> t val p = GetSystemParameters(system) val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem] - val tiles = chipyardSystem.tiles + val tiles = chipyardSystem.totalTiles.values val cfg = SpikeCosimConfig( isa = tiles.headOption.map(_.isaDTS).getOrElse(""), vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0), @@ -509,8 +509,8 @@ class WithDontTouchPorts extends OverrideIOBinder({ }) class WithNMITiedOff extends ComposeIOBinder({ - (system: HasTilesModuleImp) => { - system.nmi.flatten.foreach { nmi => + (system: HasHierarchicalElementsRootContextModuleImp) => { + system.nmi.foreach { nmi => nmi.rnmi := false.B nmi.rnmi_interrupt_vector := 0.U nmi.rnmi_exception_vector := 0.U diff --git a/generators/cva6 b/generators/cva6 index 46323fcd74..942d5aef13 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 46323fcd7407544c751b353f52e356eb8f33e9d1 +Subproject commit 942d5aef13ab82ce12adfd5346b2a2716832d69d diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 4cca755775..599788bc06 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -8,7 +8,7 @@ import chisel3._ import chisel3.experimental.{IO, annotate} import freechips.rocketchip.prci._ -import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, HasTiles} +import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName} import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap} @@ -103,8 +103,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta // FireSim ModelMultithreading chiptops.foreach { case c: ChipTop => c.lazySystem match { - case ls: HasTiles => { - if (p(FireSimMultiCycleRegFile)) ls.tiles.map { + case ls: InstantiatesHierarchicalElements => { + if (p(FireSimMultiCycleRegFile)) ls.totalTiles.values.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) @@ -120,7 +120,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta } case _ => } - if (p(FireSimFAME5)) ls.tiles.map { + if (p(FireSimFAME5)) ls.totalTiles.values.map { case b: BoomTile => annotate(EnableModelMultiThreadingAnnotation(b.module)) case r: RocketTile => diff --git a/generators/ibex b/generators/ibex index 66ec6e56ed..b52a2d7219 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 66ec6e56ed69df4e4af5383128cf21adf88b08fc +Subproject commit b52a2d721993d7b38982a0fa62b696798ac4dd9a diff --git a/generators/riscv-sodor b/generators/riscv-sodor index c1c809ebd5..ebb45b9439 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit c1c809ebd5c9a76cd60d8c3169cea4bf4b2fa8fd +Subproject commit ebb45b9439a19e2710ce0f2ee6e9ae2a192cbddf diff --git a/generators/rocket-chip b/generators/rocket-chip index 50adbdb3e4..e0ea90344e 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 50adbdb3e4e18c2b3de57693323f4174b60f9767 +Subproject commit e0ea90344e9edb6a4e24f84e7729d83c217c8859 diff --git a/generators/shuttle b/generators/shuttle index e628836c3c..924d269d1e 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit e628836c3c4bfe29927cd9e1473801fab33dee6c +Subproject commit 924d269d1ef81adfeb263a3d898c82105f7d50ed diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 5edd72e793..212c7b070b 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 5edd72e793ccb534b1395d0d8c1831754fd72fec +Subproject commit 212c7b070bc7132f31a26deec6b2bde9e0b1b612 diff --git a/generators/sifive-cache b/generators/sifive-cache index 51d400bd32..bcd248a2a2 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 51d400bd32131e8914c6713bfb71bef690f2fe70 +Subproject commit bcd248a2a2e86084a136c05d1844d88d9fba18e5 diff --git a/generators/testchipip b/generators/testchipip index 6436959d99..24de6bca03 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6436959d997d0bb578790d95078648b478ca049b +Subproject commit 24de6bca032e730749535a75b37b30834cb23c28 diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index 5d4f02114a..f51052c5be 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -13,19 +13,18 @@ import scala.math.{max, min} class WithTraceGen( n: Int = 2, - overrideIdOffset: Option[Int] = None, overrideMemOffset: Option[BigInt] = None)( params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, nReqs: Int = 8192 ) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) params.zipWithIndex.map { case (dcp, i) => TraceGenTileAttachParams( tileParams = TraceGenParams( - hartId = i + idOffset, + tileId = i + idOffset, dcache = Some(dcp), wordBits = site(XLen), addrBits = 48, @@ -48,23 +47,23 @@ class WithTraceGen( ) } ++ prev } + case NumTiles => up(NumTiles) + n }) class WithBoomTraceGen( n: Int = 2, - overrideIdOffset: Option[Int] = None, overrideMemOffset: Option[BigInt] = None)( params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) }, nReqs: Int = 8192 ) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) params.zipWithIndex.map { case (dcp, i) => BoomTraceGenTileAttachParams( tileParams = BoomTraceGenParams( - hartId = i + idOffset, + tileId = i + idOffset, dcache = Some(dcp), wordBits = site(XLen), addrBits = 48, @@ -84,24 +83,24 @@ class WithBoomTraceGen( ) } ++ prev } + case NumTiles => up(NumTiles) + n }) class WithL2TraceGen( n: Int = 2, - overrideIdOffset: Option[Int] = None, overrideMemOffset: Option[BigInt] = None)( params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, nReqs: Int = 8192 ) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) params.zipWithIndex.map { case (dcp, i) => TraceGenTileAttachParams( tileParams = TraceGenParams( - hartId = i + idOffset, + tileId = i + idOffset, dcache = Some(dcp), wordBits = site(XLen), addrBits = 48, @@ -126,4 +125,5 @@ class WithL2TraceGen( ) } ++ prev } + case NumTiles => up(NumTiles) + n }) diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 2a0ba3d5fa..5d3953cb76 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -9,11 +9,12 @@ import freechips.rocketchip.subsystem._ import boom.lsu.BoomTraceGenTile class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem - with HasTiles + with InstantiatesHierarchicalElements + with HasTileNotificationSinks with CanHaveMasterAXI4MemPort { def coreMonitorBundles = Nil - val tileStatusNodes = tiles.collect { + val tileStatusNodes = totalTiles.values.toSeq.collect { case t: GroundTestTile => t.statusNode.makeSink() case t: BoomTraceGenTile => t.statusNode.makeSink() } From 7cc03f40ebd01e8dc020eb3391ae73b5f0da39ab Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 17 Oct 2023 14:39:39 -0700 Subject: [PATCH 02/17] Add test for clustered-rocket config --- .github/scripts/defaults.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 08637428b1..e0337f30b7 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -33,7 +33,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spif grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" -grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar" +grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters" grouping["group-fpga"]="arty arty100t nexysvideo vc707 vcu118" # key value store to get the build strings @@ -67,6 +67,7 @@ mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig" mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig" mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig" mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig" +mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog" mapping["constellation"]=" SUB_PROJECT=constellation" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" From 5f51da3db361331023c660aad7166043a5831e28 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 17 Oct 2023 15:56:22 -0700 Subject: [PATCH 03/17] Fix HasChipyardPRCI typos --- .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index a983280699..1a85c9bb4e 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -29,8 +29,8 @@ case class ChipyardPRCIControlParams( case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) -trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElementss => - require(!p(SubsystemDriveDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") +trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => + require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) From e8aa68c65cdd3bf613b2d311b0b5cb0c075b9843 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 17 Oct 2023 17:05:45 -0700 Subject: [PATCH 04/17] Tiles do not generate interrupts --- generators/boom | 2 +- generators/chipyard/src/main/scala/SpikeTile.scala | 2 +- generators/chipyard/src/main/scala/example/TutorialTile.scala | 2 +- generators/chipyard/src/main/scala/iobinders/IOBinders.scala | 2 +- generators/cva6 | 2 +- generators/ibex | 2 +- generators/riscv-sodor | 2 +- generators/shuttle | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/generators/boom b/generators/boom index 65b0d39b35..9459af0c1f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 65b0d39b35bb5dbb3deba826979c5145846648ae +Subproject commit 9459af0c1f6847f8411622dac770ac78fe10847c diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index 7778deb6d5..6f211d8b08 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -111,7 +111,7 @@ class SpikeTile( this(params, crossing.crossingType, lookup, p) // Required TileLink nodes - val intOutwardNode = Some(IntIdentityNode()) + val intOutwardNode = None val masterNode = visibilityNode val slaveNode = TLIdentityNode() diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 54be0f8a2e..76b17273d2 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -117,7 +117,7 @@ class MyTile( this(params, crossing.crossingType, lookup, p) // Require TileLink nodes - val intOutwardNode = Some(IntIdentityNode()) + val intOutwardNode = None val masterNode = visibilityNode val slaveNode = TLIdentityNode() diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 7fdc2a376e..b94c1e3c80 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -459,7 +459,7 @@ class WithTraceIOPunchthrough extends OverrideLazyIOBinder({ val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace") trace <> t val p = GetSystemParameters(system) - val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem] + val chipyardSystem = system.asInstanceOf[ChipyardSystem] val tiles = chipyardSystem.totalTiles.values val cfg = SpikeCosimConfig( isa = tiles.headOption.map(_.isaDTS).getOrElse(""), diff --git a/generators/cva6 b/generators/cva6 index 942d5aef13..9d1c106834 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 942d5aef13ab82ce12adfd5346b2a2716832d69d +Subproject commit 9d1c106834824ddb8052b7f60574b2b544b40395 diff --git a/generators/ibex b/generators/ibex index b52a2d7219..c2174aba4f 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit b52a2d721993d7b38982a0fa62b696798ac4dd9a +Subproject commit c2174aba4fb304c7565c248f2a673f7151be896b diff --git a/generators/riscv-sodor b/generators/riscv-sodor index ebb45b9439..bbfc3c3510 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit ebb45b9439a19e2710ce0f2ee6e9ae2a192cbddf +Subproject commit bbfc3c35100329386314c49b62b49a7f42f65e87 diff --git a/generators/shuttle b/generators/shuttle index 924d269d1e..fd325d43a1 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit 924d269d1ef81adfeb263a3d898c82105f7d50ed +Subproject commit fd325d43a162378dc1984e87297e6d710167db79 From 686d9a5f44bd074e9e28790cd982ebade7a57def Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 18 Oct 2023 00:27:05 -0700 Subject: [PATCH 05/17] Bump rocket-chip --- generators/rocket-chip | 2 +- generators/tracegen/src/main/scala/System.scala | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index e0ea90344e..d48b45da56 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit e0ea90344e9edb6a4e24f84e7729d83c217c8859 +Subproject commit d48b45da568c0d370479325258018a8a5cf3369c diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 5d3953cb76..e7e3a03388 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -11,14 +11,22 @@ import boom.lsu.BoomTraceGenTile class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem with InstantiatesHierarchicalElements with HasTileNotificationSinks + with HasTileInputConstants + with HasHierarchicalElementsRootContext + with HasHierarchicalElements with CanHaveMasterAXI4MemPort { def coreMonitorBundles = Nil + val tileStatusNodes = totalTiles.values.toSeq.collect { case t: GroundTestTile => t.statusNode.makeSink() case t: BoomTraceGenTile => t.statusNode.makeSink() } - lazy val debugNode = IntSyncXbar() := NullIntSyncSource() + + lazy val clintOpt = None + lazy val debugOpt = None + lazy val plicOpt = None + override lazy val module = new TraceGenSystemModuleImp(this) } From 1d9dba517b6b0f4c21e7930a607f20dc51d8b316 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 18 Oct 2023 18:59:22 -0700 Subject: [PATCH 06/17] Fix unassigned clocks due to removing implicit clock from BaseSubsystem --- .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 3 +-- .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 + .../src/main/scala/example/dsptools/GenericFIR.scala | 7 ++++--- .../main/scala/example/dsptools/StreamingPassthrough.scala | 5 +++-- generators/fft-generator | 2 +- generators/icenet | 2 +- generators/rocket-chip | 2 +- generators/testchipip | 2 +- generators/tracegen/src/main/scala/System.scala | 2 ++ 9 files changed, 15 insertions(+), 11 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 1a85c9bb4e..1b5733c580 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -36,8 +36,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) - val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control"))) - prci_ctrl_domain.clockNode := tlbus.fixedClockNode + val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 0891a21dbb..140f74fb70 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -55,6 +55,7 @@ class AbstractConfig extends Config( new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus + new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 01d72d2476..df2ec35a6c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -199,12 +199,13 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p trait CanHavePeripheryStreamingFIR extends BaseSubsystem { val streamingFIR = p(GenericFIRKey) match { case Some(params) => { - val streamingFIR = LazyModule(new TLGenericFIRChain( + val domain = pbus.generateSynchronousDomain.suggestName("fir_domain") + val streamingFIR = domain { LazyModule(new TLGenericFIRChain( genIn = FixedPoint(8.W, 3.BP), genOut = FixedPoint(8.W, 3.BP), coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)), - params = params)) - pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } + params = params)) } + pbus.coupleTo("streamingFIR") { domain { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) } := _ } Some(streamingFIR) } case None => None diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 45e05fc253..a2259ab1c3 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -131,8 +131,9 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { - val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) - pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } + val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain") + val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) } + pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ } Some(streamingPassthroughChain) } case None => None diff --git a/generators/fft-generator b/generators/fft-generator index 811951b44a..4e7e6cbbbc 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit 811951b44a113f87710a6abaae4582120c1194ba +Subproject commit 4e7e6cbbbc6ed96d27dbaeb2413764cd446c50b3 diff --git a/generators/icenet b/generators/icenet index 18e88b5779..d6a471f218 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 18e88b5779ffdd7d75ca62cf9909f0ffc6fda95b +Subproject commit d6a471f2187c0671eea6567c7ba29e86e830e8d4 diff --git a/generators/rocket-chip b/generators/rocket-chip index d48b45da56..8881ccd1ca 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit d48b45da568c0d370479325258018a8a5cf3369c +Subproject commit 8881ccd1cab941ed0a0981c00361b1415027f8ce diff --git a/generators/testchipip b/generators/testchipip index 24de6bca03..9785c2662d 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 24de6bca032e730749535a75b37b30834cb23c28 +Subproject commit 9785c2662d8153477f004be10faec0037e9949e9 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index e7e3a03388..b25225c7d2 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -26,6 +26,8 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem lazy val clintOpt = None lazy val debugOpt = None lazy val plicOpt = None + lazy val clintDomainOpt = None + lazy val plicDomainOpt = None override lazy val module = new TraceGenSystemModuleImp(this) } From 127a7596296cea636dd891226f1c4544bcc31f62 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 20 Oct 2023 15:07:18 -0700 Subject: [PATCH 07/17] Bump rocket-chip --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 2 +- .../chipyard/src/main/scala/config/TracegenConfigs.scala | 3 ++- generators/rocket-chip | 2 +- generators/tracegen/src/main/scala/System.scala | 6 ++++-- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 140f74fb70..bc09862ef4 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -53,7 +53,7 @@ class AbstractConfig extends Config( // By default, punch out IOs to the Harness new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus"), Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 78c815fb99..77408a96ee 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -12,10 +12,11 @@ class AbstractTraceGenConfig extends Config( new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus"), Nil)) ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemClockIO ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++ + new chipyard.config.WithControlBusFrequency(1000.0) ++ new chipyard.config.WithSystemBusFrequency(1000.0) ++ new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ diff --git a/generators/rocket-chip b/generators/rocket-chip index 8881ccd1ca..0e88fc066e 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 8881ccd1cab941ed0a0981c00361b1415027f8ce +Subproject commit 0e88fc066e293b0da45da7360afd4cd3e6399678 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index b25225c7d2..488054d375 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -23,11 +23,13 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem case t: BoomTraceGenTile => t.statusNode.makeSink() } + lazy val fakeClockDomain = sbus.generateSynchronousDomain + lazy val clintOpt = None lazy val debugOpt = None lazy val plicOpt = None - lazy val clintDomainOpt = None - lazy val plicDomainOpt = None + lazy val clintDomainOpt = Some(fakeClockDomain) + lazy val plicDomainOpt = Some(fakeClockDomain) override lazy val module = new TraceGenSystemModuleImp(this) } From bbf37b2e4b1adeff5a35f6b654121873838b1c2f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 21 Oct 2023 12:38:21 -0700 Subject: [PATCH 08/17] Fix no-cores ibus null-connection --- generators/chipyard/src/main/scala/Subsystem.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 1a41ce8159..247a28c5ad 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -96,7 +96,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem intSink := intNexus :=* ibus.toPLIC // avoids a bug when there are no interrupt sources - ibus.fromAsync := NullIntSource() + ibus { ibus.fromAsync := NullIntSource() } // Need to have at least 1 driver to the tile notification sinks tileHaltXbarNode := IntSourceNode(IntSourcePortSimple()) From 2a6939cf0aff8f3107518188859ef05972a1f670 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 21 Oct 2023 14:15:32 -0700 Subject: [PATCH 09/17] Bump nvdla --- generators/nvdla | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/nvdla b/generators/nvdla index 730fad4360..95697452e5 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit 730fad4360e67b14b1a4656ac58aaa40cfd4fe6b +Subproject commit 95697452e51ad56230a6e631bb02b3351c4293c6 From 1e26618e8dab4a410a4d7c44994dff0c98d4bfbe Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 21 Oct 2023 15:48:01 -0700 Subject: [PATCH 10/17] Fix fpga platforms cbus freq --- fpga/src/main/scala/arty/Configs.scala | 1 + fpga/src/main/scala/arty100t/Configs.scala | 2 ++ fpga/src/main/scala/nexysvideo/Configs.scala | 4 +++- fpga/src/main/scala/vc707/Configs.scala | 2 ++ fpga/src/main/scala/vcu118/Configs.scala | 4 +++- 5 files changed, 11 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 3e208060c8..cfbb146cbc 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -28,6 +28,7 @@ class WithArtyTweaks extends Config( new chipyard.config.WithDTSTimebase(32000) ++ new chipyard.config.WithSystemBusFrequency(32) ++ new chipyard.config.WithPeripheryBusFrequency(32) ++ + new chipyard.config.WithControlBusFrequency(32) ++ new testchipip.WithNoSerialTL ) diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 4a0fb293a4..dbae2e3ba3 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -32,6 +32,7 @@ class WithArty100TTweaks extends Config( new chipyard.config.WithFrontBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithNoDebug ++ // no jtag @@ -62,5 +63,6 @@ class NoCoresArty100TConfig extends Config( new WithArty100TTweaks ++ new chipyard.config.WithMemoryBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithControlBusFrequency(50.0) ++ new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.NoCoresConfig) diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala index f31e38d111..7b8675009e 100644 --- a/fpga/src/main/scala/nexysvideo/Configs.scala +++ b/fpga/src/main/scala/nexysvideo/Configs.scala @@ -33,6 +33,7 @@ class WithNexysVideoTweaks extends Config( new chipyard.config.WithFrontBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithNoDebug ++ // no jtag @@ -59,6 +60,7 @@ class WithTinyNexysVideoTweaks extends Config( new chipyard.config.WithFrontBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithNoDebug ++ // no jtag @@ -69,4 +71,4 @@ class TinyRocketNexysVideoConfig extends Config( new WithTinyNexysVideoTweaks ++ new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.TinyRocketConfig) - // DOC include end: WithTinyNexysVideoTweaks and Rocket \ No newline at end of file + // DOC include end: WithTinyNexysVideoTweaks and Rocket diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index b37064ac9c..1d43da2cb5 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -45,6 +45,7 @@ class WithVC707Tweaks extends Config ( new chipyard.config.WithMemoryBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++ new WithFPGAFrequency(50) ++ // default 50MHz freq @@ -75,6 +76,7 @@ class BoomVC707Config extends Config ( class WithFPGAFrequency(fMHz: Double) extends Config ( new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. + new chipyard.config.WithControlBusFrequency(fMHz) ++ new chipyard.config.WithMemoryBusFrequency(fMHz) ) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 3563296130..e7ea046e54 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -47,6 +47,7 @@ class WithVCU118Tweaks extends Config( new chipyard.config.WithMemoryBusFrequency(100) ++ new chipyard.config.WithSystemBusFrequency(100) ++ new chipyard.config.WithPeripheryBusFrequency(100) ++ + new chipyard.config.WithControlBusFrequency(100) ++ new WithFPGAFrequency(100) ++ // default 100MHz freq // harness binders new WithUART ++ @@ -76,7 +77,8 @@ class BoomVCU118Config extends Config( class WithFPGAFrequency(fMHz: Double) extends Config( new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++ new chipyard.config.WithSystemBusFrequency(fMHz) ++ - new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. + new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ + new chipyard.config.WithControlBusFrequency(fMHz) ++ new chipyard.config.WithMemoryBusFrequency(fMHz) ) From 2ffd52e2db5e65525b7e9855a4fffb7e4ef9cc2f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 22 Oct 2023 14:08:51 -0700 Subject: [PATCH 11/17] Fix ChipBringupHostConfig cbus freq --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index cc61794cdb..4291ef37d1 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -85,6 +85,7 @@ class ChipBringupHostConfig extends Config( new chipyard.config.WithFrontBusFrequency(75.0) ++ // run all buses of this system at 75 MHz new chipyard.config.WithMemoryBusFrequency(75.0) ++ new chipyard.config.WithPeripheryBusFrequency(75.0) ++ + new chipyard.config.WithControlBusFrequency(75.0) ++ // Base is the no-cores config new chipyard.NoCoresConfig) From a4be70877143428a1b30acbe6a6366a077940799 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 22 Oct 2023 14:23:35 -0700 Subject: [PATCH 12/17] Fix firechip cbus freq --- generators/firechip/src/main/scala/TargetConfigs.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 6f2a02913d..66c1dc09d2 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -121,6 +121,7 @@ class WithFireSimHighPerfClocking extends Config( // This frequency selection matches FireSim's legacy selection and is required // to support 200Gb NIC performance. You may select a smaller value. new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ + new chipyard.config.WithControlBusFrequency(3200.0) ++ new chipyard.config.WithSystemBusFrequency(3200.0) ++ new chipyard.config.WithFrontBusFrequency(3200.0) ++ // Optional: These three configs put the DRAM memory system in it's own clock domain. @@ -140,6 +141,7 @@ class WithFireSimConfigTweaks extends Config( // to generate faithful DDR3 timing values. new chipyard.config.WithSystemBusFrequency(1000.0) ++ new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ + new chipyard.config.WithControlBusFrequency(1000.0) ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new WithFireSimDesignTweaks ) @@ -185,7 +187,8 @@ class WithFireSimTestChipConfigTweaks extends Config( new chipyard.config.WithTileFrequency(1000.0) ++ // Realistic tile frequency for a test chip new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately - new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus/pbus/cbus freqs + new chipyard.config.WithControlBusFrequency(500.0) ++ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ // Crossing specifications new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS @@ -247,6 +250,7 @@ class FireSimSmallSystemConfig extends Config( new WithDefaultMemModel ++ new WithBootROM ++ new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ + new chipyard.config.WithControlBusFrequency(3200.0) ++ new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ From b4d4e54f9ca9f6fd6d9e5c6201e8e349caae96e6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 24 Oct 2023 18:24:44 -0700 Subject: [PATCH 13/17] Bump fpga-shells --- fpga/fpga-shells | 2 +- fpga/src/main/scala/arty100t/Configs.scala | 2 +- fpga/src/main/scala/arty100t/Harness.scala | 4 ++-- fpga/src/main/scala/nexysvideo/Configs.scala | 2 +- fpga/src/main/scala/nexysvideo/Harness.scala | 4 ++-- fpga/src/main/scala/vc707/TestHarness.scala | 4 +++- fpga/src/main/scala/vcu118/CustomOverlays.scala | 4 ++-- fpga/src/main/scala/vcu118/TestHarness.scala | 5 +++-- fpga/src/main/scala/vcu118/bringup/TestHarness.scala | 2 +- 9 files changed, 16 insertions(+), 13 deletions(-) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 19e0e87ced..dec6398a5c 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 19e0e87cedd438f8231bb7af420cc58792735473 +Subproject commit dec6398a5c9bf7d9b80f12a9b991ee1a987337c6 diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index dbae2e3ba3..55ebcffb7d 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -18,7 +18,7 @@ import chipyard.{BuildSystem} // don't use FPGAShell's DesignKey class WithNoDesignKey extends Config((site, here, up) => { - case DesignKey => (p: Parameters) => new SimpleLazyModule()(p) + case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p) }) class WithArty100TTweaks extends Config( diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 47ffe7e089..4303a23e72 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -5,12 +5,12 @@ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink._ -import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} +import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem.{SystemBusKey} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} +import sifive.fpgashells.clocks._ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} import sifive.blocks.devices.uart._ diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala index 7b8675009e..751115ec01 100644 --- a/fpga/src/main/scala/nexysvideo/Configs.scala +++ b/fpga/src/main/scala/nexysvideo/Configs.scala @@ -18,7 +18,7 @@ import chipyard.{BuildSystem} // don't use FPGAShell's DesignKey class WithNoDesignKey extends Config((site, here, up) => { - case DesignKey => (p: Parameters) => new SimpleLazyModule()(p) + case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p) }) // DOC include start: WithNexysVideoTweaks and Rocket diff --git a/fpga/src/main/scala/nexysvideo/Harness.scala b/fpga/src/main/scala/nexysvideo/Harness.scala index 0cfb7110bb..cfc4b1cce1 100644 --- a/fpga/src/main/scala/nexysvideo/Harness.scala +++ b/fpga/src/main/scala/nexysvideo/Harness.scala @@ -7,10 +7,10 @@ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{SystemBusKey} - +import freechips.rocketchip.prci._ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} +import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart._ diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 008e23991e..75409697ac 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -7,11 +7,12 @@ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{SystemBusKey} import freechips.rocketchip.diplomacy.{IdRange, TransferSizes} +import freechips.rocketchip.prci._ import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay} import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} +import sifive.fpgashells.clocks.{PLLFactoryKey} import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO} @@ -88,6 +89,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She } class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators { + override def provideImplicitClockToLazyChildren = true val vc707Outer = _outer val reset = IO(Input(Bool())).suggestName("reset") diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala index 02669b7919..473a015d56 100644 --- a/fpga/src/main/scala/vcu118/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -5,7 +5,7 @@ import chisel3._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} - +import freechips.rocketchip.prci._ import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ @@ -79,7 +79,7 @@ class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, va ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst port.c0_sys_clk_i := sys.clock.asUInt port.sys_rst := sys.reset // pllReset - port.c0_ddr4_aresetn := !ar.reset + port.c0_ddr4_aresetn := !(ar.reset.asBool) // This was just copied from the SiFive example, but it's hard to follow. // The pins are emitted in the following order: diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 6bffc9a77c..09aef9d835 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -8,11 +8,11 @@ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy.{IdRange, TransferSizes} import freechips.rocketchip.subsystem.{SystemBusKey} - +import freechips.rocketchip.prci._ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} +import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} @@ -91,6 +91,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators { + override def provideImplicitClockToLazyChildren = true val vcu118Outer = _outer val reset = IO(Input(Bool())).suggestName("reset") diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 12398d8fdb..f2ead9ed57 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -5,7 +5,7 @@ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ - +import freechips.rocketchip.prci._ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell._ From ab1db16bdbbe764394fe4c53e0c8d9aabab6f83a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 24 Oct 2023 20:39:01 -0700 Subject: [PATCH 14/17] Bump rocket-chip --- generators/rocket-chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 0e88fc066e..59e86fd2ba 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 0e88fc066e293b0da45da7360afd4cd3e6399678 +Subproject commit 59e86fd2ba98b02a763dad2bd51b6324671ca2b1 From c5921ddef2f608c60eaab34250a1d56c35e2a520 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 15 Dec 2023 15:50:34 -0800 Subject: [PATCH 15/17] Bump rocket-chip --- generators/rocket-chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 59e86fd2ba..562ab1709f 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 59e86fd2ba98b02a763dad2bd51b6324671ca2b1 +Subproject commit 562ab1709f37a7e9cb4d52120cd3fe20d436e1f0 From 7c8de34904bd40361bcf3bf9a85c736c5229fa4d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 15 Dec 2023 17:20:48 -0800 Subject: [PATCH 16/17] Use Chipyard's hardfloat --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index c3be6161ef..47b3dbbaa6 100644 --- a/build.sbt +++ b/build.sbt @@ -95,7 +95,7 @@ lazy val chiselSettings = Seq( // -- Rocket Chip -- -lazy val hardfloat = freshProject("hardfloat", rocketChipDir / "hardfloat/hardfloat") +lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat")) .settings(chiselSettings) .dependsOn(midasTargetUtils) .settings(commonSettings) From 5bc9aea8daa4418f41edf7722629033a87b044c7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 9 Jan 2024 13:51:55 -0800 Subject: [PATCH 17/17] Bump rc-inclusive-cache --- generators/rocket-chip-inclusive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache index bcd248a2a2..1332d2268a 160000 --- a/generators/rocket-chip-inclusive-cache +++ b/generators/rocket-chip-inclusive-cache @@ -1 +1 @@ -Subproject commit bcd248a2a2e86084a136c05d1844d88d9fba18e5 +Subproject commit 1332d2268ae01b2b311966d53a3ee0d930e83f07