From 583801ed053ac7705ba54f6ca088420785d1bc65 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 23 Oct 2019 00:07:49 +0000 Subject: [PATCH 01/25] gemmini submodule --- .gitmodules | 3 +++ build.sbt | 6 +++++- generators/gemmini | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) create mode 160000 generators/gemmini diff --git a/.gitmodules b/.gitmodules index 282dc73109..688b8778ad 100644 --- a/.gitmodules +++ b/.gitmodules @@ -98,3 +98,6 @@ [submodule "tools/axe"] path = tools/axe url = https://github.com/CTSRD-CHERI/axe.git +[submodule "generators/gemmini"] + path = generators/gemmini + url = https://github.com/ucb-bar/gemmini diff --git a/build.sbt b/build.sbt index ae77dead3f..4680046a29 100644 --- a/build.sbt +++ b/build.sbt @@ -120,7 +120,7 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val example = conditionalDependsOn(project in file("generators/example")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -147,6 +147,10 @@ lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, chisel_testers, midasTargetUtils) .settings(commonSettings) +lazy val gemmini = (project in file("generators/gemmini")) + .dependsOn(rocketchip, chisel_testers) + .settings(commonSettings) + lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) .dependsOn(chisel_testers, example) .settings(commonSettings) diff --git a/generators/gemmini b/generators/gemmini new file mode 160000 index 0000000000..23e4fd82d1 --- /dev/null +++ b/generators/gemmini @@ -0,0 +1 @@ +Subproject commit 23e4fd82d18b63d6e9b0e1cd0e841b426de21bef From 8cdf95d3ba09289872aaee80ab5bbf41437343c5 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 23 Oct 2019 01:21:13 +0000 Subject: [PATCH 02/25] fix build.sbt --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 4680046a29..ad391dd4c7 100644 --- a/build.sbt +++ b/build.sbt @@ -148,7 +148,7 @@ lazy val sha3 = (project in file("generators/sha3")) .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(rocketchip, chisel_testers) + .dependsOn(rocketchip, chisel_testers, testchipip) .settings(commonSettings) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) From cfc6678de4be256f69ebca41d072673312b8077b Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 23 Oct 2019 04:29:02 +0000 Subject: [PATCH 03/25] firechip gemmini config --- .../firechip/src/main/scala/TargetConfigs.scala | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 37df379965..9e36a59070 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -208,6 +208,18 @@ class FireSimRocketBoomConfig extends Config( new FireSimBoomConfig ) +//********************************************************************************** +//* Gemmini Configurations +//*********************************************************************************/ + +// Gemmini systolic accelerator default config +class FireSimRocketChipGemminiL2Config extends Config( + new WithInclusiveCache ++ + new gemmini.DefaultGemminiConfig ++ + new WithNBigCores(1) ++ + new FireSimRocketChipConfig) + + //********************************************************************************** //* Supernode Configurations //*********************************************************************************/ From b53ba304cfc40f8d1bc28b5a14a213acb7f677d7 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 26 Oct 2019 04:21:52 +0000 Subject: [PATCH 04/25] bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 23e4fd82d1..0bc2021ef1 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 23e4fd82d18b63d6e9b0e1cd0e841b426de21bef +Subproject commit 0bc2021ef14600918e045dcb409babdd4216beb8 From 9c9b797a9d845b59e3617e912f1ac5bba492e966 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 19 Nov 2019 18:52:14 +0000 Subject: [PATCH 05/25] bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 0bc2021ef1..c6851123d7 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 0bc2021ef14600918e045dcb409babdd4216beb8 +Subproject commit c6851123d7417edfe0e6796bb3d1679960029f91 From 33f8480099d2cecc26150e54e2a9e73beac42e73 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 19 Nov 2019 23:35:48 +0000 Subject: [PATCH 06/25] bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index c6851123d7..56e9fa97dc 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit c6851123d7417edfe0e6796bb3d1679960029f91 +Subproject commit 56e9fa97dcbcdd5c0a3f1204b67c452550ef19ac From 9c7569d70dd536d4d212030b2a6e107463578f74 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 25 Nov 2019 08:05:23 +0000 Subject: [PATCH 07/25] fix hwacha typo --- docs/Generators/Hwacha.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Generators/Hwacha.rst b/docs/Generators/Hwacha.rst index 240d6fc948..ac4f4fdfd8 100644 --- a/docs/Generators/Hwacha.rst +++ b/docs/Generators/Hwacha.rst @@ -11,5 +11,5 @@ To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwac To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala `__ to see the possible configuration parameters. -Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and asseble its vector instructions. +Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions. To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it. From d9ce7dacc4fc32c5733f5ad916938763bb7d63f0 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 26 Nov 2019 17:09:36 +0000 Subject: [PATCH 08/25] start gemmini docs --- docs/Generators/Gemmini.rst | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 docs/Generators/Gemmini.rst diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst new file mode 100644 index 0000000000..5555f9ba6d --- /dev/null +++ b/docs/Generators/Gemmini.rst @@ -0,0 +1,42 @@ +Gemmini +==================================== + +The Gemmini project is developing a systolic-array based matrix multipication acceleration generation for the investigration of SoC integration of such accelerators. It is inspired by recent trends in machine learning accelerators for edge and mobile SoCs. + +Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. + +To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config mixin to the SoC configurations. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). + +To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``. You can view the ``DefaultGemminiConfig`` under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. + + +TODO: Block Diagram Figure + + +Software +------------------ + +The Gemmini accelerator includes a C matrix multipication library which wraps the calls to the custom Gemmini instructions. +This library can be found under the ``software`` directory of the generator. + +The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multipcation library to tune library performance. + + + + +The Gemmini generator includes a custom implementation of the Spike functional ISA simulator. This implementation is based on the ``esp-tools`` Spike implementation that is mixed with the Hwacha vector accelerator + + +Generator Parameters +-------------------------- + +Major parameters of interest include: + +* Systolic array dimensions (``tileRows``, ``tileColumns``, ``meshRows``, ``meshColumns``) - The systolic array is composed of a 2-level hierarchy, in which each tile is fully combinational, while a mesh of tiles + + +* Access-execute queue parameters (``ld_queue_length``, ``st_queue_length``, ``ex_queue_length``) - To implement access-execute decoupling, a Gemmini accelerator has a load instruction queue, and store instruction queue and an execute instruction queue. The relative sizes of these queue determines the level of access-execute decoupling. + +* + +* Scratchpad memory parameters - From 22b3d0fee2325624fe42d4753c4d40f46ac26e64 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 26 Nov 2019 17:09:48 +0000 Subject: [PATCH 09/25] bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 56e9fa97dc..39b40853f0 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 56e9fa97dcbcdd5c0a3f1204b67c452550ef19ac +Subproject commit 39b40853f0c931aaa0577d5e4bf90238c9f978d9 From cfe591cab7e6e01ae1362828da1a79066f943ac8 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sun, 1 Dec 2019 00:13:59 -0800 Subject: [PATCH 10/25] gemmini docs --- docs/Generators/Gemmini.rst | 39 +++++++++++------- docs/Generators/index.rst | 1 + docs/_static/images/gemmini-system.png | Bin 0 -> 115294 bytes .../_static/images/gemmini-systolic-array.png | Bin 0 -> 113148 bytes .../src/main/scala/RocketConfigs.scala | 8 ++++ 5 files changed, 32 insertions(+), 16 deletions(-) create mode 100644 docs/_static/images/gemmini-system.png create mode 100644 docs/_static/images/gemmini-systolic-array.png diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index 5555f9ba6d..0f397d2eeb 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -1,42 +1,49 @@ Gemmini ==================================== -The Gemmini project is developing a systolic-array based matrix multipication acceleration generation for the investigration of SoC integration of such accelerators. It is inspired by recent trends in machine learning accelerators for edge and mobile SoCs. +The Gemmini project is developing a systolic-array based matrix multiplication acceleration generation for the investigation of SoC integration of such accelerators. It is inspired by recent trends in machine learning accelerators for edge and mobile SoCs. Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config mixin to the SoC configurations. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). -To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``. You can view the ``DefaultGemminiConfig`` under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. +To change the configuration of the Gemmini accelerator unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``. You can view the ``DefaultGemminiConfig`` under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. +.. image:: ../_static/images/gemmini-system.png -TODO: Block Diagram Figure +Generator Parameters +-------------------------- +Major parameters of interest include: -Software ------------------- +* Systolic array dimensions (``tileRows``, ``tileColumns``, ``meshRows``, ``meshColumns``) - The systolic array is composed of a 2-level hierarchy, in which each tile is fully combinational, while a mesh of tiles -The Gemmini accelerator includes a C matrix multipication library which wraps the calls to the custom Gemmini instructions. -This library can be found under the ``software`` directory of the generator. +.. image:: ../_static/images/gemmini-systolic-array.png -The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multipcation library to tune library performance. +* Access-execute queue parameters (``ld_queue_length``, ``st_queue_length``, ``ex_queue_length``, ``rob_entries``) - To implement access-execute decoupling, a Gemmini accelerator has a load instruction queue, and store instruction queue and an execute instruction queue. The relative sizes of these queue determine the level of access-execute decoupling. Gemmini also implements a reorder buffer (ROB) - the number of entries in the ROB determines possible dependency management limitations. +* DMA parameters (``dma_maxbytes``, ``dma_buswidth``, ``mem_pipeline``) - Gemmini implements a DMA to move data from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory. The size of these DMA transactions is determined by the DMA parameters. These DMA parameters are tightly coupled with Rocket Chip SoC system parameters: in particular ``dma_buswidth`` is associated with the ``SystemBusKey`` ``beatBytes`` parameter, and ``dma_maxbytes`` is associated with ``cacheblockbytes`` Rocket Chip parameters. +* Scratchpad and accumulator memory parameters (``sp_banks``, ``sp_capacity``, ``acc_capacity``) - Determine the properties of the Gemmini scratchpad memory: overall capacity of the scratchpad or accumulators (in KiB), and the number of banks the scratchpad is divided into. +* Type parameters (``inputType``, ``outputType``, ``accType``) - Determine the data-types flowing through different parts of a Gemmini accelerator. -The Gemmini generator includes a custom implementation of the Spike functional ISA simulator. This implementation is based on the ``esp-tools`` Spike implementation that is mixed with the Hwacha vector accelerator +* Other system parameter (``shifter_banks``, ``dataflow``, ``aligned_to``) -Generator Parameters --------------------------- +Software +------------------ -Major parameters of interest include: +The Gemmini non-standard ISA extension is specified in the `Gemmini repository `__ +The instruction included configuration instructions, data movement instructions (from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory), and matrix multiplication execution instructions. -* Systolic array dimensions (``tileRows``, ``tileColumns``, ``meshRows``, ``meshColumns``) - The systolic array is composed of a 2-level hierarchy, in which each tile is fully combinational, while a mesh of tiles +Since Gemmini instructions are not exposed through the GNU binutils assembler, several C macros are provided in order to construct the instruction encodings to call these instructions. + +The Gemmini generator includes a C matrix multiplication library which wraps the calls to the custom Gemmini instructions. +The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/systolic.h`` file. +The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/systolic_params.h`` -* Access-execute queue parameters (``ld_queue_length``, ``st_queue_length``, ``ex_queue_length``) - To implement access-execute decoupling, a Gemmini accelerator has a load instruction queue, and store instruction queue and an execute instruction queue. The relative sizes of these queue determines the level of access-execute decoupling. +The Gemmini generator implements a custom non-standard version of the Spike functional ISA simulator. This implementation is based on the ``esp-tools`` Spike implementation that is mixed with the Hwacha vector accelerator. Is is currently as separate branch within the ``esp-tools`` Spike repository, but it is in the process of upstreaming to the main ``esp-tools`` branch. -* -* Scratchpad memory parameters - diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 5aa097b69b..5bb5d4911c 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -22,6 +22,7 @@ so changes to the generators themselves will automatically be used when building Rocket BOOM Hwacha + Gemmini IceNet TestChipIP SiFive-Generators diff --git a/docs/_static/images/gemmini-system.png b/docs/_static/images/gemmini-system.png new file mode 100644 index 0000000000000000000000000000000000000000..df44708fbec06198924698a47f0444ad1557a645 GIT binary patch literal 115294 zcmeGEbx>Pv_dg2PDaA@D(4xg1O0nV9uQD*>X}Z)!hs?XFR<|oSG#uY)FHjoe`%mh|;#WS#4pT#cPYyBXfUY ztRuUnpMNC({8?X0{l0WDr=MGX3Awtq`mLAJD)t)dw;$?%cHH~S`ovHFp~?@k+cg@x z8L}Mn31>@jNj;27NgvE4l8g-dC1acUl3b(ZB)S?`VwAmtLqq;vtdO$g*HVA4SUK%p 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Add quick-build instructions to Gemmini RST --- docs/Generators/Gemmini.rst | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index 0f397d2eeb..c79a6966af 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -3,11 +3,16 @@ Gemmini The Gemmini project is developing a systolic-array based matrix multiplication acceleration generation for the investigation of SoC integration of such accelerators. It is inspired by recent trends in machine learning accelerators for edge and mobile SoCs. -Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. +Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the System Bus (i.e., directly to the L2 cache). -To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config mixin to the SoC configurations. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). +To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config mixin to the SoC configurations. To change the configuration of the Gemmini accelerator unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``, which you can view under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. -To change the configuration of the Gemmini accelerator unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``. You can view the ``DefaultGemminiConfig`` under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. +Alternatively, to build our example Gemmini-equipped SoC simulator, run the following commands: + +.. code-block:: shell + + cd sims/vcs # or "cd sims/verilator" + make CONFIG=GemminiAcceleratorConfig CONFIG_PACKAGE=gemmini MODEL_PACKAGE=freechips.rocketchip.system GENERATOR_PACKAGE=freechips.rocketchip.system TOP=ExampleRocketSystem .. image:: ../_static/images/gemmini-system.png @@ -16,26 +21,25 @@ Generator Parameters Major parameters of interest include: -* Systolic array dimensions (``tileRows``, ``tileColumns``, ``meshRows``, ``meshColumns``) - The systolic array is composed of a 2-level hierarchy, in which each tile is fully combinational, while a mesh of tiles +* Systolic array dimensions (``tileRows``, ``tileColumns``, ``meshRows``, ``meshColumns``): The systolic array is composed of a 2-level hierarchy, in which each tile is fully combinational, while a mesh of tiles has pipeline registers between each tile. .. image:: ../_static/images/gemmini-systolic-array.png -* Access-execute queue parameters (``ld_queue_length``, ``st_queue_length``, ``ex_queue_length``, ``rob_entries``) - To implement access-execute decoupling, a Gemmini accelerator has a load instruction queue, and store instruction queue and an execute instruction queue. The relative sizes of these queue determine the level of access-execute decoupling. Gemmini also implements a reorder buffer (ROB) - the number of entries in the ROB determines possible dependency management limitations. +* Dataflow parameters (``dataflow``): Determine whether the systolic array in Gemmini is output-stationary or weight-stationary, or whether it supports both dataflows so that programmers may choose between them at runtime. -* DMA parameters (``dma_maxbytes``, ``dma_buswidth``, ``mem_pipeline``) - Gemmini implements a DMA to move data from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory. The size of these DMA transactions is determined by the DMA parameters. These DMA parameters are tightly coupled with Rocket Chip SoC system parameters: in particular ``dma_buswidth`` is associated with the ``SystemBusKey`` ``beatBytes`` parameter, and ``dma_maxbytes`` is associated with ``cacheblockbytes`` Rocket Chip parameters. +* Scratchpad and accumulator memory parameters (``sp_banks``, ``sp_capacity``, ``acc_capacity``): Determine the properties of the Gemmini scratchpad memory: overall capacity of the scratchpad or accumulators (in KiB), and the number of banks the scratchpad is divided into. -* Scratchpad and accumulator memory parameters (``sp_banks``, ``sp_capacity``, ``acc_capacity``) - Determine the properties of the Gemmini scratchpad memory: overall capacity of the scratchpad or accumulators (in KiB), and the number of banks the scratchpad is divided into. +* Type parameters (``inputType``, ``outputType``, ``accType``): Determine the data-types flowing through different parts of a Gemmini accelerator. For example, ``inputType`` may be an 8-bit fixed-point number, while ``accType``, which determines the type of partial accumulations in a matrix multiplication, may be a 32-bit integer. ``outputType`` only determines the type of the data passed between two processing elements (PEs); for example, an 8-bit multiplication may produce a 16-bit result which must be shared between PEs in a systolic array. -* Type parameters (``inputType``, ``outputType``, ``accType``) - Determine the data-types flowing through different parts of a Gemmini accelerator. - -* Other system parameter (``shifter_banks``, ``dataflow``, ``aligned_to``) +* Access-execute queue parameters (``ld_queue_length``, ``st_queue_length``, ``ex_queue_length``, ``rob_entries``): To implement access-execute decoupling, a Gemmini accelerator has a load instruction queue, a store instruction queue, and an execute instruction queue. The relative sizes of these queue determine the level of access-execute decoupling. Gemmini also implements a reorder buffer (ROB) - the number of entries in the ROB determines possible dependency management limitations. +* DMA parameters (``dma_maxbytes``, ``dma_buswidth``, ``mem_pipeline``): Gemmini implements a DMA to move data from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory. The size of these DMA transactions is determined by the DMA parameters. These DMA parameters are tightly coupled with Rocket Chip SoC system parameters: in particular ``dma_buswidth`` is associated with the ``SystemBusKey`` ``beatBytes`` parameter, and ``dma_maxbytes`` is associated with ``cacheblockbytes`` Rocket Chip parameters. Software ------------------ -The Gemmini non-standard ISA extension is specified in the `Gemmini repository `__ -The instruction included configuration instructions, data movement instructions (from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory), and matrix multiplication execution instructions. +The Gemmini non-standard ISA extension is specified in the `Gemmini repository `__. +The ISA includes configuration instructions, data movement instructions (from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory), and matrix multiplication execution instructions. Since Gemmini instructions are not exposed through the GNU binutils assembler, several C macros are provided in order to construct the instruction encodings to call these instructions. @@ -44,6 +48,5 @@ The ``software`` directory of the generator includes the aforementioned library The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/systolic_params.h`` -The Gemmini generator implements a custom non-standard version of the Spike functional ISA simulator. This implementation is based on the ``esp-tools`` Spike implementation that is mixed with the Hwacha vector accelerator. Is is currently as separate branch within the ``esp-tools`` Spike repository, but it is in the process of upstreaming to the main ``esp-tools`` branch. - +The Gemmini generator implements a custom non-standard version of the Spike functional ISA simulator. This implementation is based on the ``esp-tools`` Spike implementation that is mixed with the Hwacha vector accelerator. Is is currently a separate branch within the ``esp-tools`` Spike repository, but it is in the process of upstreaming to the main ``esp-tools`` branch. From da445fe6cfe6b962d4d61bf39801970d9ca61294 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 5 Dec 2019 23:26:07 -0800 Subject: [PATCH 12/25] start gemmini CI --- .circleci/config.yml | 62 ++++++++++++++++++++++++++++++++++++++++++ .circleci/defaults.sh | 1 + .circleci/run-tests.sh | 18 ++++++++++++ 3 files changed, 81 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index d6d8097bef..c54e1a6377 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -288,6 +288,35 @@ jobs: key: hwacha-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" + prepare-gemmini: + docker: + - image: riscvboom/riscvboom-images:0.0.12 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + steps: + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" + - checkout + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + - restore_cache: + keys: + - esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} + - run: + name: Building the gemmini subproject using Verilator + command: .circleci/do-rtl-build.sh gemmini + no_output_timeout: 120m + - save_cache: + key: gemmini-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" prepare-tracegen: docker: - image: riscvboom/riscvboom-images:0.0.12 @@ -516,6 +545,30 @@ jobs: - run: name: Run hwacha tests command: .circleci/run-tests.sh hwacha + gemmini-run-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.12 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + steps: + - checkout + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + - restore_cache: + keys: + - esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }} + - restore_cache: + keys: + - gemmini-{{ .Branch }}-{{ .Revision }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} + - run: + name: Run gemmini tests + command: .circleci/run-tests.sh gemmini tracegen-run-tests: docker: - image: riscvboom/riscvboom-images:0.0.12 @@ -658,6 +711,11 @@ workflows: - install-esp-toolchain - install-verilator + - prepare-gemmini: + requires: + - install-esp-toolchain + - install-verilator + - prepare-tracegen: requires: - install-riscv-toolchain @@ -702,6 +760,10 @@ workflows: requires: - prepare-hwacha + - gemmini-run-tests: + requires: + - prepare-gemmini + - tracegen-run-tests: requires: - prepare-tracegen diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index ffd45ffb6b..87a761d933 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,6 +47,7 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig" +mapping["gemmini"]="SUB_PROJECT=example CONFIG=GemminiRocketConfig" mapping["tracegen"]="SUB_PROJECT=tracegen CONFIG=NonBlockingTraceGenL2Config" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 138e27855a..a7617cae58 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -50,6 +50,24 @@ case $1 in export PATH=$RISCV/bin:$PATH make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} ;; + gemmini) + export RISCV=$LOCAL_ESP_DIR + export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib + export PATH=$RISCV/bin:$PATH + GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests + # TODO: (Alon) Write the test execution command within the verilator directory + # enable error on first non-zero error code + #set -e + cd $GEMMINI_SOFTWARE_DIR + ./build.sh + cd $LOCAL_SIM_DIR + $LOCAL_SIM_DIR/simv-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal + $LOCAL_SIM_DIR/simv-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal + $LOCAL_SIM_DIR/simv-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + # check error code $? + # disable error on first non-zero error code + #set +e + ;; tracegen) run_tracegen ${mapping[$1]} ;; From d2aef03d72a85a49de3c301ecbc3a84617913a7b Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 5 Dec 2019 23:27:57 -0800 Subject: [PATCH 13/25] bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 39b40853f0..1d4c5fe336 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 39b40853f0c931aaa0577d5e4bf90238c9f978d9 +Subproject commit 1d4c5fe33650769cdc18d3d6970d9898e0158caf From 383dacaceea7f768639ec3c2c76cb69edcbe9bf7 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 6 Dec 2019 16:16:01 -0800 Subject: [PATCH 14/25] gemmini CI fixes --- .circleci/check-commit.sh | 2 +- .circleci/do-firesim-build.sh | 2 +- .circleci/do-rtl-build.sh | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index dbf2a718bf..02f40ace17 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("boom" "hwacha" "icenet" "sha3" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip") +submodules=("boom" "hwacha" "icenet" "sha3" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip" "gemmini") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then diff --git a/.circleci/do-firesim-build.sh b/.circleci/do-firesim-build.sh index 5eb42e56d2..8114355f24 100755 --- a/.circleci/do-firesim-build.sh +++ b/.circleci/do-firesim-build.sh @@ -34,7 +34,7 @@ TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib VERILATOR_BIN_DIR=$REMOTE_VERILATOR_DIR/install/bin -if [ $1 = "hwacha" ]; then +if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib run "mkdir -p $REMOTE_ESP_DIR" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 50f9ce943b..dd667dfb41 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -32,7 +32,7 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -if [ $1 = "hwacha" ]; then +if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib run "mkdir -p $REMOTE_ESP_DIR" From ddfc6b35a9858b1b575288ac697ec4c5bf791d42 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sun, 8 Dec 2019 16:31:52 -0800 Subject: [PATCH 15/25] bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 1d4c5fe336..4850af0ca4 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 1d4c5fe33650769cdc18d3d6970d9898e0158caf +Subproject commit 4850af0ca4a6f727e968081f6bdda6cced87adfc From 6820accdf19bd8ac5668429c3de8e0fc07be3a12 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sun, 8 Dec 2019 21:43:47 -0800 Subject: [PATCH 16/25] fix simulator name in gemmini CI --- .circleci/run-tests.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index a7617cae58..f5205b3977 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -61,9 +61,9 @@ case $1 in cd $GEMMINI_SOFTWARE_DIR ./build.sh cd $LOCAL_SIM_DIR - $LOCAL_SIM_DIR/simv-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - $LOCAL_SIM_DIR/simv-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - $LOCAL_SIM_DIR/simv-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal + $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal + $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal # check error code $? # disable error on first non-zero error code #set +e From 48eb3665c647ae2d09259e481a5cce5d550f0203 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 9 Dec 2019 10:32:31 -0800 Subject: [PATCH 17/25] cleanup gemmini CI --- .circleci/run-tests.sh | 6 ------ 1 file changed, 6 deletions(-) diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index f5205b3977..97789b4cb9 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -55,18 +55,12 @@ case $1 in export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests - # TODO: (Alon) Write the test execution command within the verilator directory - # enable error on first non-zero error code - #set -e cd $GEMMINI_SOFTWARE_DIR ./build.sh cd $LOCAL_SIM_DIR $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal - # check error code $? - # disable error on first non-zero error code - #set +e ;; tracegen) run_tracegen ${mapping[$1]} From 766bf9d5fbe2d98d9a10a4b743793a3f2b68b735 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 10 Dec 2019 10:57:44 -0800 Subject: [PATCH 18/25] bump esp-isa-sim to include gemmini --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 0ffa02e5b4..5965f8fcdb 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 0ffa02e5b4ca57ec44684119a1a9a31b3871857b +Subproject commit 5965f8fcdbe931d6f8acabdea53c1e3a7b54e3f4 From 6ff23d28b8b0f06fef3721ad75a692edb8ac61dc Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 10 Dec 2019 11:29:43 -0800 Subject: [PATCH 19/25] update gemmini docs --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 2 + docs/Generators/Gemmini.rst | 39 ++++++++++++++++--- .../src/main/scala/RocketConfigs.scala | 2 + 3 files changed, 37 insertions(+), 6 deletions(-) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index ad5f1abd70..1ab06c7a02 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -21,6 +21,8 @@ After cloning this repo, you will need to initialize all of the submodules. cd chipyard ./scripts/init-submodules-no-riscv-tools.sh +.. _build-toolchains: + Building a Toolchain ------------------------ diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index c79a6966af..2ac3ba0eeb 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -1,18 +1,25 @@ Gemmini ==================================== -The Gemmini project is developing a systolic-array based matrix multiplication acceleration generation for the investigation of SoC integration of such accelerators. It is inspired by recent trends in machine learning accelerators for edge and mobile SoCs. +The Gemmini project is developing a systolic-array based matrix multiplication unit generator for the investigation of software/hardware implications of such integrated SoC accelerators. It is inspired by recent trends in machine learning accelerators for edge and mobile SoCs. Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the System Bus (i.e., directly to the L2 cache). To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config mixin to the SoC configurations. To change the configuration of the Gemmini accelerator unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``, which you can view under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. -Alternatively, to build our example Gemmini-equipped SoC simulator, run the following commands: +The example Chipyard config includes the following example SoC configuration which includes Gemmini: + +.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala + :language: scala + :start-after: DOC include start: GemminiRocketConfig + :end-before: DOC include end: GemminiRocketConfig + +To build a simulation of this example Chipyard config, run the following commands: .. code-block:: shell cd sims/vcs # or "cd sims/verilator" - make CONFIG=GemminiAcceleratorConfig CONFIG_PACKAGE=gemmini MODEL_PACKAGE=freechips.rocketchip.system GENERATOR_PACKAGE=freechips.rocketchip.system TOP=ExampleRocketSystem + make CONFIG=GemminiRocketConfig .. image:: ../_static/images/gemmini-system.png @@ -44,9 +51,29 @@ The ISA includes configuration instructions, data movement instructions (from ma Since Gemmini instructions are not exposed through the GNU binutils assembler, several C macros are provided in order to construct the instruction encodings to call these instructions. The Gemmini generator includes a C matrix multiplication library which wraps the calls to the custom Gemmini instructions. -The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/systolic.h`` file. +The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/gemmini.h`` file. + +The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` + +The Gemmini generator implements a custom non-standard version of the Spike functional ISA simulator. This implementation is found within the ``esp-tools`` Spike implementation, together with the Hwacha vector accelerator non-standard ISA-extension. In order to use this version of Spike, please make sure to build the ``esp-tools`` software toolchain, as describes in :ref:`build-toolchains`. + +In order to run Spike with the gemmini functional model, you will need to use the ``--extension=gemmini`` flag. For example: + +.. code-block:: shell + + spike --extension=gemmini -The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/systolic_params.h`` +Spike is build by default with now commit log. However, if you would like to add detailed functional log of gemmini operation to the spike model, you can rebuild spike manually (based on the instructions in the ``esp-tools/riscv-isa-sim/README`` file), with the ``--enable-gemminicommitlog`` option added to the ``configure`` step. -The Gemmini generator implements a custom non-standard version of the Spike functional ISA simulator. This implementation is based on the ``esp-tools`` Spike implementation that is mixed with the Hwacha vector accelerator. Is is currently a separate branch within the ``esp-tools`` Spike repository, but it is in the process of upstreaming to the main ``esp-tools`` branch. + +Alternative SoC Configs +-------------------------- + +The Gemmini generator includes additional alternative SoC configs (configs that are not in the Chipyard example project). +If you would like to build one of these alternative SoC configurations which are defined in within the Gemmini project repository, you can run the following commands. This commands are similar to the one required when building a simulation from the example project, but there specify that the location of the configs are in the Gemmini subproject, as opposed to the chipyard example project: + +.. code-block:: shell + + cd sims/vcs # or "cd sims/verilator" + make CONFIG=GemminiAcceleratorConfig CONFIG_PACKAGE=gemmini MODEL_PACKAGE=freechips.rocketchip.system GENERATOR_PACKAGE=freechips.rocketchip.system TOP=ExampleRocketSystem diff --git a/generators/example/src/main/scala/RocketConfigs.scala b/generators/example/src/main/scala/RocketConfigs.scala index 59b502a6a7..377b399531 100644 --- a/generators/example/src/main/scala/RocketConfigs.scala +++ b/generators/example/src/main/scala/RocketConfigs.scala @@ -23,6 +23,7 @@ class HwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +// DOC include start: GemminiRocketConfig class GemminiRocketConfig extends Config( new WithTop ++ new WithBootROM ++ @@ -30,6 +31,7 @@ class GemminiRocketConfig extends Config( new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +// DOC include end: GemminiRocketConfig class RoccRocketConfig extends Config( new WithTop ++ From 219ab452cf15592ff8f21173d52e9da40b91d574 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 10 Dec 2019 23:13:06 -0800 Subject: [PATCH 20/25] [ci skip] fix gemmini docs typos --- docs/Generators/Gemmini.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index 2ac3ba0eeb..c879da7e7e 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -63,14 +63,14 @@ In order to run Spike with the gemmini functional model, you will need to use th spike --extension=gemmini -Spike is build by default with now commit log. However, if you would like to add detailed functional log of gemmini operation to the spike model, you can rebuild spike manually (based on the instructions in the ``esp-tools/riscv-isa-sim/README`` file), with the ``--enable-gemminicommitlog`` option added to the ``configure`` step. +Spike is built by default without a commit log. However, if you would like to add detailed functional log of gemmini operation to the spike model, you can rebuild spike manually (based on the instructions in the ``esp-tools/riscv-isa-sim/README`` file), with the ``--enable-gemminicommitlog`` option added to the ``configure`` step. Alternative SoC Configs -------------------------- The Gemmini generator includes additional alternative SoC configs (configs that are not in the Chipyard example project). -If you would like to build one of these alternative SoC configurations which are defined in within the Gemmini project repository, you can run the following commands. This commands are similar to the one required when building a simulation from the example project, but there specify that the location of the configs are in the Gemmini subproject, as opposed to the chipyard example project: +If you would like to build one of these alternative SoC configurations which are defined in within the Gemmini project repository, you can run the following commands. These commands are similar to the one required when building a simulation from the example project, but they specify that the location of the configs are in the Gemmini subproject, as opposed to the Chipyard example project: .. code-block:: shell From 182b1d3d7486c9ce3deaa34ca81ecc1db7cf4c85 Mon Sep 17 00:00:00 2001 From: Hasan Genc Date: Wed, 11 Dec 2019 02:44:40 -0800 Subject: [PATCH 21/25] Update Gemmini.rst Add instructions on building Gemmini programs, or writing your own programs. --- docs/Generators/Gemmini.rst | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index c879da7e7e..fb5cae3e75 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -18,7 +18,7 @@ To build a simulation of this example Chipyard config, run the following command .. code-block:: shell - cd sims/vcs # or "cd sims/verilator" + cd sims/verilator # or "cd sims/vcs" make CONFIG=GemminiRocketConfig .. image:: ../_static/images/gemmini-system.png @@ -55,7 +55,19 @@ The ``software`` directory of the generator includes the aforementioned library The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` -The Gemmini generator implements a custom non-standard version of the Spike functional ISA simulator. This implementation is found within the ``esp-tools`` Spike implementation, together with the Hwacha vector accelerator non-standard ISA-extension. In order to use this version of Spike, please make sure to build the ``esp-tools`` software toolchain, as describes in :ref:`build-toolchains`. +Build and Run Gemmini Programs +^^^^^^^^^^^^^^^^^^^^^^^^^ + +To build pre-packaged Gemmini programs: + +.. code-block:: shell + + cd generators/gemmini/software/gemmini-rocc-tests/ + ./build.sh + +Afterwards, the program binaries will be found in ``generators/gemmini/software/gemmini-rocc-tests/build``. Binaries whose names end in ``-baremetal`` are meant to be run in a bare-metal environment, while binaries whose names end in ``-linux`` are meant to run in a Linux environment. You can run the programs either on a cycle-accurate RTL simulator, or on a (much faster) functional ISA simulator called Spike. + +The Gemmini generator implements a custom non-standard version of Spike. This implementation is found within the ``esp-tools`` Spike implementation, together with the Hwacha vector accelerator non-standard ISA-extension. In order to use this version of Spike, please make sure to build the ``esp-tools`` software toolchain, as described in :ref:`build-toolchains`. In order to run Spike with the gemmini functional model, you will need to use the ``--extension=gemmini`` flag. For example: @@ -65,6 +77,20 @@ In order to run Spike with the gemmini functional model, you will need to use th Spike is built by default without a commit log. However, if you would like to add detailed functional log of gemmini operation to the spike model, you can rebuild spike manually (based on the instructions in the ``esp-tools/riscv-isa-sim/README`` file), with the ``--enable-gemminicommitlog`` option added to the ``configure`` step. +Writing Your Own Gemmini Programs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +You can find a template for a Gemmini program, written in C, in `generators/gemmini/software/gemmini-rocc-tests/bareMetalC/template.c `__. Feel free to copy this file, say to ``my_program.c``, and add ``my_program`` to the `tests` list in `generators/gemmini/software/gemmini-rocc-tests/bareMetalC/Makefile `__: + +.. code-block:: shell + + tests = \ + my_program \ + mvin_mvout \ + mvin_mvout_stride \ + ... + +Afterwards as described above, run ``./build.sh`` again and you will be able to find the ``my_program-baremetal`` and ``my_program-linux`` binaries in the ``build/`` directory. Alternative SoC Configs -------------------------- From c07be0633b83c1e831be8cdc251fd9de7c4c6a55 Mon Sep 17 00:00:00 2001 From: Hasan Genc Date: Thu, 12 Dec 2019 00:27:52 -0800 Subject: [PATCH 22/25] Changed order of VCS and Verilator in Gemmini docs --- docs/Generators/Gemmini.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index fb5cae3e75..21131d2f61 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -100,6 +100,6 @@ If you would like to build one of these alternative SoC configurations which are .. code-block:: shell - cd sims/vcs # or "cd sims/verilator" + cd sims/verilator # or "cd sims/vcs" make CONFIG=GemminiAcceleratorConfig CONFIG_PACKAGE=gemmini MODEL_PACKAGE=freechips.rocketchip.system GENERATOR_PACKAGE=freechips.rocketchip.system TOP=ExampleRocketSystem From 33e6950dc4acb60dd06e85b4caa34d443ec12214 Mon Sep 17 00:00:00 2001 From: Hasan Genc Date: Fri, 13 Dec 2019 12:51:42 -0800 Subject: [PATCH 23/25] Remove "make your own tests" from Gemmini README --- docs/Generators/Gemmini.rst | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index 21131d2f61..d90e6224eb 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -55,17 +55,17 @@ The ``software`` directory of the generator includes the aforementioned library The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` -Build and Run Gemmini Programs +Build and Run Gemmini Tests ^^^^^^^^^^^^^^^^^^^^^^^^^ -To build pre-packaged Gemmini programs: +To build Gemmini tests: .. code-block:: shell cd generators/gemmini/software/gemmini-rocc-tests/ ./build.sh -Afterwards, the program binaries will be found in ``generators/gemmini/software/gemmini-rocc-tests/build``. Binaries whose names end in ``-baremetal`` are meant to be run in a bare-metal environment, while binaries whose names end in ``-linux`` are meant to run in a Linux environment. You can run the programs either on a cycle-accurate RTL simulator, or on a (much faster) functional ISA simulator called Spike. +Afterwards, the test binaries will be found in ``generators/gemmini/software/gemmini-rocc-tests/build``. Binaries whose names end in ``-baremetal`` are meant to be run in a bare-metal environment, while binaries whose names end in ``-linux`` are meant to run in a Linux environment. You can run the tests either on a cycle-accurate RTL simulator, or on a (much faster) functional ISA simulator called Spike. The Gemmini generator implements a custom non-standard version of Spike. This implementation is found within the ``esp-tools`` Spike implementation, together with the Hwacha vector accelerator non-standard ISA-extension. In order to use this version of Spike, please make sure to build the ``esp-tools`` software toolchain, as described in :ref:`build-toolchains`. @@ -77,21 +77,6 @@ In order to run Spike with the gemmini functional model, you will need to use th Spike is built by default without a commit log. However, if you would like to add detailed functional log of gemmini operation to the spike model, you can rebuild spike manually (based on the instructions in the ``esp-tools/riscv-isa-sim/README`` file), with the ``--enable-gemminicommitlog`` option added to the ``configure`` step. -Writing Your Own Gemmini Programs -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -You can find a template for a Gemmini program, written in C, in `generators/gemmini/software/gemmini-rocc-tests/bareMetalC/template.c `__. Feel free to copy this file, say to ``my_program.c``, and add ``my_program`` to the `tests` list in `generators/gemmini/software/gemmini-rocc-tests/bareMetalC/Makefile `__: - -.. code-block:: shell - - tests = \ - my_program \ - mvin_mvout \ - mvin_mvout_stride \ - ... - -Afterwards as described above, run ``./build.sh`` again and you will be able to find the ``my_program-baremetal`` and ``my_program-linux`` binaries in the ``build/`` directory. - Alternative SoC Configs -------------------------- From b1dbd9b5f7bad066e831a782d72809e46a480d58 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 13 Dec 2019 13:13:56 -0800 Subject: [PATCH 24/25] bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 4850af0ca4..16fda88555 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 4850af0ca4a6f727e968081f6bdda6cced87adfc +Subproject commit 16fda88555be77df41a6c0687f64810417843dae From 26484853d7c060cd613c48d5c9abfab297892344 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 13 Dec 2019 16:33:28 -0800 Subject: [PATCH 25/25] try to fix midasexamples CI --- .circleci/run-midasexamples-tests.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh index 383a75ff1b..7d31ac11b3 100755 --- a/.circleci/run-midasexamples-tests.sh +++ b/.circleci/run-midasexamples-tests.sh @@ -12,7 +12,7 @@ trap clean EXIT cd $LOCAL_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh -cd sims/firesim/sim/midas && git submodule update --init +cd sims/firesim/sim/midas # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\""