Data misalignment detection different for LBU vs LB instruction

[viniul]

The data misalignment detection is implemented as follows:

   // Data misalignment detection
   // For example, if type is 3 (word), the mask is ~(0b111 << (3 - 1)) = ~0b100 = 0b011.
   val misaligned_mask = Wire(UInt(3.W))
   misaligned_mask := ~(7.U(3.W) << (cs_msk_sel - 1.U)(2, 0))
   data_misaligned := (misaligned_mask & io.dat.mem_address_low).orR && mem_en

where cs_msk_sel is dependent on the instruction and is 5 (MT_BU ) for an LBU instruction, and 0(MT_B) for a LB instruction in the 1-stage Sodor core.

This results in a different misaligned_mask for LBU (mask will be 111) vs. LB (mask will be 000) instructions. Consequentially, some loads being flagged as misaligned for an LBU instruction, but not being flagged as misaligned for an LB instruction.

Consider the instruction sequence:

addi x15, x0, 1
slli x15, x15, 31
lb x1, 1(x15)

which correctly returns 07, but switching from lb to lbu will result in an data misaligned exception.

Is this intentional? If so, what is the rationale behind this choice?

[jerryz123]

This seems like a bug. A PR with the fix would be appreciated.