Detailed information can be found under http://flink-project.ch/flink_vhdl
At the current state flink is available for Altera and Xilinx FPGAs.
Altera:
- For compiling and downloading Quartus Version 13.0.1 Service Pack 1 and Qsys 13.0sp1 is used.
- For simulation use Modelsim Altera 10.1d.
- The TCL scripts added in the repository are only working with Qsys 13.0sp1!
Xilinx:
- Tested up to Vivado version 2022.1
Information about available functions and their register maps can be found in: http://flink-project.ch/subdevices