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flinkvhdl: vhdl part of the flink project

Detailed information can be found under http://flink-project.ch/flink_vhdl

Development Tools

At the current state flink is available for Altera and Xilinx FPGAs.

Altera:

  • For compiling and downloading Quartus Version 13.0.1 Service Pack 1 and Qsys 13.0sp1 is used.
  • For simulation use Modelsim Altera 10.1d.
  • The TCL scripts added in the repository are only working with Qsys 13.0sp1!

Xilinx:

  • Tested up to Vivado version 2022.1

Information about available functions and their register maps can be found in: http://flink-project.ch/subdevices

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  • VHDL 92.7%
  • V 2.7%
  • Verilog 2.2%
  • Tcl 2.0%
  • Stata 0.4%
  • C 0.0%