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Source map resolver #776

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dalance opened this issue Jun 11, 2024 · 0 comments · Fixed by #810
Closed

Source map resolver #776

dalance opened this issue Jun 11, 2024 · 0 comments · Fixed by #810
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@dalance
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dalance commented Jun 11, 2024

Independent library or binary from Veryl compiler to translate source position by source map is useful.
For example, the binary can translate the existing log or receive log through pipe like below:

$ resolver synthesis.log
$ ./simv | resolver

Independent library with C API may be useful to integrate to other EDA tools like Verilator, Yosys, and so on.

Related: #438
@dalance dalance mentioned this issue Jun 11, 2024
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@dalance dalance added enhancement New feature or request tools Tools feature and removed enhancement New feature or request labels Jun 11, 2024
@dalance dalance mentioned this issue Jul 3, 2024
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Add sourcemap-resolver to release build veryl-lang/veryl
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