From 52577a39f4fe6ee21c552a1da8ef5feff1ec9364 Mon Sep 17 00:00:00 2001
From: wavemotion-dave <75039837+wavemotion-dave@users.noreply.github.com>
Date: Wed, 22 Dec 2021 17:58:42 -0500
Subject: [PATCH] V4.6a - more games added to the new CZ80 CPU core and speedup
 of Z80 core.

---
 ColecoDS.nds                  | Bin 788480 -> 788480 bytes
 Makefile                      |   2 +-
 arm9/source/colecoDS.c        |   7 +-
 arm9/source/colecogeneric.c   |   1 +
 arm9/source/cpu/z80/Codes.h   | 562 ++++++++++++++++-----------------
 arm9/source/cpu/z80/CodesCB.h | 380 +++++++++++-----------
 arm9/source/cpu/z80/CodesED.h | 302 +++++++++---------
 arm9/source/cpu/z80/CodesXX.h | 576 +++++++++++++++++-----------------
 arm9/source/cpu/z80/Z80.c     | 393 +++++++++++------------
 arm9/source/cpu/z80/Z80.h     |   2 +-
 10 files changed, 1116 insertions(+), 1109 deletions(-)

diff --git a/ColecoDS.nds b/ColecoDS.nds
index ffef15a12b12504b686e2831c78bd203257db48d..fe116ebe0b151b210e75bc3183da46172e44223e 100644
GIT binary patch
delta 86154
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diff --git a/Makefile b/Makefile
index 42d9f097..d40338c8 100644
--- a/Makefile
+++ b/Makefile
@@ -9,7 +9,7 @@ include $(DEVKITARM)/ds_rules
 
 export TARGET		:=	ColecoDS
 export TOPDIR		:=	$(CURDIR)
-export VERSION		:=  4.6
+export VERSION		:=  4.6a
 
 ICON 		:= -b $(CURDIR)/logo.bmp "ColecoDS $(VERSION);wavemotion-dave;https://github.com/wavemotion-dave/ColecoDS" 
 
diff --git a/arm9/source/colecoDS.c b/arm9/source/colecoDS.c
index 557c4381..949e4393 100644
--- a/arm9/source/colecoDS.c
+++ b/arm9/source/colecoDS.c
@@ -44,6 +44,9 @@
 
 #include "cpu/sn76496/SN76496.h"
 #include "cpu/sn76496/Fake_AY.h"
+#include "cpu/z80/Z80.h"
+extern Z80 CPU;
+
 
 // --------------------------------------------------------------------------
 // This is the full 64K coleco memory map.
@@ -347,7 +350,9 @@ void ResetColecovision(void)
   sn76496W(0xB0 | 0x0F  ,&aycol);       //  Write new Volume for Channel B (off)
   sn76496W(0xD0 | 0x0F  ,&aycol);       //  Write new Volume for Channel C (off)
     
-  DrZ80_Reset();                        //  Reset the Z80 CPU Core
+  DrZ80_Reset();                        // Reset the Z80 CPU Core
+  CPU.IPeriod = TMS9918_LINE;
+  ResetZ80(&CPU);                       // Reset the CZ80 core CPU
 
   memset(pColecoMem+0x2000, 0xFF, 0x6000);  // Reset non-mapped area between BIOS and RAM - SGM RAM might map here
   
diff --git a/arm9/source/colecogeneric.c b/arm9/source/colecogeneric.c
index e9d843a5..37e779a3 100644
--- a/arm9/source/colecogeneric.c
+++ b/arm9/source/colecogeneric.c
@@ -805,6 +805,7 @@ void SetDefaultGameConfig(void)
         (file_crc == 0x260cdf98) ||     // Super Pac-Mans
         (file_crc == 0xae209065) ||     // Super Space Acer
         (file_crc == 0xbc8320a0) ||     // Uridium
+        (file_crc == 0xa7a8d25e) ||     // Vanguard        
         (file_crc == 0x530c586f)        // Vexxed
         )
     {
diff --git a/arm9/source/cpu/z80/Codes.h b/arm9/source/cpu/z80/Codes.h
index 35162efc..1f101340 100644
--- a/arm9/source/cpu/z80/Codes.h
+++ b/arm9/source/cpu/z80/Codes.h
@@ -11,180 +11,180 @@
 /**     changes to this file.                               **/
 /*************************************************************/
 
-case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
-case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
-case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
-case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
-
-case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
-case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
-case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
-case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
-case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
-case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
-case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
-case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
-
-case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
-case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
-case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
-case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
-case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
-case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
-case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
-case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
-
-case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
-case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
-case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
-case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
-case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
-case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
-case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
-case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
-
-case ADD_B:    M_ADD(R->BC.B.h);break;
-case ADD_C:    M_ADD(R->BC.B.l);break;
-case ADD_D:    M_ADD(R->DE.B.h);break;
-case ADD_E:    M_ADD(R->DE.B.l);break;
-case ADD_H:    M_ADD(R->HL.B.h);break;
-case ADD_L:    M_ADD(R->HL.B.l);break;
-case ADD_A:    M_ADD(R->AF.B.h);break;
-case ADD_xHL:  I=RdZ80(R->HL.W);M_ADD(I);break;
-case ADD_BYTE: I=OpZ80(R->PC.W++);M_ADD(I);break;
-
-case SUB_B:    M_SUB(R->BC.B.h);break;
-case SUB_C:    M_SUB(R->BC.B.l);break;
-case SUB_D:    M_SUB(R->DE.B.h);break;
-case SUB_E:    M_SUB(R->DE.B.l);break;
-case SUB_H:    M_SUB(R->HL.B.h);break;
-case SUB_L:    M_SUB(R->HL.B.l);break;
-case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
-case SUB_xHL:  I=RdZ80(R->HL.W);M_SUB(I);break;
-case SUB_BYTE: I=OpZ80(R->PC.W++);M_SUB(I);break;
-
-case AND_B:    M_AND(R->BC.B.h);break;
-case AND_C:    M_AND(R->BC.B.l);break;
-case AND_D:    M_AND(R->DE.B.h);break;
-case AND_E:    M_AND(R->DE.B.l);break;
-case AND_H:    M_AND(R->HL.B.h);break;
-case AND_L:    M_AND(R->HL.B.l);break;
-case AND_A:    M_AND(R->AF.B.h);break;
-case AND_xHL:  I=RdZ80(R->HL.W);M_AND(I);break;
-case AND_BYTE: I=OpZ80(R->PC.W++);M_AND(I);break;
-
-case OR_B:     M_OR(R->BC.B.h);break;
-case OR_C:     M_OR(R->BC.B.l);break;
-case OR_D:     M_OR(R->DE.B.h);break;
-case OR_E:     M_OR(R->DE.B.l);break;
-case OR_H:     M_OR(R->HL.B.h);break;
-case OR_L:     M_OR(R->HL.B.l);break;
-case OR_A:     M_OR(R->AF.B.h);break;
-case OR_xHL:   I=RdZ80(R->HL.W);M_OR(I);break;
-case OR_BYTE:  I=OpZ80(R->PC.W++);M_OR(I);break;
-
-case ADC_B:    M_ADC(R->BC.B.h);break;
-case ADC_C:    M_ADC(R->BC.B.l);break;
-case ADC_D:    M_ADC(R->DE.B.h);break;
-case ADC_E:    M_ADC(R->DE.B.l);break;
-case ADC_H:    M_ADC(R->HL.B.h);break;
-case ADC_L:    M_ADC(R->HL.B.l);break;
-case ADC_A:    M_ADC(R->AF.B.h);break;
-case ADC_xHL:  I=RdZ80(R->HL.W);M_ADC(I);break;
-case ADC_BYTE: I=OpZ80(R->PC.W++);M_ADC(I);break;
-
-case SBC_B:    M_SBC(R->BC.B.h);break;
-case SBC_C:    M_SBC(R->BC.B.l);break;
-case SBC_D:    M_SBC(R->DE.B.h);break;
-case SBC_E:    M_SBC(R->DE.B.l);break;
-case SBC_H:    M_SBC(R->HL.B.h);break;
-case SBC_L:    M_SBC(R->HL.B.l);break;
-case SBC_A:    M_SBC(R->AF.B.h);break;
-case SBC_xHL:  I=RdZ80(R->HL.W);M_SBC(I);break;
-case SBC_BYTE: I=OpZ80(R->PC.W++);M_SBC(I);break;
-
-case XOR_B:    M_XOR(R->BC.B.h);break;
-case XOR_C:    M_XOR(R->BC.B.l);break;
-case XOR_D:    M_XOR(R->DE.B.h);break;
-case XOR_E:    M_XOR(R->DE.B.l);break;
-case XOR_H:    M_XOR(R->HL.B.h);break;
-case XOR_L:    M_XOR(R->HL.B.l);break;
-case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
-case XOR_xHL:  I=RdZ80(R->HL.W);M_XOR(I);break;
-case XOR_BYTE: I=OpZ80(R->PC.W++);M_XOR(I);break;
-
-case CP_B:     M_CP(R->BC.B.h);break;
-case CP_C:     M_CP(R->BC.B.l);break;
-case CP_D:     M_CP(R->DE.B.h);break;
-case CP_E:     M_CP(R->DE.B.l);break;
-case CP_H:     M_CP(R->HL.B.h);break;
-case CP_L:     M_CP(R->HL.B.l);break;
-case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
-case CP_xHL:   I=RdZ80(R->HL.W);M_CP(I);break;
-case CP_BYTE:  I=OpZ80(R->PC.W++);M_CP(I);break;
+case JR_NZ:   if(CPU.AF.B.l&Z_FLAG) CPU.PC.W++; else { CPU.ICount-=5;M_JR; } break;
+case JR_NC:   if(CPU.AF.B.l&C_FLAG) CPU.PC.W++; else { CPU.ICount-=5;M_JR; } break;
+case JR_Z:    if(CPU.AF.B.l&Z_FLAG) { CPU.ICount-=5;M_JR; } else CPU.PC.W++; break;
+case JR_C:    if(CPU.AF.B.l&C_FLAG) { CPU.ICount-=5;M_JR; } else CPU.PC.W++; break;
+
+case JP_NZ:   if(CPU.AF.B.l&Z_FLAG) CPU.PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(CPU.AF.B.l&C_FLAG) CPU.PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(CPU.AF.B.l&P_FLAG) CPU.PC.W+=2; else { M_JP; } break;
+case JP_P:    if(CPU.AF.B.l&S_FLAG) CPU.PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(CPU.AF.B.l&Z_FLAG) { M_JP; } else CPU.PC.W+=2; break;
+case JP_C:    if(CPU.AF.B.l&C_FLAG) { M_JP; } else CPU.PC.W+=2; break;
+case JP_PE:   if(CPU.AF.B.l&P_FLAG) { M_JP; } else CPU.PC.W+=2; break;
+case JP_M:    if(CPU.AF.B.l&S_FLAG) { M_JP; } else CPU.PC.W+=2; break;
+
+case RET_NZ:  if(!(CPU.AF.B.l&Z_FLAG)) { CPU.ICount-=6;M_RET; } break;
+case RET_NC:  if(!(CPU.AF.B.l&C_FLAG)) { CPU.ICount-=6;M_RET; } break;
+case RET_PO:  if(!(CPU.AF.B.l&P_FLAG)) { CPU.ICount-=6;M_RET; } break;
+case RET_P:   if(!(CPU.AF.B.l&S_FLAG)) { CPU.ICount-=6;M_RET; } break;
+case RET_Z:   if(CPU.AF.B.l&Z_FLAG)    { CPU.ICount-=6;M_RET; } break;
+case RET_C:   if(CPU.AF.B.l&C_FLAG)    { CPU.ICount-=6;M_RET; } break;
+case RET_PE:  if(CPU.AF.B.l&P_FLAG)    { CPU.ICount-=6;M_RET; } break;
+case RET_M:   if(CPU.AF.B.l&S_FLAG)    { CPU.ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(CPU.AF.B.l&Z_FLAG) CPU.PC.W+=2; else { CPU.ICount-=7;M_CALL; } break;
+case CALL_NC: if(CPU.AF.B.l&C_FLAG) CPU.PC.W+=2; else { CPU.ICount-=7;M_CALL; } break;
+case CALL_PO: if(CPU.AF.B.l&P_FLAG) CPU.PC.W+=2; else { CPU.ICount-=7;M_CALL; } break;
+case CALL_P:  if(CPU.AF.B.l&S_FLAG) CPU.PC.W+=2; else { CPU.ICount-=7;M_CALL; } break;
+case CALL_Z:  if(CPU.AF.B.l&Z_FLAG) { CPU.ICount-=7;M_CALL; } else CPU.PC.W+=2; break;
+case CALL_C:  if(CPU.AF.B.l&C_FLAG) { CPU.ICount-=7;M_CALL; } else CPU.PC.W+=2; break;
+case CALL_PE: if(CPU.AF.B.l&P_FLAG) { CPU.ICount-=7;M_CALL; } else CPU.PC.W+=2; break;
+case CALL_M:  if(CPU.AF.B.l&S_FLAG) { CPU.ICount-=7;M_CALL; } else CPU.PC.W+=2; break;
+
+case ADD_B:    M_ADD(CPU.BC.B.h);break;
+case ADD_C:    M_ADD(CPU.BC.B.l);break;
+case ADD_D:    M_ADD(CPU.DE.B.h);break;
+case ADD_E:    M_ADD(CPU.DE.B.l);break;
+case ADD_H:    M_ADD(CPU.HL.B.h);break;
+case ADD_L:    M_ADD(CPU.HL.B.l);break;
+case ADD_A:    M_ADD(CPU.AF.B.h);break;
+case ADD_xHL:  I=RdZ80(CPU.HL.W);M_ADD(I);break;
+case ADD_BYTE: I=OpZ80(CPU.PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(CPU.BC.B.h);break;
+case SUB_C:    M_SUB(CPU.BC.B.l);break;
+case SUB_D:    M_SUB(CPU.DE.B.h);break;
+case SUB_E:    M_SUB(CPU.DE.B.l);break;
+case SUB_H:    M_SUB(CPU.HL.B.h);break;
+case SUB_L:    M_SUB(CPU.HL.B.l);break;
+case SUB_A:    CPU.AF.B.h=0;CPU.AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(CPU.HL.W);M_SUB(I);break;
+case SUB_BYTE: I=OpZ80(CPU.PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(CPU.BC.B.h);break;
+case AND_C:    M_AND(CPU.BC.B.l);break;
+case AND_D:    M_AND(CPU.DE.B.h);break;
+case AND_E:    M_AND(CPU.DE.B.l);break;
+case AND_H:    M_AND(CPU.HL.B.h);break;
+case AND_L:    M_AND(CPU.HL.B.l);break;
+case AND_A:    M_AND(CPU.AF.B.h);break;
+case AND_xHL:  I=RdZ80(CPU.HL.W);M_AND(I);break;
+case AND_BYTE: I=OpZ80(CPU.PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(CPU.BC.B.h);break;
+case OR_C:     M_OR(CPU.BC.B.l);break;
+case OR_D:     M_OR(CPU.DE.B.h);break;
+case OR_E:     M_OR(CPU.DE.B.l);break;
+case OR_H:     M_OR(CPU.HL.B.h);break;
+case OR_L:     M_OR(CPU.HL.B.l);break;
+case OR_A:     M_OR(CPU.AF.B.h);break;
+case OR_xHL:   I=RdZ80(CPU.HL.W);M_OR(I);break;
+case OR_BYTE:  I=OpZ80(CPU.PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(CPU.BC.B.h);break;
+case ADC_C:    M_ADC(CPU.BC.B.l);break;
+case ADC_D:    M_ADC(CPU.DE.B.h);break;
+case ADC_E:    M_ADC(CPU.DE.B.l);break;
+case ADC_H:    M_ADC(CPU.HL.B.h);break;
+case ADC_L:    M_ADC(CPU.HL.B.l);break;
+case ADC_A:    M_ADC(CPU.AF.B.h);break;
+case ADC_xHL:  I=RdZ80(CPU.HL.W);M_ADC(I);break;
+case ADC_BYTE: I=OpZ80(CPU.PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(CPU.BC.B.h);break;
+case SBC_C:    M_SBC(CPU.BC.B.l);break;
+case SBC_D:    M_SBC(CPU.DE.B.h);break;
+case SBC_E:    M_SBC(CPU.DE.B.l);break;
+case SBC_H:    M_SBC(CPU.HL.B.h);break;
+case SBC_L:    M_SBC(CPU.HL.B.l);break;
+case SBC_A:    M_SBC(CPU.AF.B.h);break;
+case SBC_xHL:  I=RdZ80(CPU.HL.W);M_SBC(I);break;
+case SBC_BYTE: I=OpZ80(CPU.PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(CPU.BC.B.h);break;
+case XOR_C:    M_XOR(CPU.BC.B.l);break;
+case XOR_D:    M_XOR(CPU.DE.B.h);break;
+case XOR_E:    M_XOR(CPU.DE.B.l);break;
+case XOR_H:    M_XOR(CPU.HL.B.h);break;
+case XOR_L:    M_XOR(CPU.HL.B.l);break;
+case XOR_A:    CPU.AF.B.h=0;CPU.AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(CPU.HL.W);M_XOR(I);break;
+case XOR_BYTE: I=OpZ80(CPU.PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(CPU.BC.B.h);break;
+case CP_C:     M_CP(CPU.BC.B.l);break;
+case CP_D:     M_CP(CPU.DE.B.h);break;
+case CP_E:     M_CP(CPU.DE.B.l);break;
+case CP_H:     M_CP(CPU.HL.B.h);break;
+case CP_L:     M_CP(CPU.HL.B.l);break;
+case CP_A:     CPU.AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(CPU.HL.W);M_CP(I);break;
+case CP_BYTE:  I=OpZ80(CPU.PC.W++);M_CP(I);break;
                
 case LD_BC_WORD: M_LDWORD(BC);break;
 case LD_DE_WORD: M_LDWORD(DE);break;
 case LD_HL_WORD: M_LDWORD(HL);break;
 case LD_SP_WORD: M_LDWORD(SP);break;
 
-case LD_PC_HL: R->PC.W=R->HL.W;JumpZ80(R->PC.W);break;
-case LD_SP_HL: R->SP.W=R->HL.W;break;
-case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
-case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+case LD_PC_HL: CPU.PC.W=CPU.HL.W;JumpZ80(CPU.PC.W);break;
+case LD_SP_HL: CPU.SP.W=CPU.HL.W;break;
+case LD_A_xBC: CPU.AF.B.h=RdZ80(CPU.BC.W);break;
+case LD_A_xDE: CPU.AF.B.h=RdZ80(CPU.DE.W);break;
 
 case ADD_HL_BC:  M_ADDW(HL,BC);break;
 case ADD_HL_DE:  M_ADDW(HL,DE);break;
 case ADD_HL_HL:  M_ADDW(HL,HL);break;
 case ADD_HL_SP:  M_ADDW(HL,SP);break;
 
-case DEC_BC:   R->BC.W--;break;
-case DEC_DE:   R->DE.W--;break;
-case DEC_HL:   R->HL.W--;break;
-case DEC_SP:   R->SP.W--;break;
-
-case INC_BC:   R->BC.W++;break;
-case INC_DE:   R->DE.W++;break;
-case INC_HL:   R->HL.W++;break;
-case INC_SP:   R->SP.W++;break;
-
-case DEC_B:    M_DEC(R->BC.B.h);break;
-case DEC_C:    M_DEC(R->BC.B.l);break;
-case DEC_D:    M_DEC(R->DE.B.h);break;
-case DEC_E:    M_DEC(R->DE.B.l);break;
-case DEC_H:    M_DEC(R->HL.B.h);break;
-case DEC_L:    M_DEC(R->HL.B.l);break;
-case DEC_A:    M_DEC(R->AF.B.h);break;
-case DEC_xHL:  I=RdZ80(R->HL.W);M_DEC(I);WrZ80(R->HL.W,I);break;
-
-case INC_B:    M_INC(R->BC.B.h);break;
-case INC_C:    M_INC(R->BC.B.l);break;
-case INC_D:    M_INC(R->DE.B.h);break;
-case INC_E:    M_INC(R->DE.B.l);break;
-case INC_H:    M_INC(R->HL.B.h);break;
-case INC_L:    M_INC(R->HL.B.l);break;
-case INC_A:    M_INC(R->AF.B.h);break;
-case INC_xHL:  I=RdZ80(R->HL.W);M_INC(I);WrZ80(R->HL.W,I);break;
+case DEC_BC:   CPU.BC.W--;break;
+case DEC_DE:   CPU.DE.W--;break;
+case DEC_HL:   CPU.HL.W--;break;
+case DEC_SP:   CPU.SP.W--;break;
+
+case INC_BC:   CPU.BC.W++;break;
+case INC_DE:   CPU.DE.W++;break;
+case INC_HL:   CPU.HL.W++;break;
+case INC_SP:   CPU.SP.W++;break;
+
+case DEC_B:    M_DEC(CPU.BC.B.h);break;
+case DEC_C:    M_DEC(CPU.BC.B.l);break;
+case DEC_D:    M_DEC(CPU.DE.B.h);break;
+case DEC_E:    M_DEC(CPU.DE.B.l);break;
+case DEC_H:    M_DEC(CPU.HL.B.h);break;
+case DEC_L:    M_DEC(CPU.HL.B.l);break;
+case DEC_A:    M_DEC(CPU.AF.B.h);break;
+case DEC_xHL:  I=RdZ80(CPU.HL.W);M_DEC(I);WrZ80(CPU.HL.W,I);break;
+
+case INC_B:    M_INC(CPU.BC.B.h);break;
+case INC_C:    M_INC(CPU.BC.B.l);break;
+case INC_D:    M_INC(CPU.DE.B.h);break;
+case INC_E:    M_INC(CPU.DE.B.l);break;
+case INC_H:    M_INC(CPU.HL.B.h);break;
+case INC_L:    M_INC(CPU.HL.B.l);break;
+case INC_A:    M_INC(CPU.AF.B.h);break;
+case INC_xHL:  I=RdZ80(CPU.HL.W);M_INC(I);WrZ80(CPU.HL.W,I);break;
 
 case RLCA:
-  I=R->AF.B.h&0x80? C_FLAG:0;
-  R->AF.B.h=(R->AF.B.h<<1)|I;
-  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  I=CPU.AF.B.h&0x80? C_FLAG:0;
+  CPU.AF.B.h=(CPU.AF.B.h<<1)|I;
+  CPU.AF.B.l=(CPU.AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
   break;
 case RLA:
-  I=R->AF.B.h&0x80? C_FLAG:0;
-  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
-  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  I=CPU.AF.B.h&0x80? C_FLAG:0;
+  CPU.AF.B.h=(CPU.AF.B.h<<1)|(CPU.AF.B.l&C_FLAG);
+  CPU.AF.B.l=(CPU.AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
   break;
 case RRCA:
-  I=R->AF.B.h&0x01;
-  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
-  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I; 
+  I=CPU.AF.B.h&0x01;
+  CPU.AF.B.h=(CPU.AF.B.h>>1)|(I? 0x80:0);
+  CPU.AF.B.l=(CPU.AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I; 
   break;
 case RRA:
-  I=R->AF.B.h&0x01;
-  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
-  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  I=CPU.AF.B.h&0x01;
+  CPU.AF.B.h=(CPU.AF.B.h>>1)|(CPU.AF.B.l&C_FLAG? 0x80:0);
+  CPU.AF.B.l=(CPU.AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
   break;
 
 case RST00:    M_RST(0x0000);break;
@@ -206,180 +206,180 @@ case POP_DE:   M_POP(DE);break;
 case POP_HL:   M_POP(HL);break;
 case POP_AF:   M_POP(AF);break;
 
-case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case DJNZ: if(--CPU.BC.B.h) { CPU.ICount-=5;M_JR; } else CPU.PC.W++;break;
 case JP:   M_JP;break;
 case JR:   M_JR;break;
 case CALL: M_CALL;break;
 case RET:  M_RET;break;
 case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
-case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case CPL:  CPU.AF.B.h=~CPU.AF.B.h;S(N_FLAG|H_FLAG);break;
 case NOP:  break;
-case OUTA: I=OpZ80(R->PC.W++);OutZ80(I|(R->AF.W&0xFF00),R->AF.B.h);break;
-case INA:  I=OpZ80(R->PC.W++);R->AF.B.h=InZ80(I|(R->AF.W&0xFF00));break;
+case OUTA: I=OpZ80(CPU.PC.W++);OutZ80(I|(CPU.AF.W&0xFF00),CPU.AF.B.h);break;
+case INA:  I=OpZ80(CPU.PC.W++);CPU.AF.B.h=InZ80(I|(CPU.AF.W&0xFF00));break;
 
 case HALT:
-  R->PC.W--;
-  R->IFF|=IFF_HALT;
-  R->IBackup=0;
-  R->ICount=0;
+  CPU.PC.W--;
+  CPU.IFF|=IFF_HALT;
+  CPU.IBackup=0;
+  CPU.ICount=0;
   break;
 
 case DI:
-  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
-  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  if(CPU.IFF&IFF_EI) CPU.ICount+=CPU.IBackup-1;
+  CPU.IFF&=~(IFF_1|IFF_2|IFF_EI);
   break;
 
 case EI:
-  if(!(R->IFF&(IFF_1|IFF_EI)))
+  if(!(CPU.IFF&(IFF_1|IFF_EI)))
   {
-    R->IFF|=IFF_2|IFF_EI;
-    R->IBackup=R->ICount;
-    R->ICount=1;
+    CPU.IFF|=IFF_2|IFF_EI;
+    CPU.IBackup=CPU.ICount;
+    CPU.ICount=1;
   }
   break;
 
 case CCF:
-  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
-  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  CPU.AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  CPU.AF.B.l|=CPU.AF.B.l&C_FLAG? 0:H_FLAG;
   break;
 
 case EXX:
-  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
-  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
-  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  J.W=CPU.BC.W;CPU.BC.W=CPU.BC1.W;CPU.BC1.W=J.W;
+  J.W=CPU.DE.W;CPU.DE.W=CPU.DE1.W;CPU.DE1.W=J.W;
+  J.W=CPU.HL.W;CPU.HL.W=CPU.HL1.W;CPU.HL1.W=J.W;
   break;
 
-case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
-case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+case EX_DE_HL: J.W=CPU.DE.W;CPU.DE.W=CPU.HL.W;CPU.HL.W=J.W;break;
+case EX_AF_AF: J.W=CPU.AF.W;CPU.AF.W=CPU.AF1.W;CPU.AF1.W=J.W;break;  
   
-case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
-case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
-case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
-case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
-case LD_H_B:   R->HL.B.h=R->BC.B.h;break;
-case LD_L_B:   R->HL.B.l=R->BC.B.h;break;
-case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
-case LD_xHL_B: WrZ80(R->HL.W,R->BC.B.h);break;
-
-case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
-case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
-case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
-case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
-case LD_H_C:   R->HL.B.h=R->BC.B.l;break;
-case LD_L_C:   R->HL.B.l=R->BC.B.l;break;
-case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
-case LD_xHL_C: WrZ80(R->HL.W,R->BC.B.l);break;
-
-case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
-case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
-case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
-case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
-case LD_H_D:   R->HL.B.h=R->DE.B.h;break;
-case LD_L_D:   R->HL.B.l=R->DE.B.h;break;
-case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
-case LD_xHL_D: WrZ80(R->HL.W,R->DE.B.h);break;
-
-case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
-case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
-case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
-case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
-case LD_H_E:   R->HL.B.h=R->DE.B.l;break;
-case LD_L_E:   R->HL.B.l=R->DE.B.l;break;
-case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
-case LD_xHL_E: WrZ80(R->HL.W,R->DE.B.l);break;
-
-case LD_B_H:   R->BC.B.h=R->HL.B.h;break;
-case LD_C_H:   R->BC.B.l=R->HL.B.h;break;
-case LD_D_H:   R->DE.B.h=R->HL.B.h;break;
-case LD_E_H:   R->DE.B.l=R->HL.B.h;break;
-case LD_H_H:   R->HL.B.h=R->HL.B.h;break;
-case LD_L_H:   R->HL.B.l=R->HL.B.h;break;
-case LD_A_H:   R->AF.B.h=R->HL.B.h;break;
-case LD_xHL_H: WrZ80(R->HL.W,R->HL.B.h);break;
-
-case LD_B_L:   R->BC.B.h=R->HL.B.l;break;
-case LD_C_L:   R->BC.B.l=R->HL.B.l;break;
-case LD_D_L:   R->DE.B.h=R->HL.B.l;break;
-case LD_E_L:   R->DE.B.l=R->HL.B.l;break;
-case LD_H_L:   R->HL.B.h=R->HL.B.l;break;
-case LD_L_L:   R->HL.B.l=R->HL.B.l;break;
-case LD_A_L:   R->AF.B.h=R->HL.B.l;break;
-case LD_xHL_L: WrZ80(R->HL.W,R->HL.B.l);break;
-
-case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
-case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
-case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
-case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
-case LD_H_A:   R->HL.B.h=R->AF.B.h;break;
-case LD_L_A:   R->HL.B.l=R->AF.B.h;break;
-case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
-case LD_xHL_A: WrZ80(R->HL.W,R->AF.B.h);break;
-
-case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
-case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
-
-case LD_B_xHL:    R->BC.B.h=RdZ80(R->HL.W);break;
-case LD_C_xHL:    R->BC.B.l=RdZ80(R->HL.W);break;
-case LD_D_xHL:    R->DE.B.h=RdZ80(R->HL.W);break;
-case LD_E_xHL:    R->DE.B.l=RdZ80(R->HL.W);break;
-case LD_H_xHL:    R->HL.B.h=RdZ80(R->HL.W);break;
-case LD_L_xHL:    R->HL.B.l=RdZ80(R->HL.W);break;
-case LD_A_xHL:    R->AF.B.h=RdZ80(R->HL.W);break;
-
-case LD_B_BYTE:   R->BC.B.h=OpZ80(R->PC.W++);break;
-case LD_C_BYTE:   R->BC.B.l=OpZ80(R->PC.W++);break;
-case LD_D_BYTE:   R->DE.B.h=OpZ80(R->PC.W++);break;
-case LD_E_BYTE:   R->DE.B.l=OpZ80(R->PC.W++);break;
-case LD_H_BYTE:   R->HL.B.h=OpZ80(R->PC.W++);break;
-case LD_L_BYTE:   R->HL.B.l=OpZ80(R->PC.W++);break;
-case LD_A_BYTE:   R->AF.B.h=OpZ80(R->PC.W++);break;
-case LD_xHL_BYTE: WrZ80(R->HL.W,OpZ80(R->PC.W++));break;
+case LD_B_B:   CPU.BC.B.h=CPU.BC.B.h;break;
+case LD_C_B:   CPU.BC.B.l=CPU.BC.B.h;break;
+case LD_D_B:   CPU.DE.B.h=CPU.BC.B.h;break;
+case LD_E_B:   CPU.DE.B.l=CPU.BC.B.h;break;
+case LD_H_B:   CPU.HL.B.h=CPU.BC.B.h;break;
+case LD_L_B:   CPU.HL.B.l=CPU.BC.B.h;break;
+case LD_A_B:   CPU.AF.B.h=CPU.BC.B.h;break;
+case LD_xHL_B: WrZ80(CPU.HL.W,CPU.BC.B.h);break;
+
+case LD_B_C:   CPU.BC.B.h=CPU.BC.B.l;break;
+case LD_C_C:   CPU.BC.B.l=CPU.BC.B.l;break;
+case LD_D_C:   CPU.DE.B.h=CPU.BC.B.l;break;
+case LD_E_C:   CPU.DE.B.l=CPU.BC.B.l;break;
+case LD_H_C:   CPU.HL.B.h=CPU.BC.B.l;break;
+case LD_L_C:   CPU.HL.B.l=CPU.BC.B.l;break;
+case LD_A_C:   CPU.AF.B.h=CPU.BC.B.l;break;
+case LD_xHL_C: WrZ80(CPU.HL.W,CPU.BC.B.l);break;
+
+case LD_B_D:   CPU.BC.B.h=CPU.DE.B.h;break;
+case LD_C_D:   CPU.BC.B.l=CPU.DE.B.h;break;
+case LD_D_D:   CPU.DE.B.h=CPU.DE.B.h;break;
+case LD_E_D:   CPU.DE.B.l=CPU.DE.B.h;break;
+case LD_H_D:   CPU.HL.B.h=CPU.DE.B.h;break;
+case LD_L_D:   CPU.HL.B.l=CPU.DE.B.h;break;
+case LD_A_D:   CPU.AF.B.h=CPU.DE.B.h;break;
+case LD_xHL_D: WrZ80(CPU.HL.W,CPU.DE.B.h);break;
+
+case LD_B_E:   CPU.BC.B.h=CPU.DE.B.l;break;
+case LD_C_E:   CPU.BC.B.l=CPU.DE.B.l;break;
+case LD_D_E:   CPU.DE.B.h=CPU.DE.B.l;break;
+case LD_E_E:   CPU.DE.B.l=CPU.DE.B.l;break;
+case LD_H_E:   CPU.HL.B.h=CPU.DE.B.l;break;
+case LD_L_E:   CPU.HL.B.l=CPU.DE.B.l;break;
+case LD_A_E:   CPU.AF.B.h=CPU.DE.B.l;break;
+case LD_xHL_E: WrZ80(CPU.HL.W,CPU.DE.B.l);break;
+
+case LD_B_H:   CPU.BC.B.h=CPU.HL.B.h;break;
+case LD_C_H:   CPU.BC.B.l=CPU.HL.B.h;break;
+case LD_D_H:   CPU.DE.B.h=CPU.HL.B.h;break;
+case LD_E_H:   CPU.DE.B.l=CPU.HL.B.h;break;
+case LD_H_H:   CPU.HL.B.h=CPU.HL.B.h;break;
+case LD_L_H:   CPU.HL.B.l=CPU.HL.B.h;break;
+case LD_A_H:   CPU.AF.B.h=CPU.HL.B.h;break;
+case LD_xHL_H: WrZ80(CPU.HL.W,CPU.HL.B.h);break;
+
+case LD_B_L:   CPU.BC.B.h=CPU.HL.B.l;break;
+case LD_C_L:   CPU.BC.B.l=CPU.HL.B.l;break;
+case LD_D_L:   CPU.DE.B.h=CPU.HL.B.l;break;
+case LD_E_L:   CPU.DE.B.l=CPU.HL.B.l;break;
+case LD_H_L:   CPU.HL.B.h=CPU.HL.B.l;break;
+case LD_L_L:   CPU.HL.B.l=CPU.HL.B.l;break;
+case LD_A_L:   CPU.AF.B.h=CPU.HL.B.l;break;
+case LD_xHL_L: WrZ80(CPU.HL.W,CPU.HL.B.l);break;
+
+case LD_B_A:   CPU.BC.B.h=CPU.AF.B.h;break;
+case LD_C_A:   CPU.BC.B.l=CPU.AF.B.h;break;
+case LD_D_A:   CPU.DE.B.h=CPU.AF.B.h;break;
+case LD_E_A:   CPU.DE.B.l=CPU.AF.B.h;break;
+case LD_H_A:   CPU.HL.B.h=CPU.AF.B.h;break;
+case LD_L_A:   CPU.HL.B.l=CPU.AF.B.h;break;
+case LD_A_A:   CPU.AF.B.h=CPU.AF.B.h;break;
+case LD_xHL_A: WrZ80(CPU.HL.W,CPU.AF.B.h);break;
+
+case LD_xBC_A: WrZ80(CPU.BC.W,CPU.AF.B.h);break;
+case LD_xDE_A: WrZ80(CPU.DE.W,CPU.AF.B.h);break;
+
+case LD_B_xHL:    CPU.BC.B.h=RdZ80(CPU.HL.W);break;
+case LD_C_xHL:    CPU.BC.B.l=RdZ80(CPU.HL.W);break;
+case LD_D_xHL:    CPU.DE.B.h=RdZ80(CPU.HL.W);break;
+case LD_E_xHL:    CPU.DE.B.l=RdZ80(CPU.HL.W);break;
+case LD_H_xHL:    CPU.HL.B.h=RdZ80(CPU.HL.W);break;
+case LD_L_xHL:    CPU.HL.B.l=RdZ80(CPU.HL.W);break;
+case LD_A_xHL:    CPU.AF.B.h=RdZ80(CPU.HL.W);break;
+
+case LD_B_BYTE:   CPU.BC.B.h=OpZ80(CPU.PC.W++);break;
+case LD_C_BYTE:   CPU.BC.B.l=OpZ80(CPU.PC.W++);break;
+case LD_D_BYTE:   CPU.DE.B.h=OpZ80(CPU.PC.W++);break;
+case LD_E_BYTE:   CPU.DE.B.l=OpZ80(CPU.PC.W++);break;
+case LD_H_BYTE:   CPU.HL.B.h=OpZ80(CPU.PC.W++);break;
+case LD_L_BYTE:   CPU.HL.B.l=OpZ80(CPU.PC.W++);break;
+case LD_A_BYTE:   CPU.AF.B.h=OpZ80(CPU.PC.W++);break;
+case LD_xHL_BYTE: WrZ80(CPU.HL.W,OpZ80(CPU.PC.W++));break;
 
 case LD_xWORD_HL:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  WrZ80(J.W++,R->HL.B.l);
-  WrZ80(J.W,R->HL.B.h);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  WrZ80(J.W++,CPU.HL.B.l);
+  WrZ80(J.W,CPU.HL.B.h);
   break;
 
 case LD_HL_xWORD:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  R->HL.B.l=RdZ80(J.W++);
-  R->HL.B.h=RdZ80(J.W);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  CPU.HL.B.l=RdZ80(J.W++);
+  CPU.HL.B.h=RdZ80(J.W);
   break;
 
 case LD_A_xWORD:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++); 
-  R->AF.B.h=RdZ80(J.W);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++); 
+  CPU.AF.B.h=RdZ80(J.W);
   break;
 
 case LD_xWORD_A:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  WrZ80(J.W,R->AF.B.h);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  WrZ80(J.W,CPU.AF.B.h);
   break;
 
 case EX_HL_xSP:
-  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->HL.B.l);
-  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->HL.B.h);
-  R->HL.W=J.W;
+  J.B.l=RdZ80(CPU.SP.W);WrZ80(CPU.SP.W++,CPU.HL.B.l);
+  J.B.h=RdZ80(CPU.SP.W);WrZ80(CPU.SP.W--,CPU.HL.B.h);
+  CPU.HL.W=J.W;
   break;
 
 case DAA:
-  J.W=R->AF.B.h;
-  if(R->AF.B.l&C_FLAG) J.W|=256;
-  if(R->AF.B.l&H_FLAG) J.W|=512;
-  if(R->AF.B.l&N_FLAG) J.W|=1024;
-  R->AF.W=DAATable[J.W];
+  J.W=CPU.AF.B.h;
+  if(CPU.AF.B.l&C_FLAG) J.W|=256;
+  if(CPU.AF.B.l&H_FLAG) J.W|=512;
+  if(CPU.AF.B.l&N_FLAG) J.W|=1024;
+  CPU.AF.W=DAATable[J.W];
   break;
 
 default:
-  if(R->TrapBadOps)
+  if(CPU.TrapBadOps)
     printf
     (
       "[Z80 %lX] Unrecognized instruction: %02X at PC=%04X\n",
-      (long)R->User,OpZ80(R->PC.W-1),R->PC.W-1
+      (long)CPU.User,OpZ80(CPU.PC.W-1),CPU.PC.W-1
     );
   break;
diff --git a/arm9/source/cpu/z80/CodesCB.h b/arm9/source/cpu/z80/CodesCB.h
index 6db53c44..418916d0 100644
--- a/arm9/source/cpu/z80/CodesCB.h
+++ b/arm9/source/cpu/z80/CodesCB.h
@@ -11,194 +11,194 @@
 /**     changes to this file.                               **/
 /*************************************************************/
 
-case RLC_B: M_RLC(R->BC.B.h);break;  case RLC_C: M_RLC(R->BC.B.l);break;
-case RLC_D: M_RLC(R->DE.B.h);break;  case RLC_E: M_RLC(R->DE.B.l);break;
-case RLC_H: M_RLC(R->HL.B.h);break;  case RLC_L: M_RLC(R->HL.B.l);break;
-case RLC_xHL: I=RdZ80(R->HL.W);M_RLC(I);WrZ80(R->HL.W,I);break;
-case RLC_A: M_RLC(R->AF.B.h);break;
-
-case RRC_B: M_RRC(R->BC.B.h);break;  case RRC_C: M_RRC(R->BC.B.l);break;
-case RRC_D: M_RRC(R->DE.B.h);break;  case RRC_E: M_RRC(R->DE.B.l);break;
-case RRC_H: M_RRC(R->HL.B.h);break;  case RRC_L: M_RRC(R->HL.B.l);break;
-case RRC_xHL: I=RdZ80(R->HL.W);M_RRC(I);WrZ80(R->HL.W,I);break;
-case RRC_A: M_RRC(R->AF.B.h);break;
-
-case RL_B: M_RL(R->BC.B.h);break;  case RL_C: M_RL(R->BC.B.l);break;
-case RL_D: M_RL(R->DE.B.h);break;  case RL_E: M_RL(R->DE.B.l);break;
-case RL_H: M_RL(R->HL.B.h);break;  case RL_L: M_RL(R->HL.B.l);break;
-case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
-case RL_A: M_RL(R->AF.B.h);break;
-
-case RR_B: M_RR(R->BC.B.h);break;  case RR_C: M_RR(R->BC.B.l);break;
-case RR_D: M_RR(R->DE.B.h);break;  case RR_E: M_RR(R->DE.B.l);break;
-case RR_H: M_RR(R->HL.B.h);break;  case RR_L: M_RR(R->HL.B.l);break;
-case RR_xHL: I=RdZ80(R->HL.W);M_RR(I);WrZ80(R->HL.W,I);break;
-case RR_A: M_RR(R->AF.B.h);break;
-
-case SLA_B: M_SLA(R->BC.B.h);break;  case SLA_C: M_SLA(R->BC.B.l);break;
-case SLA_D: M_SLA(R->DE.B.h);break;  case SLA_E: M_SLA(R->DE.B.l);break;
-case SLA_H: M_SLA(R->HL.B.h);break;  case SLA_L: M_SLA(R->HL.B.l);break;
-case SLA_xHL: I=RdZ80(R->HL.W);M_SLA(I);WrZ80(R->HL.W,I);break;
-case SLA_A: M_SLA(R->AF.B.h);break;
-
-case SRA_B: M_SRA(R->BC.B.h);break;  case SRA_C: M_SRA(R->BC.B.l);break;
-case SRA_D: M_SRA(R->DE.B.h);break;  case SRA_E: M_SRA(R->DE.B.l);break;
-case SRA_H: M_SRA(R->HL.B.h);break;  case SRA_L: M_SRA(R->HL.B.l);break;
-case SRA_xHL: I=RdZ80(R->HL.W);M_SRA(I);WrZ80(R->HL.W,I);break;
-case SRA_A: M_SRA(R->AF.B.h);break;
-
-case SLL_B: M_SLL(R->BC.B.h);break;  case SLL_C: M_SLL(R->BC.B.l);break;
-case SLL_D: M_SLL(R->DE.B.h);break;  case SLL_E: M_SLL(R->DE.B.l);break;
-case SLL_H: M_SLL(R->HL.B.h);break;  case SLL_L: M_SLL(R->HL.B.l);break;
-case SLL_xHL: I=RdZ80(R->HL.W);M_SLL(I);WrZ80(R->HL.W,I);break;
-case SLL_A: M_SLL(R->AF.B.h);break;
-
-case SRL_B: M_SRL(R->BC.B.h);break;  case SRL_C: M_SRL(R->BC.B.l);break;
-case SRL_D: M_SRL(R->DE.B.h);break;  case SRL_E: M_SRL(R->DE.B.l);break;
-case SRL_H: M_SRL(R->HL.B.h);break;  case SRL_L: M_SRL(R->HL.B.l);break;
-case SRL_xHL: I=RdZ80(R->HL.W);M_SRL(I);WrZ80(R->HL.W,I);break;
-case SRL_A: M_SRL(R->AF.B.h);break;
+case RLC_B: M_RLC(CPU.BC.B.h);break;  case RLC_C: M_RLC(CPU.BC.B.l);break;
+case RLC_D: M_RLC(CPU.DE.B.h);break;  case RLC_E: M_RLC(CPU.DE.B.l);break;
+case RLC_H: M_RLC(CPU.HL.B.h);break;  case RLC_L: M_RLC(CPU.HL.B.l);break;
+case RLC_xHL: I=RdZ80(CPU.HL.W);M_RLC(I);WrZ80(CPU.HL.W,I);break;
+case RLC_A: M_RLC(CPU.AF.B.h);break;
+
+case RRC_B: M_RRC(CPU.BC.B.h);break;  case RRC_C: M_RRC(CPU.BC.B.l);break;
+case RRC_D: M_RRC(CPU.DE.B.h);break;  case RRC_E: M_RRC(CPU.DE.B.l);break;
+case RRC_H: M_RRC(CPU.HL.B.h);break;  case RRC_L: M_RRC(CPU.HL.B.l);break;
+case RRC_xHL: I=RdZ80(CPU.HL.W);M_RRC(I);WrZ80(CPU.HL.W,I);break;
+case RRC_A: M_RRC(CPU.AF.B.h);break;
+
+case RL_B: M_RL(CPU.BC.B.h);break;  case RL_C: M_RL(CPU.BC.B.l);break;
+case RL_D: M_RL(CPU.DE.B.h);break;  case RL_E: M_RL(CPU.DE.B.l);break;
+case RL_H: M_RL(CPU.HL.B.h);break;  case RL_L: M_RL(CPU.HL.B.l);break;
+case RL_xHL: I=RdZ80(CPU.HL.W);M_RL(I);WrZ80(CPU.HL.W,I);break;
+case RL_A: M_RL(CPU.AF.B.h);break;
+
+case RR_B: M_RR(CPU.BC.B.h);break;  case RR_C: M_RR(CPU.BC.B.l);break;
+case RR_D: M_RR(CPU.DE.B.h);break;  case RR_E: M_RR(CPU.DE.B.l);break;
+case RR_H: M_RR(CPU.HL.B.h);break;  case RR_L: M_RR(CPU.HL.B.l);break;
+case RR_xHL: I=RdZ80(CPU.HL.W);M_RR(I);WrZ80(CPU.HL.W,I);break;
+case RR_A: M_RR(CPU.AF.B.h);break;
+
+case SLA_B: M_SLA(CPU.BC.B.h);break;  case SLA_C: M_SLA(CPU.BC.B.l);break;
+case SLA_D: M_SLA(CPU.DE.B.h);break;  case SLA_E: M_SLA(CPU.DE.B.l);break;
+case SLA_H: M_SLA(CPU.HL.B.h);break;  case SLA_L: M_SLA(CPU.HL.B.l);break;
+case SLA_xHL: I=RdZ80(CPU.HL.W);M_SLA(I);WrZ80(CPU.HL.W,I);break;
+case SLA_A: M_SLA(CPU.AF.B.h);break;
+
+case SRA_B: M_SRA(CPU.BC.B.h);break;  case SRA_C: M_SRA(CPU.BC.B.l);break;
+case SRA_D: M_SRA(CPU.DE.B.h);break;  case SRA_E: M_SRA(CPU.DE.B.l);break;
+case SRA_H: M_SRA(CPU.HL.B.h);break;  case SRA_L: M_SRA(CPU.HL.B.l);break;
+case SRA_xHL: I=RdZ80(CPU.HL.W);M_SRA(I);WrZ80(CPU.HL.W,I);break;
+case SRA_A: M_SRA(CPU.AF.B.h);break;
+
+case SLL_B: M_SLL(CPU.BC.B.h);break;  case SLL_C: M_SLL(CPU.BC.B.l);break;
+case SLL_D: M_SLL(CPU.DE.B.h);break;  case SLL_E: M_SLL(CPU.DE.B.l);break;
+case SLL_H: M_SLL(CPU.HL.B.h);break;  case SLL_L: M_SLL(CPU.HL.B.l);break;
+case SLL_xHL: I=RdZ80(CPU.HL.W);M_SLL(I);WrZ80(CPU.HL.W,I);break;
+case SLL_A: M_SLL(CPU.AF.B.h);break;
+
+case SRL_B: M_SRL(CPU.BC.B.h);break;  case SRL_C: M_SRL(CPU.BC.B.l);break;
+case SRL_D: M_SRL(CPU.DE.B.h);break;  case SRL_E: M_SRL(CPU.DE.B.l);break;
+case SRL_H: M_SRL(CPU.HL.B.h);break;  case SRL_L: M_SRL(CPU.HL.B.l);break;
+case SRL_xHL: I=RdZ80(CPU.HL.W);M_SRL(I);WrZ80(CPU.HL.W,I);break;
+case SRL_A: M_SRL(CPU.AF.B.h);break;
     
-case BIT0_B: M_BIT(0,R->BC.B.h);break;  case BIT0_C: M_BIT(0,R->BC.B.l);break;
-case BIT0_D: M_BIT(0,R->DE.B.h);break;  case BIT0_E: M_BIT(0,R->DE.B.l);break;
-case BIT0_H: M_BIT(0,R->HL.B.h);break;  case BIT0_L: M_BIT(0,R->HL.B.l);break;
-case BIT0_xHL: I=RdZ80(R->HL.W);M_BIT(0,I);break;
-case BIT0_A: M_BIT(0,R->AF.B.h);break;
-
-case BIT1_B: M_BIT(1,R->BC.B.h);break;  case BIT1_C: M_BIT(1,R->BC.B.l);break;
-case BIT1_D: M_BIT(1,R->DE.B.h);break;  case BIT1_E: M_BIT(1,R->DE.B.l);break;
-case BIT1_H: M_BIT(1,R->HL.B.h);break;  case BIT1_L: M_BIT(1,R->HL.B.l);break;
-case BIT1_xHL: I=RdZ80(R->HL.W);M_BIT(1,I);break;
-case BIT1_A: M_BIT(1,R->AF.B.h);break;
-
-case BIT2_B: M_BIT(2,R->BC.B.h);break;  case BIT2_C: M_BIT(2,R->BC.B.l);break;
-case BIT2_D: M_BIT(2,R->DE.B.h);break;  case BIT2_E: M_BIT(2,R->DE.B.l);break;
-case BIT2_H: M_BIT(2,R->HL.B.h);break;  case BIT2_L: M_BIT(2,R->HL.B.l);break;
-case BIT2_xHL: I=RdZ80(R->HL.W);M_BIT(2,I);break;
-case BIT2_A: M_BIT(2,R->AF.B.h);break;
-
-case BIT3_B: M_BIT(3,R->BC.B.h);break;  case BIT3_C: M_BIT(3,R->BC.B.l);break;
-case BIT3_D: M_BIT(3,R->DE.B.h);break;  case BIT3_E: M_BIT(3,R->DE.B.l);break;
-case BIT3_H: M_BIT(3,R->HL.B.h);break;  case BIT3_L: M_BIT(3,R->HL.B.l);break;
-case BIT3_xHL: I=RdZ80(R->HL.W);M_BIT(3,I);break;
-case BIT3_A: M_BIT(3,R->AF.B.h);break;
-
-case BIT4_B: M_BIT(4,R->BC.B.h);break;  case BIT4_C: M_BIT(4,R->BC.B.l);break;
-case BIT4_D: M_BIT(4,R->DE.B.h);break;  case BIT4_E: M_BIT(4,R->DE.B.l);break;
-case BIT4_H: M_BIT(4,R->HL.B.h);break;  case BIT4_L: M_BIT(4,R->HL.B.l);break;
-case BIT4_xHL: I=RdZ80(R->HL.W);M_BIT(4,I);break;
-case BIT4_A: M_BIT(4,R->AF.B.h);break;
-
-case BIT5_B: M_BIT(5,R->BC.B.h);break;  case BIT5_C: M_BIT(5,R->BC.B.l);break;
-case BIT5_D: M_BIT(5,R->DE.B.h);break;  case BIT5_E: M_BIT(5,R->DE.B.l);break;
-case BIT5_H: M_BIT(5,R->HL.B.h);break;  case BIT5_L: M_BIT(5,R->HL.B.l);break;
-case BIT5_xHL: I=RdZ80(R->HL.W);M_BIT(5,I);break;
-case BIT5_A: M_BIT(5,R->AF.B.h);break;
-
-case BIT6_B: M_BIT(6,R->BC.B.h);break;  case BIT6_C: M_BIT(6,R->BC.B.l);break;
-case BIT6_D: M_BIT(6,R->DE.B.h);break;  case BIT6_E: M_BIT(6,R->DE.B.l);break;
-case BIT6_H: M_BIT(6,R->HL.B.h);break;  case BIT6_L: M_BIT(6,R->HL.B.l);break;
-case BIT6_xHL: I=RdZ80(R->HL.W);M_BIT(6,I);break;
-case BIT6_A: M_BIT(6,R->AF.B.h);break;
-
-case BIT7_B: M_BIT(7,R->BC.B.h);break;  case BIT7_C: M_BIT(7,R->BC.B.l);break;
-case BIT7_D: M_BIT(7,R->DE.B.h);break;  case BIT7_E: M_BIT(7,R->DE.B.l);break;
-case BIT7_H: M_BIT(7,R->HL.B.h);break;  case BIT7_L: M_BIT(7,R->HL.B.l);break;
-case BIT7_xHL: I=RdZ80(R->HL.W);M_BIT(7,I);break;
-case BIT7_A: M_BIT(7,R->AF.B.h);break;
-
-case RES0_B: M_RES(0,R->BC.B.h);break;  case RES0_C: M_RES(0,R->BC.B.l);break;
-case RES0_D: M_RES(0,R->DE.B.h);break;  case RES0_E: M_RES(0,R->DE.B.l);break;
-case RES0_H: M_RES(0,R->HL.B.h);break;  case RES0_L: M_RES(0,R->HL.B.l);break;
-case RES0_xHL: I=RdZ80(R->HL.W);M_RES(0,I);WrZ80(R->HL.W,I);break;
-case RES0_A: M_RES(0,R->AF.B.h);break;
-
-case RES1_B: M_RES(1,R->BC.B.h);break;  case RES1_C: M_RES(1,R->BC.B.l);break;
-case RES1_D: M_RES(1,R->DE.B.h);break;  case RES1_E: M_RES(1,R->DE.B.l);break;
-case RES1_H: M_RES(1,R->HL.B.h);break;  case RES1_L: M_RES(1,R->HL.B.l);break;
-case RES1_xHL: I=RdZ80(R->HL.W);M_RES(1,I);WrZ80(R->HL.W,I);break;
-case RES1_A: M_RES(1,R->AF.B.h);break;
-
-case RES2_B: M_RES(2,R->BC.B.h);break;  case RES2_C: M_RES(2,R->BC.B.l);break;
-case RES2_D: M_RES(2,R->DE.B.h);break;  case RES2_E: M_RES(2,R->DE.B.l);break;
-case RES2_H: M_RES(2,R->HL.B.h);break;  case RES2_L: M_RES(2,R->HL.B.l);break;
-case RES2_xHL: I=RdZ80(R->HL.W);M_RES(2,I);WrZ80(R->HL.W,I);break;
-case RES2_A: M_RES(2,R->AF.B.h);break;
-
-case RES3_B: M_RES(3,R->BC.B.h);break;  case RES3_C: M_RES(3,R->BC.B.l);break;
-case RES3_D: M_RES(3,R->DE.B.h);break;  case RES3_E: M_RES(3,R->DE.B.l);break;
-case RES3_H: M_RES(3,R->HL.B.h);break;  case RES3_L: M_RES(3,R->HL.B.l);break;
-case RES3_xHL: I=RdZ80(R->HL.W);M_RES(3,I);WrZ80(R->HL.W,I);break;
-case RES3_A: M_RES(3,R->AF.B.h);break;
-
-case RES4_B: M_RES(4,R->BC.B.h);break;  case RES4_C: M_RES(4,R->BC.B.l);break;
-case RES4_D: M_RES(4,R->DE.B.h);break;  case RES4_E: M_RES(4,R->DE.B.l);break;
-case RES4_H: M_RES(4,R->HL.B.h);break;  case RES4_L: M_RES(4,R->HL.B.l);break;
-case RES4_xHL: I=RdZ80(R->HL.W);M_RES(4,I);WrZ80(R->HL.W,I);break;
-case RES4_A: M_RES(4,R->AF.B.h);break;
-
-case RES5_B: M_RES(5,R->BC.B.h);break;  case RES5_C: M_RES(5,R->BC.B.l);break;
-case RES5_D: M_RES(5,R->DE.B.h);break;  case RES5_E: M_RES(5,R->DE.B.l);break;
-case RES5_H: M_RES(5,R->HL.B.h);break;  case RES5_L: M_RES(5,R->HL.B.l);break;
-case RES5_xHL: I=RdZ80(R->HL.W);M_RES(5,I);WrZ80(R->HL.W,I);break;
-case RES5_A: M_RES(5,R->AF.B.h);break;
-
-case RES6_B: M_RES(6,R->BC.B.h);break;  case RES6_C: M_RES(6,R->BC.B.l);break;
-case RES6_D: M_RES(6,R->DE.B.h);break;  case RES6_E: M_RES(6,R->DE.B.l);break;
-case RES6_H: M_RES(6,R->HL.B.h);break;  case RES6_L: M_RES(6,R->HL.B.l);break;
-case RES6_xHL: I=RdZ80(R->HL.W);M_RES(6,I);WrZ80(R->HL.W,I);break;
-case RES6_A: M_RES(6,R->AF.B.h);break;
-
-case RES7_B: M_RES(7,R->BC.B.h);break;  case RES7_C: M_RES(7,R->BC.B.l);break;
-case RES7_D: M_RES(7,R->DE.B.h);break;  case RES7_E: M_RES(7,R->DE.B.l);break;
-case RES7_H: M_RES(7,R->HL.B.h);break;  case RES7_L: M_RES(7,R->HL.B.l);break;
-case RES7_xHL: I=RdZ80(R->HL.W);M_RES(7,I);WrZ80(R->HL.W,I);break;
-case RES7_A: M_RES(7,R->AF.B.h);break;
-
-case SET0_B: M_SET(0,R->BC.B.h);break;  case SET0_C: M_SET(0,R->BC.B.l);break;
-case SET0_D: M_SET(0,R->DE.B.h);break;  case SET0_E: M_SET(0,R->DE.B.l);break;
-case SET0_H: M_SET(0,R->HL.B.h);break;  case SET0_L: M_SET(0,R->HL.B.l);break;
-case SET0_xHL: I=RdZ80(R->HL.W);M_SET(0,I);WrZ80(R->HL.W,I);break;
-case SET0_A: M_SET(0,R->AF.B.h);break;
-
-case SET1_B: M_SET(1,R->BC.B.h);break;  case SET1_C: M_SET(1,R->BC.B.l);break;
-case SET1_D: M_SET(1,R->DE.B.h);break;  case SET1_E: M_SET(1,R->DE.B.l);break;
-case SET1_H: M_SET(1,R->HL.B.h);break;  case SET1_L: M_SET(1,R->HL.B.l);break;
-case SET1_xHL: I=RdZ80(R->HL.W);M_SET(1,I);WrZ80(R->HL.W,I);break;
-case SET1_A: M_SET(1,R->AF.B.h);break;
-
-case SET2_B: M_SET(2,R->BC.B.h);break;  case SET2_C: M_SET(2,R->BC.B.l);break;
-case SET2_D: M_SET(2,R->DE.B.h);break;  case SET2_E: M_SET(2,R->DE.B.l);break;
-case SET2_H: M_SET(2,R->HL.B.h);break;  case SET2_L: M_SET(2,R->HL.B.l);break;
-case SET2_xHL: I=RdZ80(R->HL.W);M_SET(2,I);WrZ80(R->HL.W,I);break;
-case SET2_A: M_SET(2,R->AF.B.h);break;
-
-case SET3_B: M_SET(3,R->BC.B.h);break;  case SET3_C: M_SET(3,R->BC.B.l);break;
-case SET3_D: M_SET(3,R->DE.B.h);break;  case SET3_E: M_SET(3,R->DE.B.l);break;
-case SET3_H: M_SET(3,R->HL.B.h);break;  case SET3_L: M_SET(3,R->HL.B.l);break;
-case SET3_xHL: I=RdZ80(R->HL.W);M_SET(3,I);WrZ80(R->HL.W,I);break;
-case SET3_A: M_SET(3,R->AF.B.h);break;
-
-case SET4_B: M_SET(4,R->BC.B.h);break;  case SET4_C: M_SET(4,R->BC.B.l);break;
-case SET4_D: M_SET(4,R->DE.B.h);break;  case SET4_E: M_SET(4,R->DE.B.l);break;
-case SET4_H: M_SET(4,R->HL.B.h);break;  case SET4_L: M_SET(4,R->HL.B.l);break;
-case SET4_xHL: I=RdZ80(R->HL.W);M_SET(4,I);WrZ80(R->HL.W,I);break;
-case SET4_A: M_SET(4,R->AF.B.h);break;
-
-case SET5_B: M_SET(5,R->BC.B.h);break;  case SET5_C: M_SET(5,R->BC.B.l);break;
-case SET5_D: M_SET(5,R->DE.B.h);break;  case SET5_E: M_SET(5,R->DE.B.l);break;
-case SET5_H: M_SET(5,R->HL.B.h);break;  case SET5_L: M_SET(5,R->HL.B.l);break;
-case SET5_xHL: I=RdZ80(R->HL.W);M_SET(5,I);WrZ80(R->HL.W,I);break;
-case SET5_A: M_SET(5,R->AF.B.h);break;
-
-case SET6_B: M_SET(6,R->BC.B.h);break;  case SET6_C: M_SET(6,R->BC.B.l);break;
-case SET6_D: M_SET(6,R->DE.B.h);break;  case SET6_E: M_SET(6,R->DE.B.l);break;
-case SET6_H: M_SET(6,R->HL.B.h);break;  case SET6_L: M_SET(6,R->HL.B.l);break;
-case SET6_xHL: I=RdZ80(R->HL.W);M_SET(6,I);WrZ80(R->HL.W,I);break;
-case SET6_A: M_SET(6,R->AF.B.h);break;
-
-case SET7_B: M_SET(7,R->BC.B.h);break;  case SET7_C: M_SET(7,R->BC.B.l);break;
-case SET7_D: M_SET(7,R->DE.B.h);break;  case SET7_E: M_SET(7,R->DE.B.l);break;
-case SET7_H: M_SET(7,R->HL.B.h);break;  case SET7_L: M_SET(7,R->HL.B.l);break;
-case SET7_xHL: I=RdZ80(R->HL.W);M_SET(7,I);WrZ80(R->HL.W,I);break;
-case SET7_A: M_SET(7,R->AF.B.h);break;
+case BIT0_B: M_BIT(0,CPU.BC.B.h);break;  case BIT0_C: M_BIT(0,CPU.BC.B.l);break;
+case BIT0_D: M_BIT(0,CPU.DE.B.h);break;  case BIT0_E: M_BIT(0,CPU.DE.B.l);break;
+case BIT0_H: M_BIT(0,CPU.HL.B.h);break;  case BIT0_L: M_BIT(0,CPU.HL.B.l);break;
+case BIT0_xHL: I=RdZ80(CPU.HL.W);M_BIT(0,I);break;
+case BIT0_A: M_BIT(0,CPU.AF.B.h);break;
+
+case BIT1_B: M_BIT(1,CPU.BC.B.h);break;  case BIT1_C: M_BIT(1,CPU.BC.B.l);break;
+case BIT1_D: M_BIT(1,CPU.DE.B.h);break;  case BIT1_E: M_BIT(1,CPU.DE.B.l);break;
+case BIT1_H: M_BIT(1,CPU.HL.B.h);break;  case BIT1_L: M_BIT(1,CPU.HL.B.l);break;
+case BIT1_xHL: I=RdZ80(CPU.HL.W);M_BIT(1,I);break;
+case BIT1_A: M_BIT(1,CPU.AF.B.h);break;
+
+case BIT2_B: M_BIT(2,CPU.BC.B.h);break;  case BIT2_C: M_BIT(2,CPU.BC.B.l);break;
+case BIT2_D: M_BIT(2,CPU.DE.B.h);break;  case BIT2_E: M_BIT(2,CPU.DE.B.l);break;
+case BIT2_H: M_BIT(2,CPU.HL.B.h);break;  case BIT2_L: M_BIT(2,CPU.HL.B.l);break;
+case BIT2_xHL: I=RdZ80(CPU.HL.W);M_BIT(2,I);break;
+case BIT2_A: M_BIT(2,CPU.AF.B.h);break;
+
+case BIT3_B: M_BIT(3,CPU.BC.B.h);break;  case BIT3_C: M_BIT(3,CPU.BC.B.l);break;
+case BIT3_D: M_BIT(3,CPU.DE.B.h);break;  case BIT3_E: M_BIT(3,CPU.DE.B.l);break;
+case BIT3_H: M_BIT(3,CPU.HL.B.h);break;  case BIT3_L: M_BIT(3,CPU.HL.B.l);break;
+case BIT3_xHL: I=RdZ80(CPU.HL.W);M_BIT(3,I);break;
+case BIT3_A: M_BIT(3,CPU.AF.B.h);break;
+
+case BIT4_B: M_BIT(4,CPU.BC.B.h);break;  case BIT4_C: M_BIT(4,CPU.BC.B.l);break;
+case BIT4_D: M_BIT(4,CPU.DE.B.h);break;  case BIT4_E: M_BIT(4,CPU.DE.B.l);break;
+case BIT4_H: M_BIT(4,CPU.HL.B.h);break;  case BIT4_L: M_BIT(4,CPU.HL.B.l);break;
+case BIT4_xHL: I=RdZ80(CPU.HL.W);M_BIT(4,I);break;
+case BIT4_A: M_BIT(4,CPU.AF.B.h);break;
+
+case BIT5_B: M_BIT(5,CPU.BC.B.h);break;  case BIT5_C: M_BIT(5,CPU.BC.B.l);break;
+case BIT5_D: M_BIT(5,CPU.DE.B.h);break;  case BIT5_E: M_BIT(5,CPU.DE.B.l);break;
+case BIT5_H: M_BIT(5,CPU.HL.B.h);break;  case BIT5_L: M_BIT(5,CPU.HL.B.l);break;
+case BIT5_xHL: I=RdZ80(CPU.HL.W);M_BIT(5,I);break;
+case BIT5_A: M_BIT(5,CPU.AF.B.h);break;
+
+case BIT6_B: M_BIT(6,CPU.BC.B.h);break;  case BIT6_C: M_BIT(6,CPU.BC.B.l);break;
+case BIT6_D: M_BIT(6,CPU.DE.B.h);break;  case BIT6_E: M_BIT(6,CPU.DE.B.l);break;
+case BIT6_H: M_BIT(6,CPU.HL.B.h);break;  case BIT6_L: M_BIT(6,CPU.HL.B.l);break;
+case BIT6_xHL: I=RdZ80(CPU.HL.W);M_BIT(6,I);break;
+case BIT6_A: M_BIT(6,CPU.AF.B.h);break;
+
+case BIT7_B: M_BIT(7,CPU.BC.B.h);break;  case BIT7_C: M_BIT(7,CPU.BC.B.l);break;
+case BIT7_D: M_BIT(7,CPU.DE.B.h);break;  case BIT7_E: M_BIT(7,CPU.DE.B.l);break;
+case BIT7_H: M_BIT(7,CPU.HL.B.h);break;  case BIT7_L: M_BIT(7,CPU.HL.B.l);break;
+case BIT7_xHL: I=RdZ80(CPU.HL.W);M_BIT(7,I);break;
+case BIT7_A: M_BIT(7,CPU.AF.B.h);break;
+
+case RES0_B: M_RES(0,CPU.BC.B.h);break;  case RES0_C: M_RES(0,CPU.BC.B.l);break;
+case RES0_D: M_RES(0,CPU.DE.B.h);break;  case RES0_E: M_RES(0,CPU.DE.B.l);break;
+case RES0_H: M_RES(0,CPU.HL.B.h);break;  case RES0_L: M_RES(0,CPU.HL.B.l);break;
+case RES0_xHL: I=RdZ80(CPU.HL.W);M_RES(0,I);WrZ80(CPU.HL.W,I);break;
+case RES0_A: M_RES(0,CPU.AF.B.h);break;
+
+case RES1_B: M_RES(1,CPU.BC.B.h);break;  case RES1_C: M_RES(1,CPU.BC.B.l);break;
+case RES1_D: M_RES(1,CPU.DE.B.h);break;  case RES1_E: M_RES(1,CPU.DE.B.l);break;
+case RES1_H: M_RES(1,CPU.HL.B.h);break;  case RES1_L: M_RES(1,CPU.HL.B.l);break;
+case RES1_xHL: I=RdZ80(CPU.HL.W);M_RES(1,I);WrZ80(CPU.HL.W,I);break;
+case RES1_A: M_RES(1,CPU.AF.B.h);break;
+
+case RES2_B: M_RES(2,CPU.BC.B.h);break;  case RES2_C: M_RES(2,CPU.BC.B.l);break;
+case RES2_D: M_RES(2,CPU.DE.B.h);break;  case RES2_E: M_RES(2,CPU.DE.B.l);break;
+case RES2_H: M_RES(2,CPU.HL.B.h);break;  case RES2_L: M_RES(2,CPU.HL.B.l);break;
+case RES2_xHL: I=RdZ80(CPU.HL.W);M_RES(2,I);WrZ80(CPU.HL.W,I);break;
+case RES2_A: M_RES(2,CPU.AF.B.h);break;
+
+case RES3_B: M_RES(3,CPU.BC.B.h);break;  case RES3_C: M_RES(3,CPU.BC.B.l);break;
+case RES3_D: M_RES(3,CPU.DE.B.h);break;  case RES3_E: M_RES(3,CPU.DE.B.l);break;
+case RES3_H: M_RES(3,CPU.HL.B.h);break;  case RES3_L: M_RES(3,CPU.HL.B.l);break;
+case RES3_xHL: I=RdZ80(CPU.HL.W);M_RES(3,I);WrZ80(CPU.HL.W,I);break;
+case RES3_A: M_RES(3,CPU.AF.B.h);break;
+
+case RES4_B: M_RES(4,CPU.BC.B.h);break;  case RES4_C: M_RES(4,CPU.BC.B.l);break;
+case RES4_D: M_RES(4,CPU.DE.B.h);break;  case RES4_E: M_RES(4,CPU.DE.B.l);break;
+case RES4_H: M_RES(4,CPU.HL.B.h);break;  case RES4_L: M_RES(4,CPU.HL.B.l);break;
+case RES4_xHL: I=RdZ80(CPU.HL.W);M_RES(4,I);WrZ80(CPU.HL.W,I);break;
+case RES4_A: M_RES(4,CPU.AF.B.h);break;
+
+case RES5_B: M_RES(5,CPU.BC.B.h);break;  case RES5_C: M_RES(5,CPU.BC.B.l);break;
+case RES5_D: M_RES(5,CPU.DE.B.h);break;  case RES5_E: M_RES(5,CPU.DE.B.l);break;
+case RES5_H: M_RES(5,CPU.HL.B.h);break;  case RES5_L: M_RES(5,CPU.HL.B.l);break;
+case RES5_xHL: I=RdZ80(CPU.HL.W);M_RES(5,I);WrZ80(CPU.HL.W,I);break;
+case RES5_A: M_RES(5,CPU.AF.B.h);break;
+
+case RES6_B: M_RES(6,CPU.BC.B.h);break;  case RES6_C: M_RES(6,CPU.BC.B.l);break;
+case RES6_D: M_RES(6,CPU.DE.B.h);break;  case RES6_E: M_RES(6,CPU.DE.B.l);break;
+case RES6_H: M_RES(6,CPU.HL.B.h);break;  case RES6_L: M_RES(6,CPU.HL.B.l);break;
+case RES6_xHL: I=RdZ80(CPU.HL.W);M_RES(6,I);WrZ80(CPU.HL.W,I);break;
+case RES6_A: M_RES(6,CPU.AF.B.h);break;
+
+case RES7_B: M_RES(7,CPU.BC.B.h);break;  case RES7_C: M_RES(7,CPU.BC.B.l);break;
+case RES7_D: M_RES(7,CPU.DE.B.h);break;  case RES7_E: M_RES(7,CPU.DE.B.l);break;
+case RES7_H: M_RES(7,CPU.HL.B.h);break;  case RES7_L: M_RES(7,CPU.HL.B.l);break;
+case RES7_xHL: I=RdZ80(CPU.HL.W);M_RES(7,I);WrZ80(CPU.HL.W,I);break;
+case RES7_A: M_RES(7,CPU.AF.B.h);break;
+
+case SET0_B: M_SET(0,CPU.BC.B.h);break;  case SET0_C: M_SET(0,CPU.BC.B.l);break;
+case SET0_D: M_SET(0,CPU.DE.B.h);break;  case SET0_E: M_SET(0,CPU.DE.B.l);break;
+case SET0_H: M_SET(0,CPU.HL.B.h);break;  case SET0_L: M_SET(0,CPU.HL.B.l);break;
+case SET0_xHL: I=RdZ80(CPU.HL.W);M_SET(0,I);WrZ80(CPU.HL.W,I);break;
+case SET0_A: M_SET(0,CPU.AF.B.h);break;
+
+case SET1_B: M_SET(1,CPU.BC.B.h);break;  case SET1_C: M_SET(1,CPU.BC.B.l);break;
+case SET1_D: M_SET(1,CPU.DE.B.h);break;  case SET1_E: M_SET(1,CPU.DE.B.l);break;
+case SET1_H: M_SET(1,CPU.HL.B.h);break;  case SET1_L: M_SET(1,CPU.HL.B.l);break;
+case SET1_xHL: I=RdZ80(CPU.HL.W);M_SET(1,I);WrZ80(CPU.HL.W,I);break;
+case SET1_A: M_SET(1,CPU.AF.B.h);break;
+
+case SET2_B: M_SET(2,CPU.BC.B.h);break;  case SET2_C: M_SET(2,CPU.BC.B.l);break;
+case SET2_D: M_SET(2,CPU.DE.B.h);break;  case SET2_E: M_SET(2,CPU.DE.B.l);break;
+case SET2_H: M_SET(2,CPU.HL.B.h);break;  case SET2_L: M_SET(2,CPU.HL.B.l);break;
+case SET2_xHL: I=RdZ80(CPU.HL.W);M_SET(2,I);WrZ80(CPU.HL.W,I);break;
+case SET2_A: M_SET(2,CPU.AF.B.h);break;
+
+case SET3_B: M_SET(3,CPU.BC.B.h);break;  case SET3_C: M_SET(3,CPU.BC.B.l);break;
+case SET3_D: M_SET(3,CPU.DE.B.h);break;  case SET3_E: M_SET(3,CPU.DE.B.l);break;
+case SET3_H: M_SET(3,CPU.HL.B.h);break;  case SET3_L: M_SET(3,CPU.HL.B.l);break;
+case SET3_xHL: I=RdZ80(CPU.HL.W);M_SET(3,I);WrZ80(CPU.HL.W,I);break;
+case SET3_A: M_SET(3,CPU.AF.B.h);break;
+
+case SET4_B: M_SET(4,CPU.BC.B.h);break;  case SET4_C: M_SET(4,CPU.BC.B.l);break;
+case SET4_D: M_SET(4,CPU.DE.B.h);break;  case SET4_E: M_SET(4,CPU.DE.B.l);break;
+case SET4_H: M_SET(4,CPU.HL.B.h);break;  case SET4_L: M_SET(4,CPU.HL.B.l);break;
+case SET4_xHL: I=RdZ80(CPU.HL.W);M_SET(4,I);WrZ80(CPU.HL.W,I);break;
+case SET4_A: M_SET(4,CPU.AF.B.h);break;
+
+case SET5_B: M_SET(5,CPU.BC.B.h);break;  case SET5_C: M_SET(5,CPU.BC.B.l);break;
+case SET5_D: M_SET(5,CPU.DE.B.h);break;  case SET5_E: M_SET(5,CPU.DE.B.l);break;
+case SET5_H: M_SET(5,CPU.HL.B.h);break;  case SET5_L: M_SET(5,CPU.HL.B.l);break;
+case SET5_xHL: I=RdZ80(CPU.HL.W);M_SET(5,I);WrZ80(CPU.HL.W,I);break;
+case SET5_A: M_SET(5,CPU.AF.B.h);break;
+
+case SET6_B: M_SET(6,CPU.BC.B.h);break;  case SET6_C: M_SET(6,CPU.BC.B.l);break;
+case SET6_D: M_SET(6,CPU.DE.B.h);break;  case SET6_E: M_SET(6,CPU.DE.B.l);break;
+case SET6_H: M_SET(6,CPU.HL.B.h);break;  case SET6_L: M_SET(6,CPU.HL.B.l);break;
+case SET6_xHL: I=RdZ80(CPU.HL.W);M_SET(6,I);WrZ80(CPU.HL.W,I);break;
+case SET6_A: M_SET(6,CPU.AF.B.h);break;
+
+case SET7_B: M_SET(7,CPU.BC.B.h);break;  case SET7_C: M_SET(7,CPU.BC.B.l);break;
+case SET7_D: M_SET(7,CPU.DE.B.h);break;  case SET7_E: M_SET(7,CPU.DE.B.l);break;
+case SET7_H: M_SET(7,CPU.HL.B.h);break;  case SET7_L: M_SET(7,CPU.HL.B.l);break;
+case SET7_xHL: I=RdZ80(CPU.HL.W);M_SET(7,I);WrZ80(CPU.HL.W,I);break;
+case SET7_A: M_SET(7,CPU.AF.B.h);break;
diff --git a/arm9/source/cpu/z80/CodesED.h b/arm9/source/cpu/z80/CodesED.h
index cb4c8b5a..af8ef15f 100644
--- a/arm9/source/cpu/z80/CodesED.h
+++ b/arm9/source/cpu/z80/CodesED.h
@@ -26,258 +26,258 @@ case SBC_HL_HL: M_SBCW(HL);break;
 case SBC_HL_SP: M_SBCW(SP);break;
 
 case LD_xWORDe_HL:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  WrZ80(J.W++,R->HL.B.l);
-  WrZ80(J.W,R->HL.B.h);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  WrZ80(J.W++,CPU.HL.B.l);
+  WrZ80(J.W,CPU.HL.B.h);
   break;
 case LD_xWORDe_DE:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  WrZ80(J.W++,R->DE.B.l);
-  WrZ80(J.W,R->DE.B.h);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  WrZ80(J.W++,CPU.DE.B.l);
+  WrZ80(J.W,CPU.DE.B.h);
   break;
 case LD_xWORDe_BC:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  WrZ80(J.W++,R->BC.B.l);
-  WrZ80(J.W,R->BC.B.h);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  WrZ80(J.W++,CPU.BC.B.l);
+  WrZ80(J.W,CPU.BC.B.h);
   break;
 case LD_xWORDe_SP:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  WrZ80(J.W++,R->SP.B.l);
-  WrZ80(J.W,R->SP.B.h);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  WrZ80(J.W++,CPU.SP.B.l);
+  WrZ80(J.W,CPU.SP.B.h);
   break;
 
 case LD_HL_xWORDe:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  R->HL.B.l=RdZ80(J.W++);
-  R->HL.B.h=RdZ80(J.W);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  CPU.HL.B.l=RdZ80(J.W++);
+  CPU.HL.B.h=RdZ80(J.W);
   break;
 case LD_DE_xWORDe:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  R->DE.B.l=RdZ80(J.W++);
-  R->DE.B.h=RdZ80(J.W);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  CPU.DE.B.l=RdZ80(J.W++);
+  CPU.DE.B.h=RdZ80(J.W);
   break;
 case LD_BC_xWORDe:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  R->BC.B.l=RdZ80(J.W++);
-  R->BC.B.h=RdZ80(J.W);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  CPU.BC.B.l=RdZ80(J.W++);
+  CPU.BC.B.h=RdZ80(J.W);
   break;
 case LD_SP_xWORDe:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  R->SP.B.l=RdZ80(J.W++);
-  R->SP.B.h=RdZ80(J.W);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  CPU.SP.B.l=RdZ80(J.W++);
+  CPU.SP.B.h=RdZ80(J.W);
   break;
 
 case RRD:
-  I=RdZ80(R->HL.W);
-  J.B.l=(I>>4)|(R->AF.B.h<<4);
-  WrZ80(R->HL.W,J.B.l);
-  R->AF.B.h=(I&0x0F)|(R->AF.B.h&0xF0);
-  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  I=RdZ80(CPU.HL.W);
+  J.B.l=(I>>4)|(CPU.AF.B.h<<4);
+  WrZ80(CPU.HL.W,J.B.l);
+  CPU.AF.B.h=(I&0x0F)|(CPU.AF.B.h&0xF0);
+  CPU.AF.B.l=PZSTable[CPU.AF.B.h]|(CPU.AF.B.l&C_FLAG);
   break;
 case RLD:
-  I=RdZ80(R->HL.W);
-  J.B.l=(I<<4)|(R->AF.B.h&0x0F);
-  WrZ80(R->HL.W,J.B.l);
-  R->AF.B.h=(I>>4)|(R->AF.B.h&0xF0);
-  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  I=RdZ80(CPU.HL.W);
+  J.B.l=(I<<4)|(CPU.AF.B.h&0x0F);
+  WrZ80(CPU.HL.W,J.B.l);
+  CPU.AF.B.h=(I>>4)|(CPU.AF.B.h&0xF0);
+  CPU.AF.B.l=PZSTable[CPU.AF.B.h]|(CPU.AF.B.l&C_FLAG);
   break;
 
 case LD_A_I:
-  R->AF.B.h=R->I;
-  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  CPU.AF.B.h=CPU.I;
+  CPU.AF.B.l=(CPU.AF.B.l&C_FLAG)|(CPU.IFF&IFF_2? P_FLAG:0)|ZSTable[CPU.AF.B.h];
   break;
 
 case LD_A_R:
-  R->AF.B.h=R->R;
-  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  CPU.AF.B.h=CPU.R;
+  CPU.AF.B.l=(CPU.AF.B.l&C_FLAG)|(CPU.IFF&IFF_2? P_FLAG:0)|ZSTable[CPU.AF.B.h];
   break;
 
-case LD_I_A:   R->I=R->AF.B.h;break;
-case LD_R_A:   R->R=R->AF.B.h;break;
+case LD_I_A:   CPU.I=CPU.AF.B.h;break;
+case LD_R_A:   CPU.R=CPU.AF.B.h;break;
 
-case IM_0:     R->IFF&=~(IFF_IM1|IFF_IM2);break;
-case IM_1:     R->IFF=(R->IFF&~IFF_IM2)|IFF_IM1;break;
-case IM_2:     R->IFF=(R->IFF&~IFF_IM1)|IFF_IM2;break;
+case IM_0:     CPU.IFF&=~(IFF_IM1|IFF_IM2);break;
+case IM_1:     CPU.IFF=(CPU.IFF&~IFF_IM2)|IFF_IM1;break;
+case IM_2:     CPU.IFF=(CPU.IFF&~IFF_IM1)|IFF_IM2;break;
 
 case RETI:
-case RETN:     if(R->IFF&IFF_2) R->IFF|=IFF_1; else R->IFF&=~IFF_1;
+case RETN:     if(CPU.IFF&IFF_2) CPU.IFF|=IFF_1; else CPU.IFF&=~IFF_1;
                M_RET;break;
 
-case NEG:      I=R->AF.B.h;R->AF.B.h=0;M_SUB(I);break;
+case NEG:      I=CPU.AF.B.h;CPU.AF.B.h=0;M_SUB(I);break;
 
-case IN_B_xC:  M_IN(R->BC.B.h);break;
-case IN_C_xC:  M_IN(R->BC.B.l);break;
-case IN_D_xC:  M_IN(R->DE.B.h);break;
-case IN_E_xC:  M_IN(R->DE.B.l);break;
-case IN_H_xC:  M_IN(R->HL.B.h);break;
-case IN_L_xC:  M_IN(R->HL.B.l);break;
-case IN_A_xC:  M_IN(R->AF.B.h);break;
+case IN_B_xC:  M_IN(CPU.BC.B.h);break;
+case IN_C_xC:  M_IN(CPU.BC.B.l);break;
+case IN_D_xC:  M_IN(CPU.DE.B.h);break;
+case IN_E_xC:  M_IN(CPU.DE.B.l);break;
+case IN_H_xC:  M_IN(CPU.HL.B.h);break;
+case IN_L_xC:  M_IN(CPU.HL.B.l);break;
+case IN_A_xC:  M_IN(CPU.AF.B.h);break;
 case IN_F_xC:  M_IN(J.B.l);break;
 
-case OUT_xC_B: OutZ80(R->BC.W,R->BC.B.h);break;
-case OUT_xC_C: OutZ80(R->BC.W,R->BC.B.l);break;
-case OUT_xC_D: OutZ80(R->BC.W,R->DE.B.h);break;
-case OUT_xC_E: OutZ80(R->BC.W,R->DE.B.l);break;
-case OUT_xC_H: OutZ80(R->BC.W,R->HL.B.h);break;
-case OUT_xC_L: OutZ80(R->BC.W,R->HL.B.l);break;
-case OUT_xC_A: OutZ80(R->BC.W,R->AF.B.h);break;
-case OUT_xC_F: OutZ80(R->BC.W,0);break;
+case OUT_xC_B: OutZ80(CPU.BC.W,CPU.BC.B.h);break;
+case OUT_xC_C: OutZ80(CPU.BC.W,CPU.BC.B.l);break;
+case OUT_xC_D: OutZ80(CPU.BC.W,CPU.DE.B.h);break;
+case OUT_xC_E: OutZ80(CPU.BC.W,CPU.DE.B.l);break;
+case OUT_xC_H: OutZ80(CPU.BC.W,CPU.HL.B.h);break;
+case OUT_xC_L: OutZ80(CPU.BC.W,CPU.HL.B.l);break;
+case OUT_xC_A: OutZ80(CPU.BC.W,CPU.AF.B.h);break;
+case OUT_xC_F: OutZ80(CPU.BC.W,0);break;
 
 case INI:
-  WrZ80(R->HL.W++,InZ80(R->BC.W));
-  --R->BC.B.h;
-  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  WrZ80(CPU.HL.W++,InZ80(CPU.BC.W));
+  --CPU.BC.B.h;
+  CPU.AF.B.l=N_FLAG|(CPU.BC.B.h? 0:Z_FLAG);
   break;
 
 case INIR:
-  WrZ80(R->HL.W++,InZ80(R->BC.W));
-  if(--R->BC.B.h) { R->AF.B.l=N_FLAG;R->ICount-=21;R->PC.W-=2; }
-  else            { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount-=16; }
+  WrZ80(CPU.HL.W++,InZ80(CPU.BC.W));
+  if(--CPU.BC.B.h) { CPU.AF.B.l=N_FLAG;CPU.ICount-=21;CPU.PC.W-=2; }
+  else            { CPU.AF.B.l=Z_FLAG|N_FLAG;CPU.ICount-=16; }
   break;
 
 case IND:
-  WrZ80(R->HL.W--,InZ80(R->BC.W));
-  --R->BC.B.h;
-  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  WrZ80(CPU.HL.W--,InZ80(CPU.BC.W));
+  --CPU.BC.B.h;
+  CPU.AF.B.l=N_FLAG|(CPU.BC.B.h? 0:Z_FLAG);
   break;
 
 case INDR:
-  WrZ80(R->HL.W--,InZ80(R->BC.W));
-  if(!--R->BC.B.h) { R->AF.B.l=N_FLAG;R->ICount-=21;R->PC.W-=2; }
-  else             { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount-=16; }
+  WrZ80(CPU.HL.W--,InZ80(CPU.BC.W));
+  if(!--CPU.BC.B.h) { CPU.AF.B.l=N_FLAG;CPU.ICount-=21;CPU.PC.W-=2; }
+  else             { CPU.AF.B.l=Z_FLAG|N_FLAG;CPU.ICount-=16; }
   break;
 
 case OUTI:
-  --R->BC.B.h;
-  I=RdZ80(R->HL.W++);
-  OutZ80(R->BC.W,I);
-  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  --CPU.BC.B.h;
+  I=RdZ80(CPU.HL.W++);
+  OutZ80(CPU.BC.W,I);
+  CPU.AF.B.l=N_FLAG|(CPU.BC.B.h? 0:Z_FLAG)|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
   break;
 
 case OTIR:
-  --R->BC.B.h;
-  I=RdZ80(R->HL.W++);
-  OutZ80(R->BC.W,I);
-  if(R->BC.B.h)
+  --CPU.BC.B.h;
+  I=RdZ80(CPU.HL.W++);
+  OutZ80(CPU.BC.W,I);
+  if(CPU.BC.B.h)
   {
-    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
-    R->ICount-=21;
-    R->PC.W-=2;
+    CPU.AF.B.l=N_FLAG|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    CPU.ICount-=21;
+    CPU.PC.W-=2;
   }
   else
   {
-    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
-    R->ICount-=16;
+    CPU.AF.B.l=Z_FLAG|N_FLAG|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    CPU.ICount-=16;
   }
   break;
 
 case OUTD:
-  --R->BC.B.h;
-  I=RdZ80(R->HL.W--);
-  OutZ80(R->BC.W,I);
-  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  --CPU.BC.B.h;
+  I=RdZ80(CPU.HL.W--);
+  OutZ80(CPU.BC.W,I);
+  CPU.AF.B.l=N_FLAG|(CPU.BC.B.h? 0:Z_FLAG)|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
   break;
 
 case OTDR:
-  --R->BC.B.h;
-  I=RdZ80(R->HL.W--);
-  OutZ80(R->BC.W,I);
-  if(R->BC.B.h)
+  --CPU.BC.B.h;
+  I=RdZ80(CPU.HL.W--);
+  OutZ80(CPU.BC.W,I);
+  if(CPU.BC.B.h)
   {
-    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
-    R->ICount-=21;
-    R->PC.W-=2;
+    CPU.AF.B.l=N_FLAG|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    CPU.ICount-=21;
+    CPU.PC.W-=2;
   }
   else
   {
-    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
-    R->ICount-=16;
+    CPU.AF.B.l=Z_FLAG|N_FLAG|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    CPU.ICount-=16;
   }
   break;
 
 case LDI:
-  WrZ80(R->DE.W++,RdZ80(R->HL.W++));
-  --R->BC.W;
-  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  WrZ80(CPU.DE.W++,RdZ80(CPU.HL.W++));
+  --CPU.BC.W;
+  CPU.AF.B.l=(CPU.AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(CPU.BC.W? P_FLAG:0);
   break;
 
 case LDIR:
-  WrZ80(R->DE.W++,RdZ80(R->HL.W++));
-  if(--R->BC.W)
+  WrZ80(CPU.DE.W++,RdZ80(CPU.HL.W++));
+  if(--CPU.BC.W)
   {
-    R->AF.B.l=(R->AF.B.l&~(H_FLAG|P_FLAG))|N_FLAG;
-    R->ICount-=21;
-    R->PC.W-=2;
+    CPU.AF.B.l=(CPU.AF.B.l&~(H_FLAG|P_FLAG))|N_FLAG;
+    CPU.ICount-=21;
+    CPU.PC.W-=2;
   }
   else
   {
-    R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
-    R->ICount-=16;
+    CPU.AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+    CPU.ICount-=16;
   }
   break;
 
 case LDD:
-  WrZ80(R->DE.W--,RdZ80(R->HL.W--));
-  --R->BC.W;
-  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  WrZ80(CPU.DE.W--,RdZ80(CPU.HL.W--));
+  --CPU.BC.W;
+  CPU.AF.B.l=(CPU.AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(CPU.BC.W? P_FLAG:0);
   break;
 
 case LDDR:
-  WrZ80(R->DE.W--,RdZ80(R->HL.W--));
-  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
-  if(--R->BC.W)
+  WrZ80(CPU.DE.W--,RdZ80(CPU.HL.W--));
+  CPU.AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(--CPU.BC.W)
   {
-    R->AF.B.l=(R->AF.B.l&~(H_FLAG|P_FLAG))|N_FLAG;
-    R->ICount-=21;
-    R->PC.W-=2;
+    CPU.AF.B.l=(CPU.AF.B.l&~(H_FLAG|P_FLAG))|N_FLAG;
+    CPU.ICount-=21;
+    CPU.PC.W-=2;
   }
   else
   {
-    R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
-    R->ICount-=16;
+    CPU.AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+    CPU.ICount-=16;
   }
   break;
 
 case CPI:
-  I=RdZ80(R->HL.W++);
-  J.B.l=R->AF.B.h-I;
-  --R->BC.W;
-  R->AF.B.l =
-    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
-    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  I=RdZ80(CPU.HL.W++);
+  J.B.l=CPU.AF.B.h-I;
+  --CPU.BC.W;
+  CPU.AF.B.l =
+    N_FLAG|(CPU.AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((CPU.AF.B.h^I^J.B.l)&H_FLAG)|(CPU.BC.W? P_FLAG:0);
   break;
 
 case CPIR:
-  I=RdZ80(R->HL.W++);
-  J.B.l=R->AF.B.h-I;
-  if(--R->BC.W&&J.B.l) { R->ICount-=21;R->PC.W-=2; } else R->ICount-=16;
-  R->AF.B.l =
-    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
-    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  I=RdZ80(CPU.HL.W++);
+  J.B.l=CPU.AF.B.h-I;
+  if(--CPU.BC.W&&J.B.l) { CPU.ICount-=21;CPU.PC.W-=2; } else CPU.ICount-=16;
+  CPU.AF.B.l =
+    N_FLAG|(CPU.AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((CPU.AF.B.h^I^J.B.l)&H_FLAG)|(CPU.BC.W? P_FLAG:0);
   break;  
 
 case CPD:
-  I=RdZ80(R->HL.W--);
-  J.B.l=R->AF.B.h-I;
-  --R->BC.W;
-  R->AF.B.l =
-    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
-    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  I=RdZ80(CPU.HL.W--);
+  J.B.l=CPU.AF.B.h-I;
+  --CPU.BC.W;
+  CPU.AF.B.l =
+    N_FLAG|(CPU.AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((CPU.AF.B.h^I^J.B.l)&H_FLAG)|(CPU.BC.W? P_FLAG:0);
   break;
 
 case CPDR:
-  I=RdZ80(R->HL.W--);
-  J.B.l=R->AF.B.h-I;
-  if(--R->BC.W&&J.B.l) { R->ICount-=21;R->PC.W-=2; } else R->ICount-=16;
-  R->AF.B.l =
-    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
-    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  I=RdZ80(CPU.HL.W--);
+  J.B.l=CPU.AF.B.h-I;
+  if(--CPU.BC.W&&J.B.l) { CPU.ICount-=21;CPU.PC.W-=2; } else CPU.ICount-=16;
+  CPU.AF.B.l =
+    N_FLAG|(CPU.AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((CPU.AF.B.h^I^J.B.l)&H_FLAG)|(CPU.BC.W? P_FLAG:0);
   break;
diff --git a/arm9/source/cpu/z80/CodesXX.h b/arm9/source/cpu/z80/CodesXX.h
index 5712df31..6cd0d9c6 100644
--- a/arm9/source/cpu/z80/CodesXX.h
+++ b/arm9/source/cpu/z80/CodesXX.h
@@ -11,192 +11,192 @@
 /**     changes to this file.                               **/
 /*************************************************************/
 
-case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
-case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
-case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
-case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
-
-case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
-case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
-case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
-case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
-case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
-case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
-case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
-case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
-
-case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
-case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
-case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
-case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
-case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
-case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
-case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
-case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
-
-case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
-case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
-case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
-case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
-case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
-case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
-case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
-case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
-
-case ADD_B:    M_ADD(R->BC.B.h);break;
-case ADD_C:    M_ADD(R->BC.B.l);break;
-case ADD_D:    M_ADD(R->DE.B.h);break;
-case ADD_E:    M_ADD(R->DE.B.l);break;
-case ADD_H:    M_ADD(R->XX.B.h);break;
-case ADD_L:    M_ADD(R->XX.B.l);break;
-case ADD_A:    M_ADD(R->AF.B.h);break;
-case ADD_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+case JR_NZ:   if(CPU.AF.B.l&Z_FLAG) CPU.PC.W++; else { CPU.ICount-=5;M_JR; } break;
+case JR_NC:   if(CPU.AF.B.l&C_FLAG) CPU.PC.W++; else { CPU.ICount-=5;M_JR; } break;
+case JR_Z:    if(CPU.AF.B.l&Z_FLAG) { CPU.ICount-=5;M_JR; } else CPU.PC.W++; break;
+case JR_C:    if(CPU.AF.B.l&C_FLAG) { CPU.ICount-=5;M_JR; } else CPU.PC.W++; break;
+
+case JP_NZ:   if(CPU.AF.B.l&Z_FLAG) CPU.PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(CPU.AF.B.l&C_FLAG) CPU.PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(CPU.AF.B.l&P_FLAG) CPU.PC.W+=2; else { M_JP; } break;
+case JP_P:    if(CPU.AF.B.l&S_FLAG) CPU.PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(CPU.AF.B.l&Z_FLAG) { M_JP; } else CPU.PC.W+=2; break;
+case JP_C:    if(CPU.AF.B.l&C_FLAG) { M_JP; } else CPU.PC.W+=2; break;
+case JP_PE:   if(CPU.AF.B.l&P_FLAG) { M_JP; } else CPU.PC.W+=2; break;
+case JP_M:    if(CPU.AF.B.l&S_FLAG) { M_JP; } else CPU.PC.W+=2; break;
+
+case RET_NZ:  if(!(CPU.AF.B.l&Z_FLAG)) { CPU.ICount-=6;M_RET; } break;
+case RET_NC:  if(!(CPU.AF.B.l&C_FLAG)) { CPU.ICount-=6;M_RET; } break;
+case RET_PO:  if(!(CPU.AF.B.l&P_FLAG)) { CPU.ICount-=6;M_RET; } break;
+case RET_P:   if(!(CPU.AF.B.l&S_FLAG)) { CPU.ICount-=6;M_RET; } break;
+case RET_Z:   if(CPU.AF.B.l&Z_FLAG)    { CPU.ICount-=6;M_RET; } break;
+case RET_C:   if(CPU.AF.B.l&C_FLAG)    { CPU.ICount-=6;M_RET; } break;
+case RET_PE:  if(CPU.AF.B.l&P_FLAG)    { CPU.ICount-=6;M_RET; } break;
+case RET_M:   if(CPU.AF.B.l&S_FLAG)    { CPU.ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(CPU.AF.B.l&Z_FLAG) CPU.PC.W+=2; else { CPU.ICount-=7;M_CALL; } break;
+case CALL_NC: if(CPU.AF.B.l&C_FLAG) CPU.PC.W+=2; else { CPU.ICount-=7;M_CALL; } break;
+case CALL_PO: if(CPU.AF.B.l&P_FLAG) CPU.PC.W+=2; else { CPU.ICount-=7;M_CALL; } break;
+case CALL_P:  if(CPU.AF.B.l&S_FLAG) CPU.PC.W+=2; else { CPU.ICount-=7;M_CALL; } break;
+case CALL_Z:  if(CPU.AF.B.l&Z_FLAG) { CPU.ICount-=7;M_CALL; } else CPU.PC.W+=2; break;
+case CALL_C:  if(CPU.AF.B.l&C_FLAG) { CPU.ICount-=7;M_CALL; } else CPU.PC.W+=2; break;
+case CALL_PE: if(CPU.AF.B.l&P_FLAG) { CPU.ICount-=7;M_CALL; } else CPU.PC.W+=2; break;
+case CALL_M:  if(CPU.AF.B.l&S_FLAG) { CPU.ICount-=7;M_CALL; } else CPU.PC.W+=2; break;
+
+case ADD_B:    M_ADD(CPU.BC.B.h);break;
+case ADD_C:    M_ADD(CPU.BC.B.l);break;
+case ADD_D:    M_ADD(CPU.DE.B.h);break;
+case ADD_E:    M_ADD(CPU.DE.B.l);break;
+case ADD_H:    M_ADD(CPU.XX.B.h);break;
+case ADD_L:    M_ADD(CPU.XX.B.l);break;
+case ADD_A:    M_ADD(CPU.AF.B.h);break;
+case ADD_xHL:  I=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));
                M_ADD(I);break;
-case ADD_BYTE: I=OpZ80(R->PC.W++);M_ADD(I);break;
-
-case SUB_B:    M_SUB(R->BC.B.h);break;
-case SUB_C:    M_SUB(R->BC.B.l);break;
-case SUB_D:    M_SUB(R->DE.B.h);break;
-case SUB_E:    M_SUB(R->DE.B.l);break;
-case SUB_H:    M_SUB(R->XX.B.h);break;
-case SUB_L:    M_SUB(R->XX.B.l);break;
-case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
-case SUB_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+case ADD_BYTE: I=OpZ80(CPU.PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(CPU.BC.B.h);break;
+case SUB_C:    M_SUB(CPU.BC.B.l);break;
+case SUB_D:    M_SUB(CPU.DE.B.h);break;
+case SUB_E:    M_SUB(CPU.DE.B.l);break;
+case SUB_H:    M_SUB(CPU.XX.B.h);break;
+case SUB_L:    M_SUB(CPU.XX.B.l);break;
+case SUB_A:    CPU.AF.B.h=0;CPU.AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));
                M_SUB(I);break;
-case SUB_BYTE: I=OpZ80(R->PC.W++);M_SUB(I);break;
-
-case AND_B:    M_AND(R->BC.B.h);break;
-case AND_C:    M_AND(R->BC.B.l);break;
-case AND_D:    M_AND(R->DE.B.h);break;
-case AND_E:    M_AND(R->DE.B.l);break;
-case AND_H:    M_AND(R->XX.B.h);break;
-case AND_L:    M_AND(R->XX.B.l);break;
-case AND_A:    M_AND(R->AF.B.h);break;
-case AND_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+case SUB_BYTE: I=OpZ80(CPU.PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(CPU.BC.B.h);break;
+case AND_C:    M_AND(CPU.BC.B.l);break;
+case AND_D:    M_AND(CPU.DE.B.h);break;
+case AND_E:    M_AND(CPU.DE.B.l);break;
+case AND_H:    M_AND(CPU.XX.B.h);break;
+case AND_L:    M_AND(CPU.XX.B.l);break;
+case AND_A:    M_AND(CPU.AF.B.h);break;
+case AND_xHL:  I=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));
                M_AND(I);break;
-case AND_BYTE: I=OpZ80(R->PC.W++);M_AND(I);break;
-
-case OR_B:     M_OR(R->BC.B.h);break;
-case OR_C:     M_OR(R->BC.B.l);break;
-case OR_D:     M_OR(R->DE.B.h);break;
-case OR_E:     M_OR(R->DE.B.l);break;
-case OR_H:     M_OR(R->XX.B.h);break;
-case OR_L:     M_OR(R->XX.B.l);break;
-case OR_A:     M_OR(R->AF.B.h);break;
-case OR_xHL:   I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+case AND_BYTE: I=OpZ80(CPU.PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(CPU.BC.B.h);break;
+case OR_C:     M_OR(CPU.BC.B.l);break;
+case OR_D:     M_OR(CPU.DE.B.h);break;
+case OR_E:     M_OR(CPU.DE.B.l);break;
+case OR_H:     M_OR(CPU.XX.B.h);break;
+case OR_L:     M_OR(CPU.XX.B.l);break;
+case OR_A:     M_OR(CPU.AF.B.h);break;
+case OR_xHL:   I=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));
                M_OR(I);break;
-case OR_BYTE:  I=OpZ80(R->PC.W++);M_OR(I);break;
-
-case ADC_B:    M_ADC(R->BC.B.h);break;
-case ADC_C:    M_ADC(R->BC.B.l);break;
-case ADC_D:    M_ADC(R->DE.B.h);break;
-case ADC_E:    M_ADC(R->DE.B.l);break;
-case ADC_H:    M_ADC(R->XX.B.h);break;
-case ADC_L:    M_ADC(R->XX.B.l);break;
-case ADC_A:    M_ADC(R->AF.B.h);break;
-case ADC_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+case OR_BYTE:  I=OpZ80(CPU.PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(CPU.BC.B.h);break;
+case ADC_C:    M_ADC(CPU.BC.B.l);break;
+case ADC_D:    M_ADC(CPU.DE.B.h);break;
+case ADC_E:    M_ADC(CPU.DE.B.l);break;
+case ADC_H:    M_ADC(CPU.XX.B.h);break;
+case ADC_L:    M_ADC(CPU.XX.B.l);break;
+case ADC_A:    M_ADC(CPU.AF.B.h);break;
+case ADC_xHL:  I=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));
                M_ADC(I);break;
-case ADC_BYTE: I=OpZ80(R->PC.W++);M_ADC(I);break;
-
-case SBC_B:    M_SBC(R->BC.B.h);break;
-case SBC_C:    M_SBC(R->BC.B.l);break;
-case SBC_D:    M_SBC(R->DE.B.h);break;
-case SBC_E:    M_SBC(R->DE.B.l);break;
-case SBC_H:    M_SBC(R->XX.B.h);break;
-case SBC_L:    M_SBC(R->XX.B.l);break;
-case SBC_A:    M_SBC(R->AF.B.h);break;
-case SBC_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+case ADC_BYTE: I=OpZ80(CPU.PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(CPU.BC.B.h);break;
+case SBC_C:    M_SBC(CPU.BC.B.l);break;
+case SBC_D:    M_SBC(CPU.DE.B.h);break;
+case SBC_E:    M_SBC(CPU.DE.B.l);break;
+case SBC_H:    M_SBC(CPU.XX.B.h);break;
+case SBC_L:    M_SBC(CPU.XX.B.l);break;
+case SBC_A:    M_SBC(CPU.AF.B.h);break;
+case SBC_xHL:  I=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));
                M_SBC(I);break;
-case SBC_BYTE: I=OpZ80(R->PC.W++);M_SBC(I);break;
-
-case XOR_B:    M_XOR(R->BC.B.h);break;
-case XOR_C:    M_XOR(R->BC.B.l);break;
-case XOR_D:    M_XOR(R->DE.B.h);break;
-case XOR_E:    M_XOR(R->DE.B.l);break;
-case XOR_H:    M_XOR(R->XX.B.h);break;
-case XOR_L:    M_XOR(R->XX.B.l);break;
-case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
-case XOR_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+case SBC_BYTE: I=OpZ80(CPU.PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(CPU.BC.B.h);break;
+case XOR_C:    M_XOR(CPU.BC.B.l);break;
+case XOR_D:    M_XOR(CPU.DE.B.h);break;
+case XOR_E:    M_XOR(CPU.DE.B.l);break;
+case XOR_H:    M_XOR(CPU.XX.B.h);break;
+case XOR_L:    M_XOR(CPU.XX.B.l);break;
+case XOR_A:    CPU.AF.B.h=0;CPU.AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));
                M_XOR(I);break;
-case XOR_BYTE: I=OpZ80(R->PC.W++);M_XOR(I);break;
-
-case CP_B:     M_CP(R->BC.B.h);break;
-case CP_C:     M_CP(R->BC.B.l);break;
-case CP_D:     M_CP(R->DE.B.h);break;
-case CP_E:     M_CP(R->DE.B.l);break;
-case CP_H:     M_CP(R->XX.B.h);break;
-case CP_L:     M_CP(R->XX.B.l);break;
-case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
-case CP_xHL:   I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+case XOR_BYTE: I=OpZ80(CPU.PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(CPU.BC.B.h);break;
+case CP_C:     M_CP(CPU.BC.B.l);break;
+case CP_D:     M_CP(CPU.DE.B.h);break;
+case CP_E:     M_CP(CPU.DE.B.l);break;
+case CP_H:     M_CP(CPU.XX.B.h);break;
+case CP_L:     M_CP(CPU.XX.B.l);break;
+case CP_A:     CPU.AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));
                M_CP(I);break;
-case CP_BYTE:  I=OpZ80(R->PC.W++);M_CP(I);break;
+case CP_BYTE:  I=OpZ80(CPU.PC.W++);M_CP(I);break;
                
 case LD_BC_WORD: M_LDWORD(BC);break;
 case LD_DE_WORD: M_LDWORD(DE);break;
 case LD_HL_WORD: M_LDWORD(XX);break;
 case LD_SP_WORD: M_LDWORD(SP);break;
 
-case LD_PC_HL: R->PC.W=R->XX.W;JumpZ80(R->PC.W);break;
-case LD_SP_HL: R->SP.W=R->XX.W;break;
-case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
-case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+case LD_PC_HL: CPU.PC.W=CPU.XX.W;JumpZ80(CPU.PC.W);break;
+case LD_SP_HL: CPU.SP.W=CPU.XX.W;break;
+case LD_A_xBC: CPU.AF.B.h=RdZ80(CPU.BC.W);break;
+case LD_A_xDE: CPU.AF.B.h=RdZ80(CPU.DE.W);break;
 
 case ADD_HL_BC:  M_ADDW(XX,BC);break;
 case ADD_HL_DE:  M_ADDW(XX,DE);break;
 case ADD_HL_HL:  M_ADDW(XX,XX);break;
 case ADD_HL_SP:  M_ADDW(XX,SP);break;
 
-case DEC_BC:   R->BC.W--;break;
-case DEC_DE:   R->DE.W--;break;
-case DEC_HL:   R->XX.W--;break;
-case DEC_SP:   R->SP.W--;break;
-
-case INC_BC:   R->BC.W++;break;
-case INC_DE:   R->DE.W++;break;
-case INC_HL:   R->XX.W++;break;
-case INC_SP:   R->SP.W++;break;
-
-case DEC_B:    M_DEC(R->BC.B.h);break;
-case DEC_C:    M_DEC(R->BC.B.l);break;
-case DEC_D:    M_DEC(R->DE.B.h);break;
-case DEC_E:    M_DEC(R->DE.B.l);break;
-case DEC_H:    M_DEC(R->XX.B.h);break;
-case DEC_L:    M_DEC(R->XX.B.l);break;
-case DEC_A:    M_DEC(R->AF.B.h);break;
-case DEC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_DEC(I);
-               WrZ80(R->XX.W+(offset)OpZ80(R->PC.W++),I);
+case DEC_BC:   CPU.BC.W--;break;
+case DEC_DE:   CPU.DE.W--;break;
+case DEC_HL:   CPU.XX.W--;break;
+case DEC_SP:   CPU.SP.W--;break;
+
+case INC_BC:   CPU.BC.W++;break;
+case INC_DE:   CPU.DE.W++;break;
+case INC_HL:   CPU.XX.W++;break;
+case INC_SP:   CPU.SP.W++;break;
+
+case DEC_B:    M_DEC(CPU.BC.B.h);break;
+case DEC_C:    M_DEC(CPU.BC.B.l);break;
+case DEC_D:    M_DEC(CPU.DE.B.h);break;
+case DEC_E:    M_DEC(CPU.DE.B.l);break;
+case DEC_H:    M_DEC(CPU.XX.B.h);break;
+case DEC_L:    M_DEC(CPU.XX.B.l);break;
+case DEC_A:    M_DEC(CPU.AF.B.h);break;
+case DEC_xHL:  I=RdZ80(CPU.XX.W+(offset)RdZ80(CPU.PC.W));M_DEC(I);
+               WrZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++),I);
                break;
 
-case INC_B:    M_INC(R->BC.B.h);break;
-case INC_C:    M_INC(R->BC.B.l);break;
-case INC_D:    M_INC(R->DE.B.h);break;
-case INC_E:    M_INC(R->DE.B.l);break;
-case INC_H:    M_INC(R->XX.B.h);break;
-case INC_L:    M_INC(R->XX.B.l);break;
-case INC_A:    M_INC(R->AF.B.h);break;
-case INC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_INC(I);
-               WrZ80(R->XX.W+(offset)OpZ80(R->PC.W++),I);
+case INC_B:    M_INC(CPU.BC.B.h);break;
+case INC_C:    M_INC(CPU.BC.B.l);break;
+case INC_D:    M_INC(CPU.DE.B.h);break;
+case INC_E:    M_INC(CPU.DE.B.l);break;
+case INC_H:    M_INC(CPU.XX.B.h);break;
+case INC_L:    M_INC(CPU.XX.B.l);break;
+case INC_A:    M_INC(CPU.AF.B.h);break;
+case INC_xHL:  I=RdZ80(CPU.XX.W+(offset)RdZ80(CPU.PC.W));M_INC(I);
+               WrZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++),I);
                break;
 
 case RLCA:
-  I=(R->AF.B.h&0x80? C_FLAG:0);
-  R->AF.B.h=(R->AF.B.h<<1)|I;
-  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  I=(CPU.AF.B.h&0x80? C_FLAG:0);
+  CPU.AF.B.h=(CPU.AF.B.h<<1)|I;
+  CPU.AF.B.l=(CPU.AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
   break;
 case RLA:
-  I=(R->AF.B.h&0x80? C_FLAG:0);
-  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
-  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  I=(CPU.AF.B.h&0x80? C_FLAG:0);
+  CPU.AF.B.h=(CPU.AF.B.h<<1)|(CPU.AF.B.l&C_FLAG);
+  CPU.AF.B.l=(CPU.AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
   break;
 case RRCA:
-  I=R->AF.B.h&0x01;
-  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
-  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  I=CPU.AF.B.h&0x01;
+  CPU.AF.B.h=(CPU.AF.B.h>>1)|(I? 0x80:0);
+  CPU.AF.B.l=(CPU.AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
   break;
 case RRA:
-  I=R->AF.B.h&0x01;
-  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
-  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  I=CPU.AF.B.h&0x01;
+  CPU.AF.B.h=(CPU.AF.B.h>>1)|(CPU.AF.B.l&C_FLAG? 0x80:0);
+  CPU.AF.B.l=(CPU.AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
   break;
 
 case RST00:    M_RST(0x0000);break;
@@ -218,179 +218,179 @@ case POP_DE:   M_POP(DE);break;
 case POP_HL:   M_POP(XX);break;
 case POP_AF:   M_POP(AF);break;
 
-case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case DJNZ: if(--CPU.BC.B.h) { CPU.ICount-=5;M_JR; } else CPU.PC.W++;break;
 case JP:   M_JP;break;
 case JR:   M_JR;break;
 case CALL: M_CALL;break;
 case RET:  M_RET;break;
 case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
-case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case CPL:  CPU.AF.B.h=~CPU.AF.B.h;S(N_FLAG|H_FLAG);break;
 case NOP:  break;
-case OUTA: I=OpZ80(R->PC.W++);OutZ80(I|(R->AF.W&0xFF00),R->AF.B.h);break;
-case INA:  I=OpZ80(R->PC.W++);R->AF.B.h=InZ80(I|(R->AF.W&0xFF00));break;
+case OUTA: I=OpZ80(CPU.PC.W++);OutZ80(I|(CPU.AF.W&0xFF00),CPU.AF.B.h);break;
+case INA:  I=OpZ80(CPU.PC.W++);CPU.AF.B.h=InZ80(I|(CPU.AF.W&0xFF00));break;
 
 case HALT:
-  R->PC.W--;
-  R->IFF|=IFF_HALT;
-  R->IBackup=0;
-  R->ICount=0;
+  CPU.PC.W--;
+  CPU.IFF|=IFF_HALT;
+  CPU.IBackup=0;
+  CPU.ICount=0;
   break;
 
 case DI:
-  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
-  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  if(CPU.IFF&IFF_EI) CPU.ICount+=CPU.IBackup-1;
+  CPU.IFF&=~(IFF_1|IFF_2|IFF_EI);
   break;
 
 case EI:
-  if(!(R->IFF&(IFF_1|IFF_EI)))
+  if(!(CPU.IFF&(IFF_1|IFF_EI)))
   {
-    R->IFF|=IFF_2|IFF_EI;
-    R->IBackup=R->ICount;
-    R->ICount=1;
+    CPU.IFF|=IFF_2|IFF_EI;
+    CPU.IBackup=CPU.ICount;
+    CPU.ICount=1;
   }
   break;
 
 case CCF:
-  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
-  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  CPU.AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  CPU.AF.B.l|=CPU.AF.B.l&C_FLAG? 0:H_FLAG;
   break;
 
 case EXX:
-  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
-  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
-  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  J.W=CPU.BC.W;CPU.BC.W=CPU.BC1.W;CPU.BC1.W=J.W;
+  J.W=CPU.DE.W;CPU.DE.W=CPU.DE1.W;CPU.DE1.W=J.W;
+  J.W=CPU.HL.W;CPU.HL.W=CPU.HL1.W;CPU.HL1.W=J.W;
   break;
 
-case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
-case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+case EX_DE_HL: J.W=CPU.DE.W;CPU.DE.W=CPU.HL.W;CPU.HL.W=J.W;break;
+case EX_AF_AF: J.W=CPU.AF.W;CPU.AF.W=CPU.AF1.W;CPU.AF1.W=J.W;break;  
   
-case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
-case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
-case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
-case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
-case LD_H_B:   R->XX.B.h=R->BC.B.h;break;
-case LD_L_B:   R->XX.B.l=R->BC.B.h;break;
-case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
-case LD_xHL_B: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-               WrZ80(J.W,R->BC.B.h);break;
-
-case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
-case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
-case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
-case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
-case LD_H_C:   R->XX.B.h=R->BC.B.l;break;
-case LD_L_C:   R->XX.B.l=R->BC.B.l;break;
-case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
-case LD_xHL_C: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-               WrZ80(J.W,R->BC.B.l);break;
-
-case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
-case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
-case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
-case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
-case LD_H_D:   R->XX.B.h=R->DE.B.h;break;
-case LD_L_D:   R->XX.B.l=R->DE.B.h;break;
-case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
-case LD_xHL_D: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-               WrZ80(J.W,R->DE.B.h);break;
-
-case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
-case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
-case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
-case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
-case LD_H_E:   R->XX.B.h=R->DE.B.l;break;
-case LD_L_E:   R->XX.B.l=R->DE.B.l;break;
-case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
-case LD_xHL_E: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-               WrZ80(J.W,R->DE.B.l);break;
-
-case LD_B_H:   R->BC.B.h=R->XX.B.h;break;
-case LD_C_H:   R->BC.B.l=R->XX.B.h;break;
-case LD_D_H:   R->DE.B.h=R->XX.B.h;break;
-case LD_E_H:   R->DE.B.l=R->XX.B.h;break;
-case LD_H_H:   R->XX.B.h=R->XX.B.h;break;
-case LD_L_H:   R->XX.B.l=R->XX.B.h;break;
-case LD_A_H:   R->AF.B.h=R->XX.B.h;break;
-case LD_xHL_H: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-               WrZ80(J.W,R->HL.B.h);break;
-
-case LD_B_L:   R->BC.B.h=R->XX.B.l;break;
-case LD_C_L:   R->BC.B.l=R->XX.B.l;break;
-case LD_D_L:   R->DE.B.h=R->XX.B.l;break;
-case LD_E_L:   R->DE.B.l=R->XX.B.l;break;
-case LD_H_L:   R->XX.B.h=R->XX.B.l;break;
-case LD_L_L:   R->XX.B.l=R->XX.B.l;break;
-case LD_A_L:   R->AF.B.h=R->XX.B.l;break;
-case LD_xHL_L: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-               WrZ80(J.W,R->HL.B.l);break;
-
-case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
-case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
-case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
-case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
-case LD_H_A:   R->XX.B.h=R->AF.B.h;break;
-case LD_L_A:   R->XX.B.l=R->AF.B.h;break;
-case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
-case LD_xHL_A: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-               WrZ80(J.W,R->AF.B.h);break;
-
-case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
-case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
-
-case LD_B_xHL:    R->BC.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
-case LD_C_xHL:    R->BC.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
-case LD_D_xHL:    R->DE.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
-case LD_E_xHL:    R->DE.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
-case LD_H_xHL:    R->HL.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
-case LD_L_xHL:    R->HL.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
-case LD_A_xHL:    R->AF.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
-
-case LD_B_BYTE:   R->BC.B.h=OpZ80(R->PC.W++);break;
-case LD_C_BYTE:   R->BC.B.l=OpZ80(R->PC.W++);break;
-case LD_D_BYTE:   R->DE.B.h=OpZ80(R->PC.W++);break;
-case LD_E_BYTE:   R->DE.B.l=OpZ80(R->PC.W++);break;
-case LD_H_BYTE:   R->XX.B.h=OpZ80(R->PC.W++);break;
-case LD_L_BYTE:   R->XX.B.l=OpZ80(R->PC.W++);break;
-case LD_A_BYTE:   R->AF.B.h=OpZ80(R->PC.W++);break;
-case LD_xHL_BYTE: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-                  WrZ80(J.W,OpZ80(R->PC.W++));break;
+case LD_B_B:   CPU.BC.B.h=CPU.BC.B.h;break;
+case LD_C_B:   CPU.BC.B.l=CPU.BC.B.h;break;
+case LD_D_B:   CPU.DE.B.h=CPU.BC.B.h;break;
+case LD_E_B:   CPU.DE.B.l=CPU.BC.B.h;break;
+case LD_H_B:   CPU.XX.B.h=CPU.BC.B.h;break;
+case LD_L_B:   CPU.XX.B.l=CPU.BC.B.h;break;
+case LD_A_B:   CPU.AF.B.h=CPU.BC.B.h;break;
+case LD_xHL_B: J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+               WrZ80(J.W,CPU.BC.B.h);break;
+
+case LD_B_C:   CPU.BC.B.h=CPU.BC.B.l;break;
+case LD_C_C:   CPU.BC.B.l=CPU.BC.B.l;break;
+case LD_D_C:   CPU.DE.B.h=CPU.BC.B.l;break;
+case LD_E_C:   CPU.DE.B.l=CPU.BC.B.l;break;
+case LD_H_C:   CPU.XX.B.h=CPU.BC.B.l;break;
+case LD_L_C:   CPU.XX.B.l=CPU.BC.B.l;break;
+case LD_A_C:   CPU.AF.B.h=CPU.BC.B.l;break;
+case LD_xHL_C: J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+               WrZ80(J.W,CPU.BC.B.l);break;
+
+case LD_B_D:   CPU.BC.B.h=CPU.DE.B.h;break;
+case LD_C_D:   CPU.BC.B.l=CPU.DE.B.h;break;
+case LD_D_D:   CPU.DE.B.h=CPU.DE.B.h;break;
+case LD_E_D:   CPU.DE.B.l=CPU.DE.B.h;break;
+case LD_H_D:   CPU.XX.B.h=CPU.DE.B.h;break;
+case LD_L_D:   CPU.XX.B.l=CPU.DE.B.h;break;
+case LD_A_D:   CPU.AF.B.h=CPU.DE.B.h;break;
+case LD_xHL_D: J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+               WrZ80(J.W,CPU.DE.B.h);break;
+
+case LD_B_E:   CPU.BC.B.h=CPU.DE.B.l;break;
+case LD_C_E:   CPU.BC.B.l=CPU.DE.B.l;break;
+case LD_D_E:   CPU.DE.B.h=CPU.DE.B.l;break;
+case LD_E_E:   CPU.DE.B.l=CPU.DE.B.l;break;
+case LD_H_E:   CPU.XX.B.h=CPU.DE.B.l;break;
+case LD_L_E:   CPU.XX.B.l=CPU.DE.B.l;break;
+case LD_A_E:   CPU.AF.B.h=CPU.DE.B.l;break;
+case LD_xHL_E: J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+               WrZ80(J.W,CPU.DE.B.l);break;
+
+case LD_B_H:   CPU.BC.B.h=CPU.XX.B.h;break;
+case LD_C_H:   CPU.BC.B.l=CPU.XX.B.h;break;
+case LD_D_H:   CPU.DE.B.h=CPU.XX.B.h;break;
+case LD_E_H:   CPU.DE.B.l=CPU.XX.B.h;break;
+case LD_H_H:   CPU.XX.B.h=CPU.XX.B.h;break;
+case LD_L_H:   CPU.XX.B.l=CPU.XX.B.h;break;
+case LD_A_H:   CPU.AF.B.h=CPU.XX.B.h;break;
+case LD_xHL_H: J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+               WrZ80(J.W,CPU.HL.B.h);break;
+
+case LD_B_L:   CPU.BC.B.h=CPU.XX.B.l;break;
+case LD_C_L:   CPU.BC.B.l=CPU.XX.B.l;break;
+case LD_D_L:   CPU.DE.B.h=CPU.XX.B.l;break;
+case LD_E_L:   CPU.DE.B.l=CPU.XX.B.l;break;
+case LD_H_L:   CPU.XX.B.h=CPU.XX.B.l;break;
+case LD_L_L:   CPU.XX.B.l=CPU.XX.B.l;break;
+case LD_A_L:   CPU.AF.B.h=CPU.XX.B.l;break;
+case LD_xHL_L: J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+               WrZ80(J.W,CPU.HL.B.l);break;
+
+case LD_B_A:   CPU.BC.B.h=CPU.AF.B.h;break;
+case LD_C_A:   CPU.BC.B.l=CPU.AF.B.h;break;
+case LD_D_A:   CPU.DE.B.h=CPU.AF.B.h;break;
+case LD_E_A:   CPU.DE.B.l=CPU.AF.B.h;break;
+case LD_H_A:   CPU.XX.B.h=CPU.AF.B.h;break;
+case LD_L_A:   CPU.XX.B.l=CPU.AF.B.h;break;
+case LD_A_A:   CPU.AF.B.h=CPU.AF.B.h;break;
+case LD_xHL_A: J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+               WrZ80(J.W,CPU.AF.B.h);break;
+
+case LD_xBC_A: WrZ80(CPU.BC.W,CPU.AF.B.h);break;
+case LD_xDE_A: WrZ80(CPU.DE.W,CPU.AF.B.h);break;
+
+case LD_B_xHL:    CPU.BC.B.h=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));break;
+case LD_C_xHL:    CPU.BC.B.l=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));break;
+case LD_D_xHL:    CPU.DE.B.h=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));break;
+case LD_E_xHL:    CPU.DE.B.l=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));break;
+case LD_H_xHL:    CPU.HL.B.h=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));break;
+case LD_L_xHL:    CPU.HL.B.l=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));break;
+case LD_A_xHL:    CPU.AF.B.h=RdZ80(CPU.XX.W+(offset)OpZ80(CPU.PC.W++));break;
+
+case LD_B_BYTE:   CPU.BC.B.h=OpZ80(CPU.PC.W++);break;
+case LD_C_BYTE:   CPU.BC.B.l=OpZ80(CPU.PC.W++);break;
+case LD_D_BYTE:   CPU.DE.B.h=OpZ80(CPU.PC.W++);break;
+case LD_E_BYTE:   CPU.DE.B.l=OpZ80(CPU.PC.W++);break;
+case LD_H_BYTE:   CPU.XX.B.h=OpZ80(CPU.PC.W++);break;
+case LD_L_BYTE:   CPU.XX.B.l=OpZ80(CPU.PC.W++);break;
+case LD_A_BYTE:   CPU.AF.B.h=OpZ80(CPU.PC.W++);break;
+case LD_xHL_BYTE: J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+                  WrZ80(J.W,OpZ80(CPU.PC.W++));break;
 
 case LD_xWORD_HL:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  WrZ80(J.W++,R->XX.B.l);
-  WrZ80(J.W,R->XX.B.h);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  WrZ80(J.W++,CPU.XX.B.l);
+  WrZ80(J.W,CPU.XX.B.h);
   break;
 
 case LD_HL_xWORD:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  R->XX.B.l=RdZ80(J.W++);
-  R->XX.B.h=RdZ80(J.W);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  CPU.XX.B.l=RdZ80(J.W++);
+  CPU.XX.B.h=RdZ80(J.W);
   break;
 
 case LD_A_xWORD:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  R->AF.B.h=RdZ80(J.W);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  CPU.AF.B.h=RdZ80(J.W);
   break;
 
 case LD_xWORD_A:
-  J.B.l=OpZ80(R->PC.W++);
-  J.B.h=OpZ80(R->PC.W++);
-  WrZ80(J.W,R->AF.B.h);
+  J.B.l=OpZ80(CPU.PC.W++);
+  J.B.h=OpZ80(CPU.PC.W++);
+  WrZ80(J.W,CPU.AF.B.h);
   break;
 
 case EX_HL_xSP:
-  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->XX.B.l);
-  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->XX.B.h);
-  R->XX.W=J.W;
+  J.B.l=RdZ80(CPU.SP.W);WrZ80(CPU.SP.W++,CPU.XX.B.l);
+  J.B.h=RdZ80(CPU.SP.W);WrZ80(CPU.SP.W--,CPU.XX.B.h);
+  CPU.XX.W=J.W;
   break;
 
 case DAA:
-  J.W=R->AF.B.h;
-  if(R->AF.B.l&C_FLAG) J.W|=256;
-  if(R->AF.B.l&H_FLAG) J.W|=512;
-  if(R->AF.B.l&N_FLAG) J.W|=1024;
-  R->AF.W=DAATable[J.W];
+  J.W=CPU.AF.B.h;
+  if(CPU.AF.B.l&C_FLAG) J.W|=256;
+  if(CPU.AF.B.l&H_FLAG) J.W|=512;
+  if(CPU.AF.B.l&N_FLAG) J.W|=1024;
+  CPU.AF.W=DAATable[J.W];
   break;
diff --git a/arm9/source/cpu/z80/Z80.c b/arm9/source/cpu/z80/Z80.c
index 9f494b31..dd8328e4 100644
--- a/arm9/source/cpu/z80/Z80.c
+++ b/arm9/source/cpu/z80/Z80.c
@@ -17,6 +17,8 @@
 #include "Tables.h"
 #include <stdio.h>
 
+extern Z80 CPU;
+
 /** INLINE ***************************************************/
 /** C99 standard has "inline", but older compilers used     **/
 /** __inline for the same purpose.                          **/
@@ -35,181 +37,180 @@
 extern byte pColecoMem[];
 INLINE byte OpZ80(word A) { return pColecoMem[A]; }
 
-#define S(Fl)        R->AF.B.l|=Fl
-#define R(Fl)        R->AF.B.l&=~(Fl)
-#define FLAGS(Rg,Fl) R->AF.B.l=Fl|ZSTable[Rg]
-#define INCR(N)      R->R=((R->R+(N))&0x7F)|(R->R&0x80)
+// -----------------------------------------------
+// These two functions are for the CZ80 core...
+// -----------------------------------------------
+extern u8 bMagicMegaCart, romBankMask;
+extern void cpu_writemem16 (u8 value,u16 address);
+extern void BankSwitch(u8 bank);
+INLINE void WrZ80(register word address,register byte Value)
+{
+    cpu_writemem16(Value, address);
+}
+
+INLINE byte RdZ80(register word address)
+{
+  if (bMagicMegaCart && (address >= 0xFFC0)) // Handle Megacart Hot Spots
+  {
+      BankSwitch(address & romBankMask);
+  }    
+  return (pColecoMem[address]);
+}
+
+#define S(Fl)        CPU.AF.B.l|=Fl
+#define R(Fl)        CPU.AF.B.l&=~(Fl)
+#define FLAGS(Rg,Fl) CPU.AF.B.l=Fl|ZSTable[Rg]
+#define INCR(N)      CPU.R=((CPU.R+(N))&0x7F)|(CPU.R&0x80)
 
 #define M_RLC(Rg)      \
-  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|R->AF.B.l;R->AF.B.l|=PZSTable[Rg]
+  CPU.AF.B.l=Rg>>7;Rg=(Rg<<1)|CPU.AF.B.l;CPU.AF.B.l|=PZSTable[Rg]
 #define M_RRC(Rg)      \
-  R->AF.B.l=Rg&0x01;Rg=(Rg>>1)|(R->AF.B.l<<7);R->AF.B.l|=PZSTable[Rg]
+  CPU.AF.B.l=Rg&0x01;Rg=(Rg>>1)|(CPU.AF.B.l<<7);CPU.AF.B.l|=PZSTable[Rg]
 #define M_RL(Rg)       \
   if(Rg&0x80)          \
   {                    \
-    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
-    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+    Rg=(Rg<<1)|(CPU.AF.B.l&C_FLAG); \
+    CPU.AF.B.l=PZSTable[Rg]|C_FLAG; \
   }                    \
   else                 \
   {                    \
-    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
-    R->AF.B.l=PZSTable[Rg];        \
+    Rg=(Rg<<1)|(CPU.AF.B.l&C_FLAG); \
+    CPU.AF.B.l=PZSTable[Rg];        \
   }
 #define M_RR(Rg)       \
   if(Rg&0x01)          \
   {                    \
-    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
-    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+    Rg=(Rg>>1)|(CPU.AF.B.l<<7);     \
+    CPU.AF.B.l=PZSTable[Rg]|C_FLAG; \
   }                    \
   else                 \
   {                    \
-    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
-    R->AF.B.l=PZSTable[Rg];        \
+    Rg=(Rg>>1)|(CPU.AF.B.l<<7);     \
+    CPU.AF.B.l=PZSTable[Rg];        \
   }
   
 #define M_SLA(Rg)      \
-  R->AF.B.l=Rg>>7;Rg<<=1;R->AF.B.l|=PZSTable[Rg]
+  CPU.AF.B.l=Rg>>7;Rg<<=1;CPU.AF.B.l|=PZSTable[Rg]
 #define M_SRA(Rg)      \
-  R->AF.B.l=Rg&C_FLAG;Rg=(Rg>>1)|(Rg&0x80);R->AF.B.l|=PZSTable[Rg]
+  CPU.AF.B.l=Rg&C_FLAG;Rg=(Rg>>1)|(Rg&0x80);CPU.AF.B.l|=PZSTable[Rg]
 
 #define M_SLL(Rg)      \
-  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|0x01;R->AF.B.l|=PZSTable[Rg]
+  CPU.AF.B.l=Rg>>7;Rg=(Rg<<1)|0x01;CPU.AF.B.l|=PZSTable[Rg]
 #define M_SRL(Rg)      \
-  R->AF.B.l=Rg&0x01;Rg>>=1;R->AF.B.l|=PZSTable[Rg]
+  CPU.AF.B.l=Rg&0x01;Rg>>=1;CPU.AF.B.l|=PZSTable[Rg]
 
 #define M_BIT(Bit,Rg)  \
-  R->AF.B.l=(R->AF.B.l&C_FLAG)|H_FLAG|PZSTable[Rg&(1<<Bit)]
+  CPU.AF.B.l=(CPU.AF.B.l&C_FLAG)|H_FLAG|PZSTable[Rg&(1<<Bit)]
 
 #define M_SET(Bit,Rg) Rg|=1<<Bit
 #define M_RES(Bit,Rg) Rg&=~(1<<Bit)
 
 #define M_POP(Rg)      \
-  R->Rg.B.l=OpZ80(R->SP.W++);R->Rg.B.h=OpZ80(R->SP.W++)
+  CPU.Rg.B.l=OpZ80(CPU.SP.W++);CPU.Rg.B.h=OpZ80(CPU.SP.W++)
 #define M_PUSH(Rg)     \
-  WrZ80(--R->SP.W,R->Rg.B.h);WrZ80(--R->SP.W,R->Rg.B.l)
+  WrZ80(--CPU.SP.W,CPU.Rg.B.h);WrZ80(--CPU.SP.W,CPU.Rg.B.l)
 
 #define M_CALL         \
-  J.B.l=OpZ80(R->PC.W++);J.B.h=OpZ80(R->PC.W++);         \
-  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l); \
-  R->PC.W=J.W; \
+  J.B.l=OpZ80(CPU.PC.W++);J.B.h=OpZ80(CPU.PC.W++);         \
+  WrZ80(--CPU.SP.W,CPU.PC.B.h);WrZ80(--CPU.SP.W,CPU.PC.B.l); \
+  CPU.PC.W=J.W; \
   JumpZ80(J.W)
 
-#define M_JP  J.B.l=OpZ80(R->PC.W++);J.B.h=OpZ80(R->PC.W);R->PC.W=J.W;JumpZ80(J.W)
-#define M_JR  R->PC.W+=(offset)OpZ80(R->PC.W)+1;JumpZ80(R->PC.W)
-#define M_RET R->PC.B.l=OpZ80(R->SP.W++);R->PC.B.h=OpZ80(R->SP.W++);JumpZ80(R->PC.W)
+#define M_JP  J.B.l=OpZ80(CPU.PC.W++);J.B.h=OpZ80(CPU.PC.W);CPU.PC.W=J.W;JumpZ80(J.W)
+#define M_JR  CPU.PC.W+=(offset)OpZ80(CPU.PC.W)+1;JumpZ80(CPU.PC.W)
+#define M_RET CPU.PC.B.l=OpZ80(CPU.SP.W++);CPU.PC.B.h=OpZ80(CPU.SP.W++);JumpZ80(CPU.PC.W)
 
 #define M_RST(Ad)      \
-  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l);R->PC.W=Ad;JumpZ80(Ad)
+  WrZ80(--CPU.SP.W,CPU.PC.B.h);WrZ80(--CPU.SP.W,CPU.PC.B.l);CPU.PC.W=Ad;JumpZ80(Ad)
 
 #define M_LDWORD(Rg)   \
-  R->Rg.B.l=OpZ80(R->PC.W++);R->Rg.B.h=OpZ80(R->PC.W++)
+  CPU.Rg.B.l=OpZ80(CPU.PC.W++);CPU.Rg.B.h=OpZ80(CPU.PC.W++)
 
 #define M_ADD(Rg)      \
-  J.W=R->AF.B.h+Rg;    \
-  R->AF.B.l=           \
-    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+  J.W=CPU.AF.B.h+Rg;    \
+  CPU.AF.B.l=           \
+    (~(CPU.AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
     J.B.h|ZSTable[J.B.l]|                        \
-    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);               \
-  R->AF.B.h=J.B.l       
+    ((CPU.AF.B.h^Rg^J.B.l)&H_FLAG);               \
+  CPU.AF.B.h=J.B.l       
 
 #define M_SUB(Rg)      \
-  J.W=R->AF.B.h-Rg;    \
-  R->AF.B.l=           \
-    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+  J.W=CPU.AF.B.h-Rg;    \
+  CPU.AF.B.l=           \
+    ((CPU.AF.B.h^Rg)&(CPU.AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
     N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
-    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);                     \
-  R->AF.B.h=J.B.l
+    ((CPU.AF.B.h^Rg^J.B.l)&H_FLAG);                     \
+  CPU.AF.B.h=J.B.l
 
 #define M_ADC(Rg)      \
-  J.W=R->AF.B.h+Rg+(R->AF.B.l&C_FLAG); \
-  R->AF.B.l=                           \
-    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+  J.W=CPU.AF.B.h+Rg+(CPU.AF.B.l&C_FLAG); \
+  CPU.AF.B.l=                           \
+    (~(CPU.AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
     J.B.h|ZSTable[J.B.l]|              \
-    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
-  R->AF.B.h=J.B.l
+    ((CPU.AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  CPU.AF.B.h=J.B.l
 
 #define M_SBC(Rg)      \
-  J.W=R->AF.B.h-Rg-(R->AF.B.l&C_FLAG); \
-  R->AF.B.l=                           \
-    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+  J.W=CPU.AF.B.h-Rg-(CPU.AF.B.l&C_FLAG); \
+  CPU.AF.B.l=                           \
+    ((CPU.AF.B.h^Rg)&(CPU.AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
     N_FLAG|-J.B.h|ZSTable[J.B.l]|      \
-    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
-  R->AF.B.h=J.B.l
+    ((CPU.AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  CPU.AF.B.h=J.B.l
 
 #define M_CP(Rg)       \
-  J.W=R->AF.B.h-Rg;    \
-  R->AF.B.l=           \
-    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+  J.W=CPU.AF.B.h-Rg;    \
+  CPU.AF.B.l=           \
+    ((CPU.AF.B.h^Rg)&(CPU.AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
     N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
-    ((R->AF.B.h^Rg^J.B.l)&H_FLAG)
+    ((CPU.AF.B.h^Rg^J.B.l)&H_FLAG)
 
-#define M_AND(Rg) R->AF.B.h&=Rg;R->AF.B.l=H_FLAG|PZSTable[R->AF.B.h]
-#define M_OR(Rg)  R->AF.B.h|=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
-#define M_XOR(Rg) R->AF.B.h^=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+#define M_AND(Rg) CPU.AF.B.h&=Rg;CPU.AF.B.l=H_FLAG|PZSTable[CPU.AF.B.h]
+#define M_OR(Rg)  CPU.AF.B.h|=Rg;CPU.AF.B.l=PZSTable[CPU.AF.B.h]
+#define M_XOR(Rg) CPU.AF.B.h^=Rg;CPU.AF.B.l=PZSTable[CPU.AF.B.h]
 
 #define M_IN(Rg)        \
-  Rg=InZ80(R->BC.W);  \
-  R->AF.B.l=PZSTable[Rg]|(R->AF.B.l&C_FLAG)
+  Rg=InZ80(CPU.BC.W);  \
+  CPU.AF.B.l=PZSTable[Rg]|(CPU.AF.B.l&C_FLAG)
 
 #define M_INC(Rg)       \
   Rg++;                 \
-  R->AF.B.l=            \
-    (R->AF.B.l&C_FLAG)|ZSTable[Rg]|           \
+  CPU.AF.B.l=            \
+    (CPU.AF.B.l&C_FLAG)|ZSTable[Rg]|           \
     (Rg==0x80? V_FLAG:0)|(Rg&0x0F? 0:H_FLAG)
 
 #define M_DEC(Rg)       \
   Rg--;                 \
-  R->AF.B.l=            \
-    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[Rg]| \
+  CPU.AF.B.l=            \
+    N_FLAG|(CPU.AF.B.l&C_FLAG)|ZSTable[Rg]| \
     (Rg==0x7F? V_FLAG:0)|((Rg&0x0F)==0x0F? H_FLAG:0)
 
 #define M_ADDW(Rg1,Rg2) \
-  J.W=(R->Rg1.W+R->Rg2.W)&0xFFFF;                        \
-  R->AF.B.l=                                             \
-    (R->AF.B.l&~(H_FLAG|N_FLAG|C_FLAG))|                 \
-    ((R->Rg1.W^R->Rg2.W^J.W)&0x1000? H_FLAG:0)|          \
-    (((long)R->Rg1.W+(long)R->Rg2.W)&0x10000? C_FLAG:0); \
-  R->Rg1.W=J.W
+  J.W=(CPU.Rg1.W+CPU.Rg2.W)&0xFFFF;                        \
+  CPU.AF.B.l=                                             \
+    (CPU.AF.B.l&~(H_FLAG|N_FLAG|C_FLAG))|                 \
+    ((CPU.Rg1.W^CPU.Rg2.W^J.W)&0x1000? H_FLAG:0)|          \
+    (((long)CPU.Rg1.W+(long)CPU.Rg2.W)&0x10000? C_FLAG:0); \
+  CPU.Rg1.W=J.W
 
 #define M_ADCW(Rg)      \
-  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W+R->Rg.W+I)&0xFFFF;           \
-  R->AF.B.l=                                                   \
-    (((long)R->HL.W+(long)R->Rg.W+(long)I)&0x10000? C_FLAG:0)| \
-    (~(R->HL.W^R->Rg.W)&(R->Rg.W^J.W)&0x8000? V_FLAG:0)|       \
-    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+  I=CPU.AF.B.l&C_FLAG;J.W=(CPU.HL.W+CPU.Rg.W+I)&0xFFFF;           \
+  CPU.AF.B.l=                                                   \
+    (((long)CPU.HL.W+(long)CPU.Rg.W+(long)I)&0x10000? C_FLAG:0)| \
+    (~(CPU.HL.W^CPU.Rg.W)&(CPU.Rg.W^J.W)&0x8000? V_FLAG:0)|       \
+    ((CPU.HL.W^CPU.Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
     (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
-  R->HL.W=J.W
+  CPU.HL.W=J.W
    
 #define M_SBCW(Rg)      \
-  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W-R->Rg.W-I)&0xFFFF;           \
-  R->AF.B.l=                                                   \
+  I=CPU.AF.B.l&C_FLAG;J.W=(CPU.HL.W-CPU.Rg.W-I)&0xFFFF;           \
+  CPU.AF.B.l=                                                   \
     N_FLAG|                                                    \
-    (((long)R->HL.W-(long)R->Rg.W-(long)I)&0x10000? C_FLAG:0)| \
-    ((R->HL.W^R->Rg.W)&(R->HL.W^J.W)&0x8000? V_FLAG:0)|        \
-    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (((long)CPU.HL.W-(long)CPU.Rg.W-(long)I)&0x10000? C_FLAG:0)| \
+    ((CPU.HL.W^CPU.Rg.W)&(CPU.HL.W^J.W)&0x8000? V_FLAG:0)|        \
+    ((CPU.HL.W^CPU.Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
     (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
-  R->HL.W=J.W
-
-
-// -----------------------------------------------
-// These two functions are for the CZ80 core...
-// -----------------------------------------------
-extern u8 bMagicMegaCart, romBankMask;
-extern void cpu_writemem16 (u8 value,u16 address);
-extern void BankSwitch(u8 bank);
-INLINE void WrZ80(register word address,register byte Value)
-{
-    cpu_writemem16(Value, address);
-}
-
-INLINE byte RdZ80(register word address)
-{
-  if (bMagicMegaCart && (address >= 0xFFC0)) // Handle Megacart Hot Spots
-  {
-      BankSwitch(address & romBankMask);
-  }    
-  return (pColecoMem[address]);
-}
+  CPU.HL.W=J.W
 
 
 enum Codes
@@ -325,8 +326,8 @@ static void CodesCB(register Z80 *R)
   register byte I;
 
   /* Read opcode and count cycles */
-  I=OpZ80(R->PC.W++);
-  R->ICount-=CyclesCB[I];
+  I=OpZ80(CPU.PC.W++);
+  CPU.ICount-=CyclesCB[I];
 
   /* R register incremented on each M1 cycle */
   INCR(1);
@@ -335,11 +336,11 @@ static void CodesCB(register Z80 *R)
   {
 #include "CodesCB.h"
     default:
-      if(R->TrapBadOps)
+      if(CPU.TrapBadOps)
         printf
         (   
           "[Z80 %lX] Unrecognized instruction: CB %02X at PC=%04X\n",
-          (long)(R->User),OpZ80(R->PC.W-1),R->PC.W-2
+          (long)(CPU.User),OpZ80(CPU.PC.W-1),CPU.PC.W-2
         );
   }
 }
@@ -351,19 +352,19 @@ static void CodesDDCB(register Z80 *R)
 
 #define XX IX    
   /* Get offset, read opcode and count cycles */
-  J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-  I=OpZ80(R->PC.W++);
-  R->ICount-=CyclesXXCB[I];
+  J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+  I=OpZ80(CPU.PC.W++);
+  CPU.ICount-=CyclesXXCB[I];
 
   switch(I)
   {
 #include "CodesXCB.h"
     default:
-      if(R->TrapBadOps)
+      if(CPU.TrapBadOps)
         printf
         (
           "[Z80 %lX] Unrecognized instruction: DD CB %02X %02X at PC=%04X\n",
-          (long)(R->User),OpZ80(R->PC.W-2),OpZ80(R->PC.W-1),R->PC.W-4
+          (long)(CPU.User),OpZ80(CPU.PC.W-2),OpZ80(CPU.PC.W-1),CPU.PC.W-4
         );
   }
 #undef XX
@@ -376,19 +377,19 @@ static void CodesFDCB(register Z80 *R)
 
 #define XX IY
   /* Get offset, read opcode and count cycles */
-  J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
-  I=OpZ80(R->PC.W++);
-  R->ICount-=CyclesXXCB[I];
+  J.W=CPU.XX.W+(offset)OpZ80(CPU.PC.W++);
+  I=OpZ80(CPU.PC.W++);
+  CPU.ICount-=CyclesXXCB[I];
 
   switch(I)
   {
 #include "CodesXCB.h"
     default:
-      if(R->TrapBadOps)
+      if(CPU.TrapBadOps)
         printf
         (
           "[Z80 %lX] Unrecognized instruction: FD CB %02X %02X at PC=%04X\n",
-          (long)R->User,OpZ80(R->PC.W-2),OpZ80(R->PC.W-1),R->PC.W-4
+          (long)CPU.User,OpZ80(CPU.PC.W-2),OpZ80(CPU.PC.W-1),CPU.PC.W-4
         );
   }
 #undef XX
@@ -400,8 +401,8 @@ static void CodesED(register Z80 *R)
   register pair J;
 
   /* Read opcode and count cycles */
-  I=OpZ80(R->PC.W++);
-  R->ICount-=CyclesED[I];
+  I=OpZ80(CPU.PC.W++);
+  CPU.ICount-=CyclesED[I];
 
   /* R register incremented on each M1 cycle */
   INCR(1);
@@ -410,13 +411,13 @@ static void CodesED(register Z80 *R)
   {
 #include "CodesED.h"
     case PFX_ED:
-      R->PC.W--;break;
+      CPU.PC.W--;break;
     default:
-      if(R->TrapBadOps)
+      if(CPU.TrapBadOps)
         printf
         (
           "[Z80 %lX] Unrecognized instruction: ED %02X at PC=%04X\n",
-          (long)R->User,OpZ80(R->PC.W-1),R->PC.W-2
+          (long)CPU.User,OpZ80(CPU.PC.W-1),CPU.PC.W-2
         );
   }
 }
@@ -428,8 +429,8 @@ static void CodesDD(register Z80 *R)
 
 #define XX IX
   /* Read opcode and count cycles */
-  I=OpZ80(R->PC.W++);
-  R->ICount-=CyclesXX[I];
+  I=OpZ80(CPU.PC.W++);
+  CPU.ICount-=CyclesXX[I];
 
   /* R register incremented on each M1 cycle */
   INCR(1);
@@ -439,15 +440,15 @@ static void CodesDD(register Z80 *R)
 #include "CodesXX.h"
     case PFX_FD:
     case PFX_DD:
-      R->PC.W--;break;
+      CPU.PC.W--;break;
     case PFX_CB:
       CodesDDCB(R);break;
     default:
-      if(R->TrapBadOps)
+      if(CPU.TrapBadOps)
         printf
         (
           "[Z80 %lX] Unrecognized instruction: DD %02X at PC=%04X\n",
-          (long)R->User,OpZ80(R->PC.W-1),R->PC.W-2
+          (long)CPU.User,OpZ80(CPU.PC.W-1),CPU.PC.W-2
         );
   }
 #undef XX
@@ -460,8 +461,8 @@ static void CodesFD(register Z80 *R)
 
 #define XX IY
   /* Read opcode and count cycles */
-  I=OpZ80(R->PC.W++);
-  R->ICount-=CyclesXX[I];
+  I=OpZ80(CPU.PC.W++);
+  CPU.ICount-=CyclesXX[I];
 
   /* R register incremented on each M1 cycle */
   INCR(1);
@@ -471,14 +472,14 @@ static void CodesFD(register Z80 *R)
 #include "CodesXX.h"
     case PFX_FD:
     case PFX_DD:
-      R->PC.W--;break;
+      CPU.PC.W--;break;
     case PFX_CB:
       CodesFDCB(R);break;
     default:
         printf
         (
           "Unrecognized instruction: FD %02X at PC=%04X\n",
-          OpZ80(R->PC.W-1),R->PC.W-2
+          OpZ80(CPU.PC.W-1),CPU.PC.W-2
         );
   }
 #undef XX
@@ -491,26 +492,26 @@ static void CodesFD(register Z80 *R)
 /*************************************************************/
 void ResetZ80(Z80 *R)
 {
-  R->PC.W     = 0x0000;
-  R->SP.W     = 0xF000;
-  R->AF.W     = 0x0000;
-  R->BC.W     = 0x0000;
-  R->DE.W     = 0x0000;
-  R->HL.W     = 0x0000;
-  R->AF1.W    = 0x0000;
-  R->BC1.W    = 0x0000;
-  R->DE1.W    = 0x0000;
-  R->HL1.W    = 0x0000;
-  R->IX.W     = 0x0000;
-  R->IY.W     = 0x0000;
-  R->I        = 0x00;
-  R->R        = 0x00;
-  R->IFF      = 0x00;
-  R->ICount   = R->IPeriod;
-  R->IRequest = INT_NONE;
-  R->IBackup  = 0;
-
-  JumpZ80(R->PC.W);
+  CPU.PC.W     = 0x0000;
+  CPU.SP.W     = 0xF000;
+  CPU.AF.W     = 0x0000;
+  CPU.BC.W     = 0x0000;
+  CPU.DE.W     = 0x0000;
+  CPU.HL.W     = 0x0000;
+  CPU.AF1.W    = 0x0000;
+  CPU.BC1.W    = 0x0000;
+  CPU.DE1.W    = 0x0000;
+  CPU.HL1.W    = 0x0000;
+  CPU.IX.W     = 0x0000;
+  CPU.IY.W     = 0x0000;
+  CPU.I        = 0x00;
+  CPU.R        = 0x00;
+  CPU.IFF      = 0x00;
+  CPU.ICount   = CPU.IPeriod;
+  CPU.IRequest = INT_NONE;
+  CPU.IBackup  = 0;
+
+  JumpZ80(CPU.PC.W);
 }
 
 /** ExecZ80() ************************************************/
@@ -524,21 +525,21 @@ int ExecZ80(register Z80 *R,register int RunCycles)
   register byte I;
   register pair J;
 
-  for(R->ICount=RunCycles;;)
+  for(CPU.ICount=RunCycles;;)
   {
-    while(R->ICount>0)
+    while(CPU.ICount>0)
     {
 #ifdef DEBUG
       /* Turn tracing on when reached trap address */
-      if(R->PC.W==R->Trap) R->Trace=1;
+      if(CPU.PC.W==CPU.Trap) CPU.Trace=1;
       /* Call single-step debugger, exit if requested */
-      if(R->Trace)
-        if(!DebugZ80(R)) return(R->ICount);
+      if(CPU.Trace)
+        if(!DebugZ80(R)) return(CPU.ICount);
 #endif
 
       /* Read opcode and count cycles */
-      I=OpZ80(R->PC.W++);
-      R->ICount-=Cycles[I];
+      I=OpZ80(CPU.PC.W++);
+      CPU.ICount-=Cycles[I];
 
       /* R register incremented on each M1 cycle */
       INCR(1);
@@ -555,15 +556,15 @@ int ExecZ80(register Z80 *R,register int RunCycles)
     }
 
     /* Unless we have come here after EI, exit */
-    if(!(R->IFF&IFF_EI)) return(R->ICount);
+    if(!(CPU.IFF&IFF_EI)) return(CPU.ICount);
     else
     {
       /* Done with AfterEI state */
-      R->IFF=(R->IFF&~IFF_EI)|IFF_1;
+      CPU.IFF=(CPU.IFF&~IFF_EI)|IFF_1;
       /* Restore the ICount */
-      R->ICount+=R->IBackup-1;
+      CPU.ICount+=CPU.IBackup-1;
       /* Interrupt CPU if needed */
-      if((R->IRequest!=INT_NONE)&&(R->IRequest!=INT_QUIT)) IntZ80(R,R->IRequest);
+      if((CPU.IRequest!=INT_NONE)&&(CPU.IRequest!=INT_QUIT)) IntZ80(R,CPU.IRequest);
     }
   }
 }
@@ -575,60 +576,60 @@ int ExecZ80(register Z80 *R,register int RunCycles)
 void IntZ80(Z80 *R,word Vector)
 {
   /* If HALTed, take CPU off HALT instruction */
-  if(R->IFF&IFF_HALT) { R->PC.W++;R->IFF&=~IFF_HALT; }
+  if(CPU.IFF&IFF_HALT) { CPU.PC.W++;CPU.IFF&=~IFF_HALT; }
 
-  if((R->IFF&IFF_1)||(Vector==INT_NMI))
+  if((CPU.IFF&IFF_1)||(Vector==INT_NMI))
   {
     /* Save PC on stack */
     M_PUSH(PC);
 
     /* Automatically reset IRequest if needed */
-    if(R->IAutoReset&&(Vector==R->IRequest)) R->IRequest=INT_NONE;
+    if(CPU.IAutoReset&&(Vector==CPU.IRequest)) CPU.IRequest=INT_NONE;
 
     /* If it is NMI... */
     if(Vector==INT_NMI)
     {
       /* Clear IFF1 */
-      R->IFF&=~(IFF_1|IFF_EI);
+      CPU.IFF&=~(IFF_1|IFF_EI);
       /* Jump to hardwired NMI vector */
-      R->PC.W=0x0066;
+      CPU.PC.W=0x0066;
       JumpZ80(0x0066);
       /* Done */
       return;
     }
 
     /* Further interrupts off */
-    R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+    CPU.IFF&=~(IFF_1|IFF_2|IFF_EI);
 
     /* If in IM2 mode... */
-    if(R->IFF&IFF_IM2)
+    if(CPU.IFF&IFF_IM2)
     {
       /* Make up the vector address */
-      Vector=(Vector&0xFF)|((word)(R->I)<<8);
+      Vector=(Vector&0xFF)|((word)(CPU.I)<<8);
       /* Read the vector */
-      R->PC.B.l=RdZ80(Vector++);
-      R->PC.B.h=RdZ80(Vector);
-      JumpZ80(R->PC.W);
+      CPU.PC.B.l=RdZ80(Vector++);
+      CPU.PC.B.h=RdZ80(Vector);
+      JumpZ80(CPU.PC.W);
       /* Done */
       return;
     }
 
     /* If in IM1 mode, just jump to hardwired IRQ vector */
-    if(R->IFF&IFF_IM1) { R->PC.W=0x0038;JumpZ80(0x0038);return; }
+    if(CPU.IFF&IFF_IM1) { CPU.PC.W=0x0038;JumpZ80(0x0038);return; }
 
     /* If in IM0 mode... */
 
     /* Jump to a vector */
     switch(Vector)
     {
-      case INT_RST00: R->PC.W=0x0000;JumpZ80(0x0000);break;
-      case INT_RST08: R->PC.W=0x0008;JumpZ80(0x0008);break;
-      case INT_RST10: R->PC.W=0x0010;JumpZ80(0x0010);break;
-      case INT_RST18: R->PC.W=0x0018;JumpZ80(0x0018);break;
-      case INT_RST20: R->PC.W=0x0020;JumpZ80(0x0020);break;
-      case INT_RST28: R->PC.W=0x0028;JumpZ80(0x0028);break;
-      case INT_RST30: R->PC.W=0x0030;JumpZ80(0x0030);break;
-      case INT_RST38: R->PC.W=0x0038;JumpZ80(0x0038);break;
+      case INT_RST00: CPU.PC.W=0x0000;JumpZ80(0x0000);break;
+      case INT_RST08: CPU.PC.W=0x0008;JumpZ80(0x0008);break;
+      case INT_RST10: CPU.PC.W=0x0010;JumpZ80(0x0010);break;
+      case INT_RST18: CPU.PC.W=0x0018;JumpZ80(0x0018);break;
+      case INT_RST20: CPU.PC.W=0x0020;JumpZ80(0x0020);break;
+      case INT_RST28: CPU.PC.W=0x0028;JumpZ80(0x0028);break;
+      case INT_RST30: CPU.PC.W=0x0030;JumpZ80(0x0030);break;
+      case INT_RST38: CPU.PC.W=0x0038;JumpZ80(0x0038);break;
     }
   }
 }
@@ -648,16 +649,16 @@ word RunZ80(Z80 *R)
   {
 #ifdef DEBUG
     /* Turn tracing on when reached trap address */
-    if(R->PC.W==R->Trap) R->Trace=1;
+    if(CPU.PC.W==CPU.Trap) CPU.Trace=1;
     /* Call single-step debugger, exit if requested */
-    if(R->Trace){
-      if(!DebugZ80(R)) return(R->PC.W);
+    if(CPU.Trace){
+      if(!DebugZ80(R)) return(CPU.PC.W);
 }
 #endif
 
     /* Read opcode and count cycles */
-    I=OpZ80(R->PC.W++);
-    R->ICount-=Cycles[I];
+    I=OpZ80(CPU.PC.W++);
+    CPU.ICount-=Cycles[I];
 
     /* R register incremented on each M1 cycle */
     INCR(1);
@@ -672,37 +673,37 @@ word RunZ80(Z80 *R)
     }
  
     /* If cycle counter expired... */
-    if(R->ICount<=0)
+    if(CPU.ICount<=0)
     {
       /* If we have come after EI, get address from IRequest */
       /* Otherwise, get it from the loop handler             */
-      if(R->IFF&IFF_EI)
+      if(CPU.IFF&IFF_EI)
       {
-        R->IFF=(R->IFF&~IFF_EI)|IFF_1; /* Done with AfterEI state */
-        R->ICount+=R->IBackup-1;       /* Restore the ICount      */
+        CPU.IFF=(CPU.IFF&~IFF_EI)|IFF_1; /* Done with AfterEI state */
+        CPU.ICount+=CPU.IBackup-1;       /* Restore the ICount      */
 
         /* Call periodic handler or set pending IRQ */
-        if(R->ICount>0) J.W=R->IRequest;
+        if(CPU.ICount>0) J.W=CPU.IRequest;
         else
         {
           J.W=LoopZ80(R);        /* Call periodic handler    */
-          R->ICount+=R->IPeriod; /* Reset the cycle counter  */
-          if(J.W==INT_NONE) J.W=R->IRequest;  /* Pending IRQ */
+          CPU.ICount+=CPU.IPeriod; /* Reset the cycle counter  */
+          if(J.W==INT_NONE) J.W=CPU.IRequest;  /* Pending IRQ */
         }
       }
       else
       {
         J.W=LoopZ80(R);          /* Call periodic handler    */
-        R->ICount+=R->IPeriod;   /* Reset the cycle counter  */
-        if(J.W==INT_NONE) J.W=R->IRequest;    /* Pending IRQ */
+        CPU.ICount+=CPU.IPeriod;   /* Reset the cycle counter  */
+        if(J.W==INT_NONE) J.W=CPU.IRequest;    /* Pending IRQ */
       }
 
-      if(J.W==INT_QUIT) return(R->PC.W); /* Exit if INT_QUIT */
+      if(J.W==INT_QUIT) return(CPU.PC.W); /* Exit if INT_QUIT */
       if(J.W!=INT_NONE) IntZ80(R,J.W);   /* Int-pt if needed */
     }
   }
 
   /* Execution stopped */
-  return(R->PC.W);
+  return(CPU.PC.W);
 }
 #endif /* !EXECZ80 */
diff --git a/arm9/source/cpu/z80/Z80.h b/arm9/source/cpu/z80/Z80.h
index acc876ab..2444f8d8 100644
--- a/arm9/source/cpu/z80/Z80.h
+++ b/arm9/source/cpu/z80/Z80.h
@@ -19,7 +19,7 @@ extern "C" {
 
                                /* Compilation options:       */
 /* #define DEBUG */            /* Compile debugging version  */
-#define LSB_FIRST         /* Compile for low-endian CPU */
+#define LSB_FIRST              /* Compile for low-endian CPU */
 /* #define MSB_FIRST */        /* Compile for hi-endian CPU  */
 #define EXECZ80                /* Call Z80 each scanline     */