diff --git a/.gitignore b/.gitignore
index e18b8a452..ab287f854 100644
--- a/.gitignore
+++ b/.gitignore
@@ -230,3 +230,6 @@ lib/r_bsp
lib/r_config
lib/r_flash_rx
lib/r_tsip_rx
+
+Debug/
+Release/
diff --git a/IDE/XilinxSDK/.cproject b/IDE/XilinxSDK/.cproject
index 27798132c..25ab1f61b 100644
--- a/IDE/XilinxSDK/.cproject
+++ b/IDE/XilinxSDK/.cproject
@@ -1,134 +1,127 @@
-
-
-
-
-
-
-
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
@@ -136,130 +129,129 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
+
-
-
-
-
@@ -267,36 +259,35 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/IDE/XilinxSDK/.project b/IDE/XilinxSDK/.project
index ec014f0bc..85fe00c9a 100644
--- a/IDE/XilinxSDK/.project
+++ b/IDE/XilinxSDK/.project
@@ -1,9 +1,9 @@
- efuse_wolfboot
- Created by SDK v2018.2. standalone_bsp_0 - psu_cortexa53_0
+ wolfboot
+ Created by Vitis v2022.1
- standalone_bsp_0
+ zcu102
@@ -19,6 +19,7 @@
+ com.xilinx.sdx.sdk.core.SdkProjectNature
org.eclipse.cdt.core.cnature
org.eclipse.cdt.managedbuilder.core.managedBuildNature
org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
diff --git a/IDE/XilinxSDK/README.md b/IDE/XilinxSDK/README.md
index 72d8b0ef3..6d101bc24 100644
--- a/IDE/XilinxSDK/README.md
+++ b/IDE/XilinxSDK/README.md
@@ -19,7 +19,7 @@ You may need to adjust/add the following project settings under Properties -> C/
1) Platform bspInclude path: "Paths and Symbols" -> "Includes" -> "GNU C" -> "Add" -> Workspace Path for platform (example: `/zcu102/export/zcu102/sw/zcu102/standalone_domain/bspinclude/include`).
-2) Platform BSP Library path: See "Library Paths" -> "Add" (example: `/zcu102/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/lib`).ß
+2) Platform BSP Library path: See "Library Paths" -> "Add" (example: `/zcu102/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/lib`).
## wolfBoot Configuration
@@ -43,8 +43,22 @@ Note: If not using Position Independent Code (PIC) the linker script `ldscript.l
## Signing Example
```sh
-make keytools
-./tools/keytools/sign --rsa4096 --sha3 ../helloworld/Debug/helloworld.elf ./rsa4096.der 1
+$ make keytools
+$ ./tools/keytools/sign --rsa4096 --sha3 ../hello_world/Debug/hello_world.elf ./wolfboot_signing_private_key.der 1
+wolfBoot KeyTools (Compiled C version)
+wolfBoot version 2020000
+Update type: Firmware
+Input image: ../hello_world/Debug/hello_world.elf
+Selected cipher: RSA4096
+Selected hash : SHA3
+Public key: ./wolfboot_signing_private_key.der
+Output image: ../hello_world/Debug/hello_world_v1_signed.bin
+Target partition id : 1
+Found RSA512 key
+image header size calculated at runtime (1024 bytes)
+Calculating SHA3 digest...
+Signing the digest...
+Output image(s) successfully created.
```
## Bootgen
@@ -55,6 +69,45 @@ Xilinx uses a `bootgen` tool for generating a boot binary image that has Xilinx
* Use "offset=" option to place the application into a specific location in flash.
* Use "load=" option to have FSBL load into specific location in RAM.
+Generating a boot.bin (from boot.bif).
+Run the Xilinx -> Vitis Shell and cd into the workspace root.
+
+Example boot.bif in workspace root:
+
+```
+// Boot BIF example for wolfBoot with signed Hello World
+// Note: "partition_owner=uboot" prevents partition from being loaded to RAM
+the_ROM_image:
+{
+ [bootloader, destination_cpu=a53-0] zcu102\zynqmp_fsbl\fsbl_a53.elf
+ [destination_cpu=a53-0, exception_level=el-1] wolfboot\Debug\wolfboot.elf
+ [destination_cpu=a53-0, partition_owner=uboot, offset=0x800000] hello_world\Debug\hello_world_v1_signed.bin
+}
+```
+
+```sh
+bootgen -image boot.bif -arch zynqmp -o BOOT.bin
+
+****** Xilinx Bootgen v2022.1
+ **** Build date : Apr 18 2022-16:02:32
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+[INFO] : Bootimage generated successfully
+```
+
+## Running Boot.bin
+
+* QSPI: Flash using Vitis -> Xilinx (menu) -> Program Flash
+* SD: or copy boot.bin to SDCARD
+
+| Boot Mode | MODE Pins 3:0 | Mode SW6[4:1] |
+| --------- | ------------- | -------------- |
+| JTAG | 0 0 0 0 | on, on, on, on |
+| QSPI32 | 0 0 1 0 | on, on, off,on |
+| SD | 1 1 1 0 | off,off,off,on |
+
+
+
### Adding RSA Authentication
1. Generate keys:
diff --git a/hal/zynq.c b/hal/zynq.c
index da492fa22..56a23f08c 100644
--- a/hal/zynq.c
+++ b/hal/zynq.c
@@ -183,7 +183,7 @@
#define GQSPI_QSPI_MODE GQSPI_GEN_FIFO_MODE_QSPI
#endif
#ifndef GQPI_USE_DUAL_PARALLEL
-#define GQPI_USE_DUAL_PARALLEL 1 /* stripe */
+#define GQPI_USE_DUAL_PARALLEL 0 /* default is single QSPI chip. Use 1=stripe */
#endif
#ifndef GQPI_USE_4BYTE_ADDR
#define GQPI_USE_4BYTE_ADDR 1
@@ -271,8 +271,8 @@ static QspiDev_t mDev;
static int qspi_wait_ready(QspiDev_t* dev);
static int qspi_status(QspiDev_t* dev, uint8_t* status);
static int qspi_wait_we(QspiDev_t* dev);
-#ifdef TEST_FLASH
-static int test_flash(QspiDev_t* dev);
+#ifdef TEST_EXT_FLASH
+static int test_ext_flash(QspiDev_t* dev);
#endif
/* eFUSE support */
@@ -359,8 +359,13 @@ void uart_write(const char* buf, uint32_t sz)
{
uint32_t pos = 0;
while (sz-- > 0) {
+ char c = buf[pos++];
+ if (c == '\n') { /* handle CRLF */
+ while (ZYNQMP_UART_SR & ZYNQMP_UART_SR_TXFULL);
+ ZYNQMP_UART_SR = '\r';
+ }
while (ZYNQMP_UART_SR & ZYNQMP_UART_SR_TXFULL);
- ZYNQMP_UART_SR = (uint32_t)buf[pos++];
+ ZYNQMP_UART_SR = c;
}
/* Wait till TX Fifo is empty */
while (!(ZYNQMP_UART_SR & ZYNQMP_UART_SR_TXEMPTY));
@@ -1109,8 +1114,8 @@ void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
return;
#endif
-#ifdef TEST_FLASH
- test_flash(&mDev);
+#ifdef TEST_EXT_FLASH
+ test_ext_flash(&mDev);
#endif
}
@@ -1146,18 +1151,17 @@ void zynq_exit(void)
void hal_init(void)
{
uint32_t cpu_freq = 0;
-
-#ifdef DEBUG_ZYNQ
const char* bootMsg = "\nwolfBoot Secure Boot\n";
+
#ifdef DEBUG_UART
uart_init();
- uart_write(bootMsg, strlen(bootMsg));
#endif
wolfBoot_printf(bootMsg);
-#endif /* DEBUG_ZYNQ */
+#ifdef USE_BUILTIN_STARTUP /* Vitis is EL-3 */
/* This is only allowed for EL-3 */
- //asm volatile("msr cntfrq_el0, %0" : : "r" (cpu_freq) : "memory");
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cpu_freq) : "memory");
+#endif
zynq_init(cpu_freq);
}
@@ -1338,9 +1342,11 @@ void* hal_get_dts_address(void)
#endif
-#ifdef TEST_FLASH
-#define TEST_ADDRESS 0x2800000 /* 40MB */
-static int test_flash(QspiDev_t* dev)
+#ifdef TEST_EXT_FLASH
+#ifndef TEST_EXT_ADDRESS
+#define TEST_EXT_ADDRESS 0x2800000 /* 40MB */
+#endif
+static int test_ext_flash(QspiDev_t* dev)
{
int ret;
uint32_t i;
@@ -1348,20 +1354,20 @@ static int test_flash(QspiDev_t* dev)
#ifndef TEST_FLASH_READONLY
/* Erase sector */
- ret = ext_flash_erase(TEST_ADDRESS, WOLFBOOT_SECTOR_SIZE);
+ ret = ext_flash_erase(TEST_EXT_ADDRESS, WOLFBOOT_SECTOR_SIZE);
wolfBoot_printf("Erase Sector: Ret %d\n", ret);
/* Write Pages */
for (i=0; i