From 51de556e1b14824bed1ab0fd051721c346187c40 Mon Sep 17 00:00:00 2001 From: Daniele Lacamera Date: Thu, 21 Apr 2022 18:53:24 +0200 Subject: [PATCH 1/4] Added support for NXP i.MX-RT105x --- arch.mk | 47 +++-- config/examples/imx-rt1050.config | 29 +++ config/examples/imx-rt1060.config | 2 +- hal/imx_rt.c | 24 ++- hal/imx_rt1050_nor.h | 266 +++++++++++++++++++++++++ hal/{imx_rt_nor.h => imx_rt1060_nor.h} | 53 +++-- test-app/Makefile | 25 ++- test-app/app_imx_rt.c | 38 +++- test-app/imx_rt_clock_config.c | 29 ++- 9 files changed, 449 insertions(+), 64 deletions(-) create mode 100644 config/examples/imx-rt1050.config create mode 100644 hal/imx_rt1050_nor.h rename hal/{imx_rt_nor.h => imx_rt1060_nor.h} (90%) diff --git a/arch.mk b/arch.mk index 3e836b465..a5babb8ef 100644 --- a/arch.mk +++ b/arch.mk @@ -226,15 +226,28 @@ ifeq ($(TARGET),imx_rt) -I$(MCUXPRESSO)/components/flash/nor \ -I$(MCUXPRESSO)/components/flash/nor/flexspi \ -I$(MCUXPRESSO)/components/serial_manager/ \ - -DCPU_$(MCUXPRESSO_CPU) -I$(MCUXPRESSO_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -I$(MCUXPRESSO_DRIVERS)/project_template/ \ - -I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ -DXIP_EXTERNAL_FLASH=1 -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -DPRINTF_ADVANCED_ENABLE=1 \ + -DCPU_$(MCUXPRESSO_CPU) -I$(MCUXPRESSO_CMSIS)/Include \ + -DCPU_$(MCUXPRESSO_CPU) -I$(MCUXPRESSO_CMSIS)/Core/Include \ + -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -I$(MCUXPRESSO_DRIVERS)/project_template/ \ + -DXIP_EXTERNAL_FLASH=1 -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -DPRINTF_ADVANCED_ENABLE=1 \ -DSCANF_ADVANCED_ENABLE=1 -DSERIAL_PORT_TYPE_UART=1 -DNDEBUG=1 + OBJS+= $(MCUXPRESSO_DRIVERS)/drivers/fsl_clock.o $(MCUXPRESSO_DRIVERS)/drivers/fsl_flexspi.o + ifeq ($(MCUXPRESSO_CPU),MIMXRT1052DVJ6B) + CFLAGS+=-I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ + ifeq ($(PKA),1) + PKA_EXTRA_OBJS+= $(MCUXPRESSO)/devices/MIMXRT1062/drivers/fsl_dcp.o + endif + else + CFLAGS+=-I$(MCUXPRESSO)/boards/evkmimxrt1050/xip/ + ifeq ($(PKA),1) + PKA_EXTRA_OBJS+= $(MCUXPRESSO)/devices/MIMXRT1052/drivers/fsl_dcp.o + endif + endif + ifeq ($(PKA),1) - PKA_EXTRA_OBJS+= \ - $(MCUXPRESSO)/devices/MIMXRT1062/drivers/fsl_dcp.o \ - ./lib/wolfssl/wolfcrypt/src/port/nxp/dcp_port.o - PKA_EXTRA_CFLAGS+=-DWOLFSSL_IMXRT_DCP + PKA_EXTRA_OBJS+=./lib/wolfssl/wolfcrypt/src/port/nxp/dcp_port.o + PKA_EXTRA_CFLAGS+=-DWOLFSSL_IMXRT_DCP endif endif @@ -298,17 +311,17 @@ ifeq ($(TARGET),psoc6) $(CYPRESS_PDL)/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.o \ $(CYPRESS_PDL)/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.o PSOC6_CRYPTO_OBJS=./lib/wolfssl/wolfcrypt/src/port/cypress/psoc6_crypto.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_vu.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_ecc_domain_params.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_ecc_nist_p.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_ecc_ecdsa.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_sha_v2.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_sha_v1.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_mem_v2.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_mem_v1.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_hw.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto_core_hw_v1.o \ - $(CYPRESS_PDL)/drivers/source/cy_crypto.o + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_vu.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_ecc_domain_params.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_ecc_nist_p.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_ecc_ecdsa.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_sha_v2.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_sha_v1.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_mem_v2.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_mem_v1.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_hw.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto_core_hw_v1.o \ + $(CYPRESS_PDL)/drivers/source/cy_crypto.o CFLAGS+=-I$(CYPRESS_PDL)/drivers/include/ \ -I$(CYPRESS_PDL)/devices/include \ diff --git a/config/examples/imx-rt1050.config b/config/examples/imx-rt1050.config new file mode 100644 index 000000000..beb5a22c8 --- /dev/null +++ b/config/examples/imx-rt1050.config @@ -0,0 +1,29 @@ +ARCH?=ARM +TARGET?=imx_rt +SIGN?=ECC256 +HASH?=SHA256 +MCUXPRESSO?=$(PWD)/../SDK_2_11_0_EVKB-IMXRT1050 +MCUXPRESSO_CPU?=MIMXRT1052DVJ6B +MCUXPRESSO_DRIVERS?=$(MCUXPRESSO)/devices/MIMXRT1052 +MCUXPRESSO_CMSIS?=$(MCUXPRESSO)/CMSIS +DEBUG?=0 +VTOR?=1 +CORTEX_M0?=0 +NO_ASM?=0 +NO_MPU=1 +EXT_FLASH?=0 +SPI_FLASH?=0 +ALLOW_DOWNGRADE?=0 +NVM_FLASH_WRITEONCE?=1 +WOLFBOOT_VERSION?=0 +V?=0 +SPMATH?=1 +RAM_CODE?=0 +DUALBANK_SWAP?=0 +PKA?=0 +WOLFBOOT_PARTITION_SIZE?=0x20000 +WOLFBOOT_SECTOR_SIZE?=0x1000 +WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x60010000 +WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x60030000 +WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x60050000 +WOLFBOOT_SMALL_STACK?=1 diff --git a/config/examples/imx-rt1060.config b/config/examples/imx-rt1060.config index 06ed4e057..1bbf21377 100644 --- a/config/examples/imx-rt1060.config +++ b/config/examples/imx-rt1060.config @@ -2,7 +2,7 @@ ARCH?=ARM TARGET?=imx_rt SIGN?=ECC256 HASH?=SHA256 -MCUXPRESSO?=$(PWD)/../SDK-2.8.2_EVK-MIMXRT1060 +MCUXPRESSO?=$(PWD)/../SDK-2.11.0_EVK-MIMXRT1060 MCUXPRESSO_CPU?=MIMXRT1062DVL6A MCUXPRESSO_DRIVERS?=$(MCUXPRESSO)/devices/MIMXRT1062 MCUXPRESSO_CMSIS?=$(MCUXPRESSO)/CMSIS diff --git a/hal/imx_rt.c b/hal/imx_rt.c index 9133fbff6..7f9728d8a 100644 --- a/hal/imx_rt.c +++ b/hal/imx_rt.c @@ -30,7 +30,12 @@ #include "fsl_nor_flash.h" #include "fsl_flexspi.h" #include "fsl_flexspi_nor_flash.h" -#include "imx_rt_nor.h" +#ifdef CPU_MIMXRT1062DVL6A +#include "imx_rt1060_nor.h" +#endif +#ifdef CPU_MIMXRT1052DVJ6B +#include "imx_rt1050_nor.h" +#endif #include "xip/fsl_flexspi_nor_boot.h" #ifdef __WOLFBOOT @@ -213,6 +218,14 @@ const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_c const uint8_t dcd_data[1] = {0}; extern void isr_reset(void); + +const BOOT_DATA_T __attribute__((section(".boot_data"))) boot_data = { + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + const ivt __attribute__((section(".image_vt"))) image_vector_table = { IVT_HEADER, /* IVT Header */ (uint32_t)isr_reset, /* Image Entry Function */ @@ -224,13 +237,6 @@ const ivt __attribute__((section(".image_vt"))) image_vector_table = { IVT_RSVD /* Reserved = 0 */ }; -const BOOT_DATA_T __attribute__((section(".boot_data"))) boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; - /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -304,11 +310,13 @@ static void clock_init(void) CCM->CBCDR = (CCM->CBCDR & (~(CCM_CBCDR_SEMC_PODF_MASK | CCM_CBCDR_AHB_PODF_MASK | CCM_CBCDR_IPG_PODF_MASK))) | CCM_CBCDR_SEMC_PODF(2) | CCM_CBCDR_AHB_PODF(2) | CCM_CBCDR_IPG_PODF(2); +#ifdef CPU_MIMXRT1062DVL6A // Configure FLEXSPI2 CLOCKS CCM->CBCMR = (CCM->CBCMR & (~(CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK | CCM_CBCMR_FLEXSPI2_PODF_MASK))) | CCM_CBCMR_PRE_PERIPH_CLK_SEL(3) | CCM_CBCMR_FLEXSPI2_CLK_SEL(1) | CCM_CBCMR_FLEXSPI2_PODF(7); +#endif // Confgiure FLEXSPI CLOCKS CCM->CSCMR1 = ((CCM->CSCMR1 & diff --git a/hal/imx_rt1050_nor.h b/hal/imx_rt1050_nor.h new file mode 100644 index 000000000..7a2cfd3cc --- /dev/null +++ b/hal/imx_rt1050_nor.h @@ -0,0 +1,266 @@ + +/* wolfBoot interface for iMX-RT1060-EVK. + * + * Description of the NOR configuration interface required by the board. + * + * Copyright (C) 2021 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef IMXRT_NOR +#define IMXRT_NOR +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +/* FlexSPI Memory Configuration Block */ +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_common_mem_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +/* +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + */ + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_common_mem_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#endif /* IMXRT_NOR */ diff --git a/hal/imx_rt_nor.h b/hal/imx_rt1060_nor.h similarity index 90% rename from hal/imx_rt_nor.h rename to hal/imx_rt1060_nor.h index a0fa737c5..a897a1d3e 100644 --- a/hal/imx_rt_nor.h +++ b/hal/imx_rt1060_nor.h @@ -159,25 +159,7 @@ enum kDeviceConfigCmdType_Reset, //!< Reset device command }; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block - -/* - * Serial NOR configuration block - */ +/* FlexSPI Memory Configuration Block */ typedef struct _FlexSPIConfig { uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL @@ -231,6 +213,39 @@ typedef struct _FlexSPIConfig uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use } flexspi_common_mem_t; +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ typedef struct _flexspi_nor_config { flexspi_common_mem_t memConfig; //!< Common memory configuration info via FlexSPI diff --git a/test-app/Makefile b/test-app/Makefile index ddc27f70f..b5d67ceb6 100644 --- a/test-app/Makefile +++ b/test-app/Makefile @@ -95,7 +95,7 @@ ifeq ($(TARGET),stm32l5) else LSCRIPT_TEMPLATE=ARM-stm32l5.ld endif - CFLAGS+=-mcpu=cortex-m33 + CFLAGS+=-mcpu=cortex-m33 LDFLAGS+=-mcpu=cortex-m33 endif @@ -105,7 +105,7 @@ ifeq ($(TARGET),stm32u5) else LSCRIPT_TEMPLATE=ARM-stm32u5.ld endif - CFLAGS+=-mcpu=cortex-m33 + CFLAGS+=-mcpu=cortex-m33 LDFLAGS+=-mcpu=cortex-m33 endif @@ -143,7 +143,6 @@ endif ifeq ($(TARGET),imx_rt) CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/drivers -I$(MCUXPRESSO_DRIVERS) -DCPU_$(MCUXPRESSO_CPU) -I$(MCUXPRESSO_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -DXIP_EXTERNAL_FLASH=1 \ - -I$(MCUXPRESSO_DRIVERS)/project_template/ -I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ \ -I$(MCUXPRESSO_DRIVERS)/utilities/debug_console/ -I$(MCUXPRESSO)/components/serial_manager \ -I$(MCUXPRESSO)/components/uart/ -I$(MCUXPRESSO_DRIVERS)/utilities/str/ \ -I$(MCUXPRESSO)/components/flash/nor \ @@ -152,16 +151,26 @@ ifeq ($(TARGET),imx_rt) LDFLAGS+=-mcpu=cortex-m7 -Wall --specs=nosys.specs -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mthumb -mapcs -Xlinker --gc-sections -Xlinker -static -Xlinker -z -Xlinker muldefs -Xlinker -Map=output.map -static -lm -lc -lnosys LSCRIPT_TEMPLATE=imx_rt.ld APP_OBJS+=$(MCUXPRESSO_DRIVERS)/drivers/fsl_gpio.o $(MCUXPRESSO_DRIVERS)/drivers/fsl_common.o $(MCUXPRESSO_DRIVERS)/drivers/fsl_clock.o \ - imx_rt_clock_config.o $(MCUXPRESSO_DRIVERS)/system_MIMXRT1062.o \ + $(MCUXPRESSO_DRIVERS)/drivers/fsl_common_arm.o \ + imx_rt_clock_config.o \ $(MCUXPRESSO_DRIVERS)/drivers/fsl_flexspi.o \ $(MCUXPRESSO_DRIVERS)/utilities/str/fsl_str.o \ - $(MCUXPRESSO)/components/uart/lpuart_adapter.o \ - $(MCUXPRESSO)/components/serial_manager/serial_manager.o \ - $(MCUXPRESSO)/components/lists/generic_list.o \ - $(MCUXPRESSO)/components/serial_manager/serial_port_uart.o \ + $(MCUXPRESSO)/components/uart/fsl_adapter_lpuart.o \ + $(MCUXPRESSO)/components/serial_manager/fsl_component_serial_manager.o \ + $(MCUXPRESSO)/components/lists/fsl_component_generic_list.o \ + $(MCUXPRESSO)/components/serial_manager/fsl_component_serial_port_uart.o \ $(MCUXPRESSO_DRIVERS)/drivers/fsl_lpuart.o \ $(MCUXPRESSO)/components/flash/nor/flexspi/fsl_flexspi_nor_flash.o \ $(MCUXPRESSO_DRIVERS)/utilities/debug_console/fsl_debug_console.o + + + ifeq ($(MCUXPRESSO_CPU),MIMXRT1052DVJ6B) + CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/project_template/ -I$(MCUXPRESSO)/boards/evkmimxrt1050/xip/ + APP_OBJS+=$(MCUXPRESSO_DRIVERS)/system_MIMXRT1052.o + else ifeq ($(MCUXPRESSO_CPU),MIMXRT1062DVL6A) + CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/project_template/ -I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ + APP_OBJS+=$(MCUXPRESSO_DRIVERS)/system_MIMXRT1062.o + endif endif ifeq ($(TARGET),stm32g0) diff --git a/test-app/app_imx_rt.c b/test-app/app_imx_rt.c index 03c98de89..4f8f1468a 100644 --- a/test-app/app_imx_rt.c +++ b/test-app/app_imx_rt.c @@ -26,9 +26,12 @@ #include "fsl_iomuxc.h" static int g_pinSet = false; +extern void imx_rt_init_boot_clock(void); + + /* Get debug console frequency. */ -static uint32_t rt1060_debug_console_get_freq(void) +static uint32_t debug_console_get_freq(void) { uint32_t freq; /* To make it simple, we assume default PLL and divider settings, and the only variable @@ -49,12 +52,13 @@ static uint32_t rt1060_debug_console_get_freq(void) #define UART_BASEADDR (uint32_t) LPUART1 #define UART_INSTANCE 1U #define UART_BAUDRATE (115200U) -void rt1060_init_debug_console(void) +void init_debug_console(void) { - uint32_t uartClkSrcFreq = rt1060_debug_console_get_freq(); + uint32_t uartClkSrcFreq = debug_console_get_freq(); DbgConsole_Init(UART_INSTANCE, UART_BAUDRATE, UART_TYPE, uartClkSrcFreq); } +#ifdef CPU_MIMXRT1062DVL6A /* Pin settings */ void rt1060_init_pins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ @@ -86,16 +90,38 @@ void rt1060_init_pins(void) { 0x10B0U); } +#endif + +#ifdef CPU_MIMXRT1052DVJ6B +void rt1050_init_pins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_CCM_CLKO1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_CCM_CLKO2, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_CCM_CLKO1, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_CCM_CLKO2, 0x10B0U); +} +#endif + -void rt1060_init_boot_clock(void); void main() { + + imx_rt_init_boot_clock(); +#ifdef CPU_MIMXRT1062DVL6A rt1060_init_pins(); - rt1060_init_boot_clock(); +#endif + +#ifdef CPU_MIMXRT1052DVJ6B + rt1050_init_pins(); +#endif SystemCoreClockUpdate(); SysTick_Config(SystemCoreClock / 1000U); - rt1060_init_debug_console(); + init_debug_console(); PRINTF("wolfBoot Test app, version = %d\n", wolfBoot_current_firmware_version()); while(1) { SDK_DelayAtLeastUs(100000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); diff --git a/test-app/imx_rt_clock_config.c b/test-app/imx_rt_clock_config.c index e23a6c0e6..e463637b2 100644 --- a/test-app/imx_rt_clock_config.c +++ b/test-app/imx_rt_clock_config.c @@ -47,7 +47,7 @@ const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; -void rt1060_init_boot_clock(void) +void imx_rt_init_boot_clock(void) { /* Init RTC OSC clock frequency. */ CLOCK_SetRtcXtalFreq(32768U); @@ -125,17 +125,28 @@ void rt1060_init_boot_clock(void) #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 3); + #ifdef CPU_MIMXRT1062DVL6A + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); + #endif + #ifdef CPU_MIMXRT1062DVL6A + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); + #endif #endif + +#ifdef CPU_MIMXRT1062DVL6A /* Disable Flexspi2 clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi2); /* Set FLEXSPI2_PODF. */ CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); /* Set Flexspi2 clock source. */ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); +#endif /* Disable CSI clock gate. */ CLOCK_DisableClock(kCLOCK_Csi); /* Set CSI_PODF. */ @@ -192,10 +203,14 @@ void rt1060_init_boot_clock(void) /* Disable CAN clock gate. */ CLOCK_DisableClock(kCLOCK_Can1); CLOCK_DisableClock(kCLOCK_Can2); +#ifdef CPU_MIMXRT1062DVL6A CLOCK_DisableClock(kCLOCK_Can3); +#endif CLOCK_DisableClock(kCLOCK_Can1S); CLOCK_DisableClock(kCLOCK_Can2S); +#ifdef CPU_MIMXRT1062DVL6A CLOCK_DisableClock(kCLOCK_Can3S); +#endif /* Set CAN_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_CanDiv, 1); /* Set Can clock source. */ @@ -320,10 +335,12 @@ void rt1060_init_boot_clock(void) CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); /* Enable Enet output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; +#ifdef CPU_MIMXRT1062DVL6A /* Set Enet2 output divider. */ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); /* Enable Enet2 output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; +#endif /* Enable Enet25M output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; /* DeInit Usb2 PLL. */ @@ -370,11 +387,13 @@ void rt1060_init_boot_clock(void) IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); /* Set ENET1 Tx clock source. */ IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); +#ifdef CPU_MIMXRT1062DVL6A /* Set ENET2 Tx clock source. */ #if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); #else IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); +#endif #endif /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; From ee2e250376e812966333531107af3c613c882bcd Mon Sep 17 00:00:00 2001 From: Daniele Lacamera Date: Wed, 27 Apr 2022 12:29:36 +0200 Subject: [PATCH 2/4] [RT1050] Fix flash geometry configuration --- hal/imx_rt.c | 139 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 91 insertions(+), 48 deletions(-) diff --git a/hal/imx_rt.c b/hal/imx_rt.c index 7f9728d8a..923692807 100644 --- a/hal/imx_rt.c +++ b/hal/imx_rt.c @@ -83,14 +83,10 @@ typedef struct /* Flex SPI op */ typedef enum _FlexSPIOperationType { - kFlexSpiOperation_Command, //!< FlexSPI operation: Only command, both TX and - //! RX buffer are ignored. - kFlexSpiOperation_Config, //!< FlexSPI operation: Configure device mode, the - //! TX FIFO size is fixed in LUT. - kFlexSpiOperation_Write, //!< FlexSPI operation: Write, only TX buffer is - //! effective - kFlexSpiOperation_Read, //!< FlexSPI operation: Read, only Rx Buffer is - //! effective. + kFlexSpiOperation_Command, + kFlexSpiOperation_Config, + kFlexSpiOperation_Write, + kFlexSpiOperation_Read, kFlexSpiOperation_End = kFlexSpiOperation_Read, } flexspi_operation_t; @@ -115,14 +111,14 @@ typedef struct _serial_nor_config_option { struct { - uint32_t max_freq : 4; //!< Maximum supported Frequency - uint32_t misc_mode : 4; //!< miscellaneous mode - uint32_t quad_mode_setting : 4; //!< Quad mode setting - uint32_t cmd_pads : 4; //!< Command pads - uint32_t query_pads : 4; //!< SFDP read pads - uint32_t device_type : 4; //!< Device type - uint32_t option_size : 4; //!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 - uint32_t tag : 4; //!< Tag, must be 0x0E + uint32_t max_freq : 4; /* Maximum supported Frequency */ + uint32_t misc_mode : 4; /* miscellaneous mode */ + uint32_t quad_mode_setting : 4; /* Quad mode setting */ + uint32_t cmd_pads : 4; /* Command pads */ + uint32_t query_pads : 4; /* SFDP read pads */ + uint32_t device_type : 4; /* Device type */ + uint32_t option_size : 4; /* Option size, in terms of uint32_t, size = (option_size + 1) * 4 */ + uint32_t tag : 4; /* Tag, must be 0x0E */ } B; uint32_t U; } option0; @@ -130,11 +126,11 @@ typedef struct _serial_nor_config_option { struct { - uint32_t dummy_cycles : 8; //!< Dummy cycles before read - uint32_t reserved0 : 8; //!< Reserved for future use - uint32_t pinmux_group : 4; //!< The pinmux group selection - uint32_t reserved1 : 8; //!< Reserved for future use - uint32_t flash_connection : 4; //!< Flash connection option: 0 - Single Flash connected to port A + uint32_t dummy_cycles : 8; /* Dummy cycles before read */ + uint32_t reserved0 : 8; /* Reserved for future use */ + uint32_t pinmux_group : 4; /* The pinmux group selection */ + uint32_t reserved1 : 8; /* Reserved for future use */ + uint32_t flash_connection : 4; /* Flash connection option: 0 - Single Flash connected to port A */ } B; uint32_t U; } option1; @@ -165,12 +161,12 @@ typedef struct /* Root pointer */ typedef struct { - const uint32_t version; //!< Bootloader version number - const char *copyright; //!< Bootloader Copyright - void (*runBootloader)(void *arg); //!< Function to start the bootloader executing - const uint32_t *reserved0; //!< Reserved - const flexspi_nor_driver_interface_t *flexSpiNorDriver; //!< FlexSPI NOR Flash API - const uint32_t *reserved1; //!< Reserved + const uint32_t version; /* Bootloader version number */ + const char *copyright; /* Bootloader Copyright */ + void (*runBootloader)(void *arg); /* Function to start the bootloader executing */ + const uint32_t *reserved0; /* Reserved */ + const flexspi_nor_driver_interface_t *flexSpiNorDriver; /* FlexSPI NOR Flash API */ + const uint32_t *reserved1; /* Reserved */ const rtwdog_driver_interface_t *rtwdogDriver; const wdog_driver_interface_t *wdogDriver; const uint32_t *reserved2; @@ -181,7 +177,13 @@ flexspi_nor_config_t flexspi_config; /** Flash configuration in the .flash_config section of flash **/ - +#ifdef CPU_MIMXRT1062DVL6A + #define CONFIG_FLASH_SIZE (8 * 1024 * 1024) /* 8MBytes */ + #define CONFIG_FLASH_PAGE_SIZE 256UL /* 256Bytes */ + #define CONFIG_FLASH_SECTOR_SIZE (4 * 1024) /* 4KBytes */ + #define CONFIG_FLASH_BLOCK_SIZE (64 * 1024) /* 64KBytes */ + #define CONFIG_FLASH_UNIFORM_BLOCKSIZE false + #define CONFIG_SERIAL_CLK_FREQ kFlexSpiSerialClk_100MHz const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_config = { .memConfig = { @@ -191,27 +193,66 @@ const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_c .csHoldTime = 3u, .csSetupTime = 3u, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, + .serialClkFreq = CONFIG_SERIAL_CLK_FREQ, + .sflashA1Size = CONFIG_FLASH_SIZE, .lookupTable = { - // Read LUTs FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, + .pageSize = CONFIG_FLASH_PAGE_SIZE, + .sectorSize = CONFIG_FLASH_SECTOR_SIZE, + .blockSize = CONFIG_FLASH_BLOCK_SIZE, + .isUniformBlockSize = CONFIG_FLASH_UNIFORM_BLOCKSIZE, +}; +#endif + + +#ifdef CPU_MIMXRT1052DVJ6B + #define CONFIG_FLASH_SIZE (64 * 1024 * 1024) /* 64MBytes */ + #define CONFIG_FLASH_PAGE_SIZE 512UL /* 512Bytes */ + #define CONFIG_FLASH_SECTOR_SIZE (256 * 1024) /* 256KBytes */ + #define CONFIG_FLASH_BLOCK_SIZE (256 * 1024) /* 256KBytes */ + #define CONFIG_FLASH_UNIFORM_BLOCKSIZE true + #define CONFIG_SERIAL_CLK_FREQ kFlexSpiSerialClk_30MHz +const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = + { + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, }; +#endif + + #ifndef __FLASH_BASE # define __FLASH_BASE 0x60000000 #endif #ifndef FLASH_BASE #define FLASH_BASE __FLASH_BASE -#define FLASH_SIZE 0x800000 #define PLUGIN_FLAG 0x0UL #endif @@ -221,7 +262,7 @@ extern void isr_reset(void); const BOOT_DATA_T __attribute__((section(".boot_data"))) boot_data = { FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ + CONFIG_FLASH_SIZE, /* size */ PLUGIN_FLAG, /* Plugin flag*/ 0xFFFFFFFF /* empty - extra data word */ }; @@ -273,26 +314,26 @@ static void clock_init(void) { if (CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) { - // Configure ARM_PLL + /* Configure ARM_PLL */ CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_BYPASS(1) | CCM_ANALOG_PLL_ARM_ENABLE(1) | CCM_ANALOG_PLL_ARM_DIV_SELECT(24); - // Wait Until clock is locked + /* Wait Until clock is locked */ while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) { } - // Configure PLL_SYS + /* Configure PLL_SYS */ CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; - // Wait Until clock is locked + /* Wait Until clock is locked */ while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) { } - // Configure PFD_528 + /* Configure PFD_528 */ CCM_ANALOG->PFD_528 = CCM_ANALOG_PFD_528_PFD0_FRAC(24) | CCM_ANALOG_PFD_528_PFD1_FRAC(24) | CCM_ANALOG_PFD_528_PFD2_FRAC(19) | CCM_ANALOG_PFD_528_PFD3_FRAC(24); - // Configure USB1_PLL + /* Configure USB1_PLL */ CCM_ANALOG->PLL_USB1 = CCM_ANALOG_PLL_USB1_DIV_SELECT(0) | CCM_ANALOG_PLL_USB1_POWER(1) | CCM_ANALOG_PLL_USB1_ENABLE(1); while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) @@ -300,31 +341,31 @@ static void clock_init(void) } CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; - // Configure PFD_480 + /* Configure PFD_480 */ CCM_ANALOG->PFD_480 = CCM_ANALOG_PFD_480_PFD0_FRAC(35) | CCM_ANALOG_PFD_480_PFD1_FRAC(35) | CCM_ANALOG_PFD_480_PFD2_FRAC(26) | CCM_ANALOG_PFD_480_PFD3_FRAC(15); - // Configure Clock PODF + /* Configure Clock PODF */ CCM->CACRR = CCM_CACRR_ARM_PODF(1); CCM->CBCDR = (CCM->CBCDR & (~(CCM_CBCDR_SEMC_PODF_MASK | CCM_CBCDR_AHB_PODF_MASK | CCM_CBCDR_IPG_PODF_MASK))) | CCM_CBCDR_SEMC_PODF(2) | CCM_CBCDR_AHB_PODF(2) | CCM_CBCDR_IPG_PODF(2); #ifdef CPU_MIMXRT1062DVL6A - // Configure FLEXSPI2 CLOCKS + /* Configure FLEXSPI2 CLOCKS */ CCM->CBCMR = (CCM->CBCMR & (~(CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK | CCM_CBCMR_FLEXSPI2_PODF_MASK))) | CCM_CBCMR_PRE_PERIPH_CLK_SEL(3) | CCM_CBCMR_FLEXSPI2_CLK_SEL(1) | CCM_CBCMR_FLEXSPI2_PODF(7); #endif - // Confgiure FLEXSPI CLOCKS + /* Configure FLEXSPI CLOCKS */ CCM->CSCMR1 = ((CCM->CSCMR1 & ~(CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK | CCM_CSCMR1_PERCLK_PODF_MASK | CCM_CSCMR1_PERCLK_CLK_SEL_MASK)) | CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(7) | CCM_CSCMR1_PERCLK_PODF(1)); - // Finally, Enable PLL_ARM, PLL_SYS and PLL_USB1 + /* Finally, Enable PLL_ARM, PLL_SYS and PLL_USB1 */ CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; @@ -357,8 +398,10 @@ static serial_nor_config_option_t flexspi_cfg_option = {}; static int nor_flash_init(void) { +#ifdef CPU_MIMXRT1062DVL6A flexspi_cfg_option.option0.U = 0xC0000007; /* QuadSPI-NOR, f = default */ g_bootloaderTree->flexSpiNorDriver->get_config(0, &flexspi_config, &flexspi_cfg_option); +#endif g_bootloaderTree->flexSpiNorDriver->init(0, &flexspi_config); return 0; } From bc111ae41cdbdecabfe6016ec88b9c81f1f8d7b5 Mon Sep 17 00:00:00 2001 From: Daniele Lacamera Date: Wed, 27 Apr 2022 14:37:53 +0200 Subject: [PATCH 3/4] Removed duplicate definition section --- hal/imx_rt1060_nor.h | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/hal/imx_rt1060_nor.h b/hal/imx_rt1060_nor.h index a897a1d3e..52b9b1e46 100644 --- a/hal/imx_rt1060_nor.h +++ b/hal/imx_rt1060_nor.h @@ -223,26 +223,6 @@ typedef struct _FlexSPIConfig #define NOR_CMD_INDEX_DUMMY 6 //!< 6 #define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - /* * Serial NOR configuration block */ From 1c9e3fd46d14dbcd5aabf8710ec244fe128e18b9 Mon Sep 17 00:00:00 2001 From: David Garske Date: Wed, 27 Apr 2022 11:15:32 -0700 Subject: [PATCH 4/4] Updated Targets.md with RT1050 information. --- docs/Targets.md | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/docs/Targets.md b/docs/Targets.md index eaec8213e..d6cd7f770 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -972,7 +972,7 @@ the monitor command sequence below: ## NXP iMX-RT -NXP RT1060/1062 (RT1060-EVK) +NXP RT1060/1062 and RT1050 The NXP iMX-RT1060 is a Cortex-M7 with a DCP coprocessor for SHA256 acceleration. Example configuration for this target is provided in [/config/examples/imx-rt1060.config](/config/examples/imx-rt1060.config). @@ -980,14 +980,17 @@ Example configuration for this target is provided in [/config/examples/imx-rt106 ### Building wolfBoot MCUXpresso SDK is required by wolfBoot to access device drivers on this platform. -A package can be obtained from the [MCUXpresso SDK Builder](https://mcuxpresso.nxp.com/en/welcome), by selecting `EVK-MIMXRT1060` as target, and keeping the default choice of components. +A package can be obtained from the [MCUXpresso SDK Builder](https://mcuxpresso.nxp.com/en/welcome), by selecting a target and keeping the default choice of components. -Set the `MCUXPRESSO` configuration variable to the path where the SDK package is extracted, then build wolfBoot normally by running `make`. +* For the RT1060 use `EVKB-IMXRT1060`. See configuration example in `config/examples/imx-rt1060.config`. +* For the RT1050 use `EVKB-IMXRT1050`. See configuration example in `config/examples/imx-rt1050.config`. -wolfBoot support for iMX-RT1060 has been tested using MCUXpresso SDK version 2.8.2. +Set the wolfBoot `MCUXPRESSO` configuration variable to the path where the SDK package is extracted, then build wolfBoot normally by running `make`. + +wolfBoot support for iMX-RT1060/iMX-RT1050 has been tested using MCUXpresso SDK version 2.11.1. DCP support (hardware acceleration for SHA256 operations) can be enabled by using PKA=1 in the configuration file. -Firmware can be directly uploaded to the target by copying `factory.bin` to the virtual USB drive associated to the device (RT1060-EVK). +Firmware can be directly uploaded to the target by copying `factory.bin` to the virtual USB drive associated to the device. ## NXP Kinetis