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Working with original dvb-usb-dw2104.fw? #7

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jonnyh64 opened this issue Sep 27, 2024 · 8 comments
Open

Working with original dvb-usb-dw2104.fw? #7

jonnyh64 opened this issue Sep 27, 2024 · 8 comments

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@jonnyh64
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Does your hardware work with the original dvb-usb-dw2104.fw? From what I can see, the original one uses PA6 for h/v control (instead of PD0 in your schematic). But apart from this, it should work?

@jonnyh64
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I found another difference: The original firmware sets IFCONFIG = 0xcb, where your firmware sets IFCONFIG = 0x03. This means, the original firmware uses asynchronous slave FIFO mode, where your firmware uses synchronous slave mode.

For the wiring, this means:

  • The original firmware needs demod CLKOUT connected to SLWR. I'm also pretty sure that demod SYNC is connected to PA6/PKTEND.
  • Your firmware needs demod CLKOUT connected to IFCLK. I'm surprised that SYNC is not connected?!

In your schematic, demod Data_Valid is connected to SLWR, so that IFCLK is ignored while SLWR is inactive. I'm not quite sure how the original firmware handles this. Maybe the demod does not use Data_Valid at all - it can just stop CLKOUT when no data is being transmitted, but this might be configurable. But maybe it needs demod Data_Valid connected to SLCS, which would then require a certain output polarity on demod side, because it is not configurable on the FX2 side.

@xenpac
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xenpac commented Sep 29, 2024

Oh hi jonny,
we have an expert here ;)

I am a bit away from the details.
Yes SYNC is not connected for some reason. i have to look into the demod datasheet.
so i only fetch the data from demod when data_valid is on.
It toggle between the packets.

In asynchronous mode (IFCONFIG.3 = 1), SLRD and SLWR
are read and write strobes; in synchronous mode
(IFCONFIG.3 = 0), SLRD and SLWR are enables for the
IFCLK clock pin.

So i use data_valid to let the clock input the data if active.

PORTA alternate Pin configurations is activated when IFCONFIG = 0x03; enabling slave fifo mode.
ifconfig 0xcb is bin 1100 1011, so async mode, IFCLKSRC, 3048MHZ , 0,0, ASYNC ,0, IFCFG1 ,IFCFG0
maybe 3048MHZ should be 1 for 48mhz fifo clock.

i dont have the original hardware so i dont know if my firmware works on it. i guess not.
But you can adjust the software and check.

you seem to have the original sourcecode. ?

@jonnyh64
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I don't have the original source code, just a disassembly, and the 8051 code is relatively easy to read. Actually I'm designing my own DVB device PCB (also with the FX2 chip), so I'm using any opportunity to study the details, hoping to limit the number of bodge wires necessary. Also I hope that I can reuse some existing FX2 firmware - because getting all the details right seems like a nightmare, and sharing a self-written firmware binary based on the Cypress libraries seems legally questionable.

I've digged a little more and can see that the original dvb-usb-dw2104.fw sets PORTACFG = 0, i.e. the SLCS pin function is disabled (even though the CX24116 would allow to adjust the Data_Valid polarity via MPEGConfig/MPGValidPol register to match what the FX2 expects).

So, my interpretation is that on the original hardware, Data_Valid is not used and that the demod only generates CLKOUT edges when there is valid data transmitted. The CX24116 allows that by setting the MPEGConfig/MPGClkGap register to 1. The weird thing is that the linux driver (drivers/media/dvb-frontends/cx24116.c, search for CMD_MPEGCONFIG) does NOT set this bit.

As you are confirming that you observed data_valid actually toggling, I have no clue how Linux driver can work with the original firmware and hardware...

@jonnyh64
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jonnyh64 commented Sep 29, 2024

Maybe I have found the explanation how it works. The Linux driver sets the MPEGConfig/MPEGSyncPunc bit to 1, which enables "Sync word is punctured" behavior. I admit that I never heard the term "puncture" in context of a digital signal, but I'm guessing that this means that the demod SYNC signal is pulled low when the 188-byte TS packet ends (and the high-low edge triggers sending the packet via USB) and then also KEPT low while the error detection/correction bytes are sent. While I find no clear evidence in the FX2 TRM, I'm assuming that keeping PKTEND low also leads to SLWR edges being ignored.

I will base my PCB on that assumption, but also keep all other pins routed to pin headers, just in case.

Not sure if you are still working on the project, but maybe this helps you to also switch to the original firmware and frees you from the burden of maintaining your own.

@jonnyh64
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Thinking some more, I guess demod data_valid is simply connected to FX2 PKTEND. This could make it compatible also to other demods.

@xenpac
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xenpac commented Sep 29, 2024

Ok, so you are disassembling the original firmware file to evaluate how it works.
and you are designing your own PCB for a ? sat receiver, based on the same Tuner/NIM ? or something else?
yes the FX2 cypress device is quite versatile and can interface various hardware via USB to PC.
I like FX2,

@jonnyh64
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jonnyh64 commented Sep 29, 2024

My primary goal of the disassembly is to make a hardware which is compatible with the existing firmware.

It will be based on a different NIM (with Montage tuner & demod). I will probably publish it under an open hardware license, so everybody can adapt it to other NIMs. As DVB usage seems to be declining more and more it might be an opportunity to recycle old hardware. Together with a Raspberry Pi it makes a nice STB - this would have been a popular device in the 2000s and early 2010s, but nowadays I guess not many people will be interested. So now it mainly serves for my self-education with PCB design and switching power supplies and linear voltage regulators...

@xenpac
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xenpac commented Sep 30, 2024

yeah DVB usage is declining.
Internet streaming is the THING.
someday the Sat-Dishes may disappear.
This here is just a Hobby.

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