From 1d033caf9fbd9bbb5028139d7fe81104753e1cf7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 9 Jun 2017 10:20:38 -0500 Subject: [PATCH 01/29] arm: Add build time consistency check for irq priority defines We need to make sure that __NVIC_PRIO_BITS & CONFIG_NUM_IRQ_PRIO_BITS are set to the same value. Add a simple build time check to ensure this is the case. This is to catch future cases of issues like ZEP-2243. This is a stop gap til we resolve ZEP-2262, which covers use of both __NVIC_PRIO_BITS & CONFIG_NUM_IRQ_PRIO_BITS. Signed-off-by: Kumar Gala --- include/arch/arm/cortex_m/cmsis.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/arch/arm/cortex_m/cmsis.h b/include/arch/arm/cortex_m/cmsis.h index f42b94c7e7492e..aad213b9451fb2 100644 --- a/include/arch/arm/cortex_m/cmsis.h +++ b/include/arch/arm/cortex_m/cmsis.h @@ -124,6 +124,10 @@ typedef enum { #define __Vendor_SysTickConfig 0 /* Default to standard SysTick */ #endif /* __NVIC_PRIO_BITS */ +#if __NVIC_PRIO_BITS != CONFIG_NUM_IRQ_PRIO_BITS +#error "CONFIG_NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value" +#endif + #if defined(CONFIG_CPU_CORTEX_M0) #include #elif defined(CONFIG_CPU_CORTEX_M0PLUS) From d9d46d3f3e1feaecc90dc51b954059ee647faf38 Mon Sep 17 00:00:00 2001 From: Shiksha Patel Date: Sun, 4 Jun 2017 08:21:42 -0500 Subject: [PATCH 02/29] pinmux: pinmux_dev_k64 driver and related references are removed. Functionality of a pinmux driver is now a part of a regular driver. Signed-off-by: Shiksha Patel --- drivers/pinmux/dev/Kconfig | 7 ----- drivers/pinmux/dev/Makefile | 3 -- drivers/pinmux/dev/pinmux_dev_k64.c | 49 ----------------------------- 3 files changed, 59 deletions(-) delete mode 100644 drivers/pinmux/dev/pinmux_dev_k64.c diff --git a/drivers/pinmux/dev/Kconfig b/drivers/pinmux/dev/Kconfig index 87a93cb9db9f42..b4fdab5e105b75 100644 --- a/drivers/pinmux/dev/Kconfig +++ b/drivers/pinmux/dev/Kconfig @@ -30,13 +30,6 @@ config PINMUX_DEV_ATMEL_SAM3X Atmel SAM3X family of microcontrollers. default n -config PINMUX_DEV_K64 - bool "Enable the pinmux dev driver for Freescale K64" - depends on PINMUX_DEV && SOC_MK64F12 - help - Enables the pinmux dev driver for Freescale K64. - default n - config PINMUX_DEV_STM32 bool "Enable pinmux dev driver for the ST STM32 family." depends on PINMUX_DEV && SOC_FAMILY_STM32 diff --git a/drivers/pinmux/dev/Makefile b/drivers/pinmux/dev/Makefile index 4f9d1f1c8ecc6e..ae7cd83174717f 100644 --- a/drivers/pinmux/dev/Makefile +++ b/drivers/pinmux/dev/Makefile @@ -1,7 +1,4 @@ ccflags-$(CONFIG_PINMUX_DEV) +=-I$(srctree)/drivers -ccflags-$(CONFIG_PINMUX_DEV_K64) +=-I$(srctree)/drivers/pinmux/k64/ - obj-$(CONFIG_PINMUX_DEV_ATMEL_SAM3X) += pinmux_dev_atmel_sam3x.o -obj-$(CONFIG_PINMUX_DEV_K64) += pinmux_dev_k64.o obj-$(CONFIG_PINMUX_DEV_STM32) += pinmux_dev_stm32.o obj-$(CONFIG_PINMUX_DEV_ARM_V2M_BEETLE) += pinmux_dev_arm_beetle.o diff --git a/drivers/pinmux/dev/pinmux_dev_k64.c b/drivers/pinmux/dev/pinmux_dev_k64.c deleted file mode 100644 index a6aece17f1c3a6..00000000000000 --- a/drivers/pinmux/dev/pinmux_dev_k64.c +++ /dev/null @@ -1,49 +0,0 @@ -/* pinmux_dev_k64.c - Pinmux dev driver for Freescale K64 */ - -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include - -static int fsl_k64_dev_set(struct device *dev, u32_t pin, - u32_t func) -{ - ARG_UNUSED(dev); - - return _fsl_k64_set_pin(pin, func); -} - -static int fsl_k64_dev_get(struct device *dev, u32_t pin, - u32_t *func) -{ - ARG_UNUSED(dev); - - return _fsl_k64_get_pin(pin, func); -} - -static const struct pinmux_driver_api api_funcs = { - .set = fsl_k64_dev_set, - .get = fsl_k64_dev_get -}; - -int pinmux_fsl_k64_initialize(struct device *port) -{ - ARG_UNUSED(port); - - return 0; -} - -/* must be initialized after GPIO */ -DEVICE_AND_API_INIT(pmux, CONFIG_PINMUX_DEV_NAME, &pinmux_fsl_k64_initialize, - NULL, NULL, - POST_KERNEL, CONFIG_PINMUX_INIT_PRIORITY, - &api_funcs); From 446ad9f930b57352fd44f0a0114ad2fedeafae5d Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 13 Jun 2017 16:08:09 -0500 Subject: [PATCH 03/29] arm: nxp: mpu: Fix region descriptor 0 attributes Clearing fields in the region descriptor attributes doesn't always have the expected effect of revoking permissions. In the case of bus master supervisor mode fields (MxSM), setting to zero actually enables read, write, and execute access. When we reworked handling of region descriptor 0, we inadvertently enabled execution from RAM by clearing the MxSM fields and enabling the descriptor. This caused samples/mpu_test run to throw a usage fault instead of an MPU-triggered bus fault. Fix this by setting all the MxSM fields to 2'b11, which gives supervisor mode the same access as user mode. Signed-off-by: Maureen Helm --- arch/arm/soc/nxp_kinetis/k6x/nxp_mpu_regions.c | 2 +- include/arch/arm/cortex_m/mpu/nxp_mpu.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/soc/nxp_kinetis/k6x/nxp_mpu_regions.c b/arch/arm/soc/nxp_kinetis/k6x/nxp_mpu_regions.c index 734b17b986624b..16245d767700b7 100644 --- a/arch/arm/soc/nxp_kinetis/k6x/nxp_mpu_regions.c +++ b/arch/arm/soc/nxp_kinetis/k6x/nxp_mpu_regions.c @@ -15,7 +15,7 @@ static struct nxp_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("DEBUGGER_0", 0, 0xFFFFFFFF, - 0), + REGION_DEBUG_ATTR), /* Region 1 */ MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS, diff --git a/include/arch/arm/cortex_m/mpu/nxp_mpu.h b/include/arch/arm/cortex_m/mpu/nxp_mpu.h index b451d8793856a0..a4cb3895f5bcc1 100644 --- a/include/arch/arm/cortex_m/mpu/nxp_mpu.h +++ b/include/arch/arm/cortex_m/mpu/nxp_mpu.h @@ -78,6 +78,9 @@ #define REGION_RO_ATTR (MPU_REGION_READ | \ MPU_REGION_SU) +#define REGION_DEBUG_ATTR MPU_REGION_SU + + /* Region definition data structure */ struct nxp_mpu_region { /* Region Base Address */ From 443466f6d8cf244f02cb2935a8538d55a42d6911 Mon Sep 17 00:00:00 2001 From: Piotr Mienkowski Date: Wed, 14 Jun 2017 22:48:31 +0200 Subject: [PATCH 04/29] arch: same70: Fix ERASE pin configuration Correct code that allows to disable ERASE pin functionality during boot. Signed-off-by: Piotr Mienkowski --- arch/arm/soc/atmel_sam/same70/soc_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/soc/atmel_sam/same70/soc_config.c b/arch/arm/soc/atmel_sam/same70/soc_config.c index f9a5e7730dfc81..f6c3fe7af8381d 100644 --- a/arch/arm/soc/atmel_sam/same70/soc_config.c +++ b/arch/arm/soc/atmel_sam/same70/soc_config.c @@ -22,7 +22,7 @@ */ static int atmel_same70_config(struct device *dev) { -#ifdef SOC_ATMEL_SAME70_DISABLE_ERASE_PIN +#ifdef CONFIG_SOC_ATMEL_SAME70_DISABLE_ERASE_PIN /* Disable ERASE function on PB12 pin, this is controlled by Bus Matrix */ MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; #endif From f73bf35d6718aa228cad06e53c9e4bcdc20b120c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Geoffrey=20Le=20Gourri=C3=A9rec?= Date: Thu, 15 Jun 2017 14:05:45 +0200 Subject: [PATCH 05/29] arm: Modify linker script to accomodate need for flash footer. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The porting of the TI CC2650 SoC introduces the need to write a specific configuration area (CCFG) at the end of the flash. It is read by the bootloader ROM of the SoC. For now, this is a quick hack and not a generic solution; similar needs may arise with other hardware. Signed-off-by: Geoffrey Le Gourriérec --- include/arch/arm/cortex_m/scripts/linker.ld | 18 ++++++++++++++++++ include/section_tags.h | 1 + include/sections.h | 1 + 3 files changed, 20 insertions(+) diff --git a/include/arch/arm/cortex_m/scripts/linker.ld b/include/arch/arm/cortex_m/scripts/linker.ld index 04f39a8a7d71ef..33eb57bda9d4cb 100644 --- a/include/arch/arm/cortex_m/scripts/linker.ld +++ b/include/arch/arm/cortex_m/scripts/linker.ld @@ -41,11 +41,18 @@ #endif #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET) +#ifdef CONFIG_TI_CCFG_PRESENT + #define CCFG_SIZE 88 + #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \ + CCFG_SIZE) + #define CCFG_ADDR (ROM_ADDR + ROM_SIZE) +#else #if CONFIG_FLASH_LOAD_SIZE > 0 #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE #else #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET) #endif +#endif #if defined(CONFIG_XIP) #if defined(CONFIG_IS_BOOTLOADER) @@ -64,6 +71,9 @@ MEMORY { FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE +#ifdef CONFIG_TI_CCFG_PRESENT + FLASH_CCFG (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE +#endif SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE /* Used by and documented in include/linker/intlist.ld */ @@ -156,6 +166,14 @@ SECTIONS GROUP_END(ROMABLE_REGION) +/* Some TI SoCs have a special configuration footer, at the end of flash. */ +#ifdef CONFIG_TI_CCFG_PRESENT + SECTION_PROLOGUE(.ti_ccfg,,) + { + KEEP(*(TI_CCFG)) + } > FLASH_CCFG +#endif + GROUP_START(RAMABLE_REGION) SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) diff --git a/include/section_tags.h b/include/section_tags.h index ce6853cde40aca..af548afe602d3a 100644 --- a/include/section_tags.h +++ b/include/section_tags.h @@ -19,6 +19,7 @@ #if defined(CONFIG_ARM) #define __kinetis_flash_config_section __in_section_unique(KINETIS_FLASH_CONFIG) +#define __ti_ccfg_section _GENERIC_SECTION(TI_CCFG) #endif /* CONFIG_ARM */ #endif /* !_ASMLANGUAGE */ diff --git a/include/sections.h b/include/sections.h index da5ec1ffe5d51d..2f78d74f22a67a 100644 --- a/include/sections.h +++ b/include/sections.h @@ -46,6 +46,7 @@ /* Architecture-specific sections */ #if defined(CONFIG_ARM) #define KINETIS_FLASH_CONFIG kinetis_flash_config +#define TI_CCFG .ti_ccfg #endif #include From 9fd57b4e59135dbe68678341ba9d681c0bc3c445 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Geoffrey=20Le=20Gourri=C3=A9rec?= Date: Thu, 15 Jun 2017 14:06:05 +0200 Subject: [PATCH 06/29] drivers: serial: uart_stellaris: Remove UART_IRQ_FLAGS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We always have UART_IRQ_FLAGS set to 0, so just call IRQ_CONNECT with a 0 argument for the flags, and remove the UART_IRQ_FLAGS. This is towards support for using the driver on the TI CC2650. (we add a comment about that as well). Signed-off-by: Geoffrey Le Gourriérec Signed-off-by: Kumar Gala --- arch/arm/soc/ti_lm3s6965/soc.h | 2 -- drivers/serial/uart_stellaris.c | 8 +++++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/soc/ti_lm3s6965/soc.h b/arch/arm/soc/ti_lm3s6965/soc.h index 56509edf261bae..6fa04cc2d33b6b 100644 --- a/arch/arm/soc/ti_lm3s6965/soc.h +++ b/arch/arm/soc/ti_lm3s6965/soc.h @@ -78,8 +78,6 @@ extern "C" { /* uart configuration settings */ #if defined(CONFIG_UART_STELLARIS) -#define UART_IRQ_FLAGS 0 - #define UART_STELLARIS_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ #endif /* CONFIG_UART_STELLARIS */ diff --git a/drivers/serial/uart_stellaris.c b/drivers/serial/uart_stellaris.c index a95a87a255b434..b697f10b110129 100644 --- a/drivers/serial/uart_stellaris.c +++ b/drivers/serial/uart_stellaris.c @@ -11,6 +11,8 @@ * * Driver for Stellaris UART found namely on TI LM3S6965 board. It is similar to * an 16550 in functionality, but is not register-compatible. + * It is also register-compatible with the UART found on TI CC2650 SoC, + * so it can be used for boards using it, like the TI SensorTag. * * There is only support for poll-mode, so it can only be used with the printk * and STDOUT_CONSOLE APIs. @@ -653,7 +655,7 @@ static void irq_config_func_0(struct device *dev) IRQ_CONNECT(TI_STELLARIS_UART_4000C000_IRQ_0, TI_STELLARIS_UART_4000C000_IRQ_0_PRIORITY, uart_stellaris_isr, DEVICE_GET(uart_stellaris0), - UART_IRQ_FLAGS); + 0); irq_enable(TI_STELLARIS_UART_4000C000_IRQ_0); } #endif @@ -690,7 +692,7 @@ static void irq_config_func_1(struct device *dev) IRQ_CONNECT(TI_STELLARIS_UART_4000D000_IRQ_0, TI_STELLARIS_UART_4000D000_IRQ_0_PRIORITY, uart_stellaris_isr, DEVICE_GET(uart_stellaris1), - UART_IRQ_FLAGS); + 0); irq_enable(TI_STELLARIS_UART_4000D000_IRQ_0); } #endif @@ -727,7 +729,7 @@ static void irq_config_func_2(struct device *dev) IRQ_CONNECT(TI_STELLARIS_UART_4000E000_IRQ_0, TI_STELLARIS_UART_4000E000_IRQ_0_PRIORITY, uart_stellaris_isr, DEVICE_GET(uart_stellaris2), - UART_IRQ_FLAGS); + 0); irq_enable(TI_STELLARIS_UART_4000E000_IRQ_0); } #endif From 93da617ba2112335cdeaf1168f3fccf2af0a82fe Mon Sep 17 00:00:00 2001 From: Michel Jaouen Date: Tue, 6 Jun 2017 10:34:52 +0200 Subject: [PATCH 07/29] flash: stm32: fix for l4 writing wrong data L4 have 64 bits write access. The cast to 64 bits data address in write_dword requires 3 right shifts on i (byte index) else the data taken are wrong for i different from 0 Signed-off-by: Michel Jaouen --- drivers/flash/flash_stm32l4x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/flash/flash_stm32l4x.c b/drivers/flash/flash_stm32l4x.c index 48a5834f055247..45141b2be5fd3c 100644 --- a/drivers/flash/flash_stm32l4x.c +++ b/drivers/flash/flash_stm32l4x.c @@ -142,7 +142,7 @@ int flash_stm32_write_range(unsigned int offset, const void *data, int i, rc = 0; for (i = 0; i < len; i += 8, offset += 8) { - rc = write_dword(offset, ((const u64_t *) data)[i], p); + rc = write_dword(offset, ((const u64_t *) data)[i>>3], p); if (rc < 0) { return rc; } From ba4def2e70192dd0a1034d883e7a4fd95c92650a Mon Sep 17 00:00:00 2001 From: Michel Jaouen Date: Wed, 14 Jun 2017 12:49:33 +0200 Subject: [PATCH 08/29] flash: stm32: distinguish read/write for flash range valid L4 write access requires 64 bits alignment while L4 read access does not require any alignment. To support specific check according to read/write,erase a parameter is added to stm32_valid_range. Signed-off-by: Michel Jaouen --- drivers/flash/flash_stm32.c | 6 +++--- drivers/flash/flash_stm32.h | 2 +- drivers/flash/flash_stm32f4x.c | 3 ++- drivers/flash/flash_stm32l4x.c | 12 ++++++------ 4 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/flash/flash_stm32.c b/drivers/flash/flash_stm32.c index 12db619bdee0d5..a7171769a1d532 100644 --- a/drivers/flash/flash_stm32.c +++ b/drivers/flash/flash_stm32.c @@ -95,7 +95,7 @@ void flash_stm32_flush_caches(struct flash_stm32_priv *p) static int flash_stm32_read(struct device *dev, off_t offset, void *data, size_t len) { - if (!flash_stm32_valid_range(offset, len)) { + if (!flash_stm32_valid_range(offset, len, false)) { return -EINVAL; } @@ -113,7 +113,7 @@ int flash_stm32_erase(struct device *dev, off_t offset, size_t len) struct flash_stm32_priv *p = dev->driver_data; int rc; - if (!flash_stm32_valid_range(offset, len)) { + if (!flash_stm32_valid_range(offset, len, true)) { return -EINVAL; } @@ -138,7 +138,7 @@ int flash_stm32_write(struct device *dev, off_t offset, struct flash_stm32_priv *p = dev->driver_data; int rc; - if (!flash_stm32_valid_range(offset, len)) { + if (!flash_stm32_valid_range(offset, len, true)) { return -EINVAL; } diff --git a/drivers/flash/flash_stm32.h b/drivers/flash/flash_stm32.h index 2b8bf90cf39423..9566424969cf1b 100644 --- a/drivers/flash/flash_stm32.h +++ b/drivers/flash/flash_stm32.h @@ -30,7 +30,7 @@ struct flash_stm32_priv { struct k_sem sem; }; -bool flash_stm32_valid_range(off_t offset, u32_t len); +bool flash_stm32_valid_range(off_t offset, u32_t len, bool write); int flash_stm32_write_range(unsigned int offset, const void *data, unsigned int len, struct flash_stm32_priv *p); diff --git a/drivers/flash/flash_stm32f4x.c b/drivers/flash/flash_stm32f4x.c index e3b361dbbeb9dd..36c3152c02e74d 100644 --- a/drivers/flash/flash_stm32f4x.c +++ b/drivers/flash/flash_stm32f4x.c @@ -13,8 +13,9 @@ #include -bool flash_stm32_valid_range(off_t offset, u32_t len) +bool flash_stm32_valid_range(off_t offset, u32_t len, bool write) { + ARG_UNUSED(write); return offset >= 0 && (offset + len - 1 <= STM32F4X_FLASH_END); } diff --git a/drivers/flash/flash_stm32l4x.c b/drivers/flash/flash_stm32l4x.c index 45141b2be5fd3c..feddaccaa7b982 100644 --- a/drivers/flash/flash_stm32l4x.c +++ b/drivers/flash/flash_stm32l4x.c @@ -20,13 +20,13 @@ #define STM32L4X_FLASH_END \ ((u32_t)(STM32L4X_BANK_SIZE_MAX << STM32L4X_PAGE_SHIFT) - 1) -/* offset and len must be aligned on 8, positive and not beyond end of flash */ -bool flash_stm32_valid_range(off_t offset, u32_t len) +/* offset and len must be aligned on 8 for write + * , positive and not beyond end of flash */ +bool flash_stm32_valid_range(off_t offset, u32_t len, bool write) { - return offset % 8 == 0 && - len % 8 == 0 && - offset >= 0 && - (offset + len - 1 <= STM32L4X_FLASH_END); + return (!write || (offset % 8 == 0 && len % 8 == 0)) && + offset >= 0 && + (offset + len - 1 <= STM32L4X_FLASH_END); } /* STM32L4xx devices can have up to 512 2K pages on two 256x2K pages banks */ From a2dae79bcbcb734cad4030172ccaa31756f4ee9e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Geoffrey=20Le=20Gourri=C3=A9rec?= Date: Fri, 16 Jun 2017 17:42:01 +0200 Subject: [PATCH 09/29] uart: Use DTS labels for Stellaris driver. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update driver to use DTS-generated #defines for port names, and not obsolete Kconfig variables. Signed-off-by: Geoffrey Le Gourriérec --- drivers/serial/uart_stellaris.c | 9 ++++++--- dts/arm/qemu_cortex_m3.fixup | 3 --- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/serial/uart_stellaris.c b/drivers/serial/uart_stellaris.c index b697f10b110129..d359efe0a2b587 100644 --- a/drivers/serial/uart_stellaris.c +++ b/drivers/serial/uart_stellaris.c @@ -644,7 +644,8 @@ static struct uart_stellaris_dev_data_t uart_stellaris_dev_data_0 = { .baud_rate = TI_STELLARIS_UART_4000C000_CURRENT_SPEED, }; -DEVICE_AND_API_INIT(uart_stellaris0, CONFIG_UART_STELLARIS_PORT_0_NAME, &uart_stellaris_init, +DEVICE_AND_API_INIT(uart_stellaris0, TI_STELLARIS_UART_4000C000_LABEL, + &uart_stellaris_init, &uart_stellaris_dev_data_0, &uart_stellaris_dev_cfg_0, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_stellaris_driver_api); @@ -681,7 +682,8 @@ static struct uart_stellaris_dev_data_t uart_stellaris_dev_data_1 = { .baud_rate = TI_STELLARIS_UART_4000D000_CURRENT_SPEED, }; -DEVICE_AND_API_INIT(uart_stellaris1, CONFIG_UART_STELLARIS_PORT_1_NAME, &uart_stellaris_init, +DEVICE_AND_API_INIT(uart_stellaris1, TI_STELLARIS_UART_4000D000_LABEL, + &uart_stellaris_init, &uart_stellaris_dev_data_1, &uart_stellaris_dev_cfg_1, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_stellaris_driver_api); @@ -718,7 +720,8 @@ static struct uart_stellaris_dev_data_t uart_stellaris_dev_data_2 = { .baud_rate = TI_STELLARIS_UART_4000E000_CURRENT_SPEED, }; -DEVICE_AND_API_INIT(uart_stellaris2, CONFIG_UART_STELLARIS_PORT_2_NAME, &uart_stellaris_init, +DEVICE_AND_API_INIT(uart_stellaris2, TI_STELLARIS_UART_4000E000_LABEL, + &uart_stellaris_init, &uart_stellaris_dev_data_2, &uart_stellaris_dev_cfg_2, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_stellaris_driver_api); diff --git a/dts/arm/qemu_cortex_m3.fixup b/dts/arm/qemu_cortex_m3.fixup index 20975620edb9ef..af1312e9de4ed3 100644 --- a/dts/arm/qemu_cortex_m3.fixup +++ b/dts/arm/qemu_cortex_m3.fixup @@ -1,4 +1 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_STELLARIS_PORT_0_NAME TI_STELLARIS_UART_4000C000_LABEL -#define CONFIG_UART_STELLARIS_PORT_1_NAME TI_STELLARIS_UART_4000D000_LABEL -#define CONFIG_UART_STELLARIS_PORT_2_NAME TI_STELLARIS_UART_4000E000_LABEL From 96280c8f1c485257c4ff14fa4fdd474551bce5d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Geoffrey=20Le=20Gourri=C3=A9rec?= Date: Fri, 16 Jun 2017 17:42:03 +0200 Subject: [PATCH 10/29] arm: Add support for TI's CC2650 SoC. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support in arch/arm/soc/ti_simplelink, along with support for CC32xx SoC. Signed-off-by: Geoffrey Le Gourriérec --- .../cc2650/Kconfig.defconfig.series | 17 + .../soc/ti_simplelink/cc2650/Kconfig.series | 13 + arch/arm/soc/ti_simplelink/cc2650/Kconfig.soc | 21 + arch/arm/soc/ti_simplelink/cc2650/Makefile | 3 + .../soc/ti_simplelink/cc2650/include/ccfg.h | 749 ++++++++++++++++++ .../soc/ti_simplelink/cc2650/include/gpio.h | 658 +++++++++++++++ .../soc/ti_simplelink/cc2650/include/ioc.h | 270 +++++++ .../soc/ti_simplelink/cc2650/include/prcm.h | 108 +++ arch/arm/soc/ti_simplelink/cc2650/linker.ld | 7 + arch/arm/soc/ti_simplelink/cc2650/soc.c | 146 ++++ arch/arm/soc/ti_simplelink/cc2650/soc.h | 25 + dts/arm/ti/cc2650.dtsi | 66 ++ dts/arm/yaml/ti,cc2650-prcm.yaml | 22 + 13 files changed, 2105 insertions(+) create mode 100644 arch/arm/soc/ti_simplelink/cc2650/Kconfig.defconfig.series create mode 100644 arch/arm/soc/ti_simplelink/cc2650/Kconfig.series create mode 100644 arch/arm/soc/ti_simplelink/cc2650/Kconfig.soc create mode 100644 arch/arm/soc/ti_simplelink/cc2650/Makefile create mode 100644 arch/arm/soc/ti_simplelink/cc2650/include/ccfg.h create mode 100644 arch/arm/soc/ti_simplelink/cc2650/include/gpio.h create mode 100644 arch/arm/soc/ti_simplelink/cc2650/include/ioc.h create mode 100644 arch/arm/soc/ti_simplelink/cc2650/include/prcm.h create mode 100644 arch/arm/soc/ti_simplelink/cc2650/linker.ld create mode 100644 arch/arm/soc/ti_simplelink/cc2650/soc.c create mode 100644 arch/arm/soc/ti_simplelink/cc2650/soc.h create mode 100644 dts/arm/ti/cc2650.dtsi create mode 100644 dts/arm/yaml/ti,cc2650-prcm.yaml diff --git a/arch/arm/soc/ti_simplelink/cc2650/Kconfig.defconfig.series b/arch/arm/soc/ti_simplelink/cc2650/Kconfig.defconfig.series new file mode 100644 index 00000000000000..485da1097e5730 --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/Kconfig.defconfig.series @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Kconfig.defconfig.series - TI SimpleLink CC2650 +# + +if SOC_SERIES_CC2650 + +config SOC_SERIES + default cc2650 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 48000000 + +config NUM_IRQS + default 34 + +endif # SOC_SERIES_CC2650 diff --git a/arch/arm/soc/ti_simplelink/cc2650/Kconfig.series b/arch/arm/soc/ti_simplelink/cc2650/Kconfig.series new file mode 100644 index 00000000000000..65e54b77d068cf --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/Kconfig.series @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Kconfig.series - TI SimpleLink CC2650 +# + +config SOC_SERIES_CC2650 + bool "TI SimpleLink Family CC2650" + select CPU_CORTEX_M + select CPU_CORTEX_M3 + select SOC_FAMILY_TISIMPLELINK + select CPU_HAS_SYSTICK + help + Enable support for TI SimpleLink CC2650. diff --git a/arch/arm/soc/ti_simplelink/cc2650/Kconfig.soc b/arch/arm/soc/ti_simplelink/cc2650/Kconfig.soc new file mode 100644 index 00000000000000..39ca0a8de09f29 --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/Kconfig.soc @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Kconfig.soc - Texas Instruments CC2650 +# + +choice +prompt "TI SimpleLink MCU Selection" +depends on SOC_SERIES_CC2650 + +config SOC_CC2650 + bool "CC2650" + +endchoice + +if SOC_SERIES_CC2650 + +config TI_CCFG_PRESENT + bool + default y + +endif # SOC_SERIES_CC2650 diff --git a/arch/arm/soc/ti_simplelink/cc2650/Makefile b/arch/arm/soc/ti_simplelink/cc2650/Makefile new file mode 100644 index 00000000000000..cd0443f999911e --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +obj-y += soc.o diff --git a/arch/arm/soc/ti_simplelink/cc2650/include/ccfg.h b/arch/arm/soc/ti_simplelink/cc2650/include/ccfg.h new file mode 100644 index 00000000000000..faf7777b0e71c8 --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/include/ccfg.h @@ -0,0 +1,749 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * CCFG (User configuration area) interface registers and bit offsets + * for the CC2650 System on Chip. + */ + + +#ifndef _CC2650_CCFG_H_ +#define _CC2650_CCFG_H_ + +/* Registers */ + +enum CC2650_CCFG_Registers { + CC2650_CCFG_EXT_LF_CLK = 0xFA8, + CC2650_CCFG_MODE_CONF_1 = 0xFAC, + CC2650_CCFG_SIZE_AND_DIS_FLAGS = 0xFB0, + CC2650_CCFG_MODE_CONF = 0xFB4, + CC2650_CCFG_VOLT_LOAD_0 = 0xFB8, + CC2650_CCFG_VOLT_LOAD_1 = 0xFBC, + CC2650_CCFG_RTC_OFFSET = 0xFC0, + CC2650_CCFG_FREQ_OFFSET = 0xFC4, + CC2650_CCFG_IEEE_MAC_0 = 0xFC8, + CC2650_CCFG_IEEE_MAC_1 = 0xFCC, + CC2650_CCFG_IEEE_BLE_0 = 0xFD0, + CC2650_CCFG_IEEE_BLE_1 = 0xFD4, + CC2650_CCFG_BL_CONFIG = 0xFD8, + CC2650_CCFG_ERASE_CONF = 0xFDC, + CC2650_CCFG_CCFG_TI_OPTIONS = 0xFE0, + CC2650_CCFG_CCFG_TAP_DAP_0 = 0xFE4, + CC2650_CCFG_CCFG_TAP_DAP_1 = 0xFE8, + CC2650_CCFG_IMAGE_VALID_CONF = 0xFEC, + CC2650_CCFG_CCFG_PROT_31_0 = 0xFF0, + CC2650_CCFG_CCFG_PROT_63_32 = 0xFF4, + CC2650_CCFG_CCFG_PROT_95_64 = 0xFF8, + CC2650_CCFG_CCFG_PROT_127_96 = 0xFFC +}; + +/* Register-specific bits */ + +/* EXT_LF_CLK */ +enum CC2650_CCFG_EXT_LF_CLK_POS { + CC2650_CCFG_EXT_LF_CLK_RTC_INCREMENT_POS = 0, + CC2650_CCFG_EXT_LF_CLK_DIO_POS = 24 +}; + +enum CC2650_CCFG_EXT_LF_CLK_MASK { + CC2650_CCFG_EXT_LF_CLK_RTC_INCREMENT_MASK = 0x00FFFFFF, + CC2650_CCFG_EXT_LF_CLK_DIO_MASK = 0xFF000000 +}; + +/* MODE_CONF_1 */ +enum CC2650_CCFG_MODE_CONF_1_POS { + CC2650_CCFG_MODE_CONF_1_XOSC_MAX_START_POS = 0, + CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_POS = 8, + CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_POS = 12, + CC2650_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_POS = 16, + CC2650_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_POS = 19, + CC2650_CCFG_MODE_CONF_1_ALT_DCDC_VMIN_POS = 20 +}; + +enum CC2650_CCFG_MODE_CONF_1_MASK { + CC2650_CCFG_MODE_CONF_1_XOSC_MAX_START_MASK = 0x000000FF, + CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_MASK = 0x00000F00, + CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_MASK = 0x0000F000, + CC2650_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_MASK = 0x00070000, + CC2650_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_MASK = 0x00080000, + CC2650_CCFG_MODE_CONF_1_ALT_DCDC_VMIN_MASK = 0x00F00000 +}; + +/* SIZE_AND_DIS_FLAGS */ +enum CC2650_CCFG_SIZE_AND_DIS_FLAGS_POS { + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_POS = 0, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCD_C_SETTING_POS = 1, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_POS = 2, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_POS = 3, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_POS = 4, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_POS = 16 +}; + +enum CC2650_CCFG_SIZE_AND_DIS_FLAGS_MASK { + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_MASK = + 0x00000001, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCD_C_SETTING_MASK = + 0x00000002, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_MASK = + 0x00000004, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_MASK = + 0x00000008, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_MASK = + 0x0000FFF0, + CC2650_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_MASK = + 0xFFFF0000 +}; + +/* MODE_CONF */ +enum CC2650_CCFG_MODE_CONF_POS { + CC2650_CCFG_MODE_CONF_VDDR_CAP_POS = 0, + CC2650_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_POS = 8, + CC2650_CCFG_MODE_CONF_HF_COMP_POS = 16, + CC2650_CCFG_MODE_CONF_XOSC_CAP_MOD_POS = 17, + CC2650_CCFG_MODE_CONF_XOSC_FREQ_POS = 18, + CC2650_CCFG_MODE_CONF_RTC_COMP_POS = 20, + CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_POS = 21, + CC2650_CCFG_MODE_CONF_SCLK_LF_OPTION_POS = 22, + CC2650_CCFG_MODE_CONF_VDDS_BOD_LEVEL_POS = 24, + CC2650_CCFG_MODE_CONF_VDDR_EXT_LOAD_POS = 25, + CC2650_CCFG_MODE_CONF_DCDC_ACTIVE_POS = 26, + CC2650_CCFG_MODE_CONF_DCDC_RECHARGE_POS = 27, + CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_POS = 28 +}; + +enum CC2650_CCFG_MODE_CONF_MASK { + CC2650_CCFG_MODE_CONF_VDDR_CAP_MASK = + 0x000000FF, + CC2650_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_MASK = + 0x0000FF00, + CC2650_CCFG_MODE_CONF_HF_COMP_MASK = + 0x00010000, + CC2650_CCFG_MODE_CONF_XOSC_CAP_MOD_MASK = + 0x00020000, + CC2650_CCFG_MODE_CONF_XOSC_FREQ_MASK = + 0x000C0000, + CC2650_CCFG_MODE_CONF_RTC_COMP_MASK = + 0x00100000, + CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_MASK = + 0x00200000, + CC2650_CCFG_MODE_CONF_SCLK_LF_OPTION_MASK = + 0x00C00000, + CC2650_CCFG_MODE_CONF_VDDS_BOD_LEVEL_MASK = + 0x01000000, + CC2650_CCFG_MODE_CONF_VDDR_EXT_LOAD_MASK = + 0x02000000, + CC2650_CCFG_MODE_CONF_DCDC_ACTIVE_MASK = + 0x04000000, + CC2650_CCFG_MODE_CONF_DCDC_RECHARGE_MASK = + 0x08000000, + CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_MASK = + 0xF0000000 +}; + +/* VOLT_LOAD_0 */ +enum CC2650_CCFG_VOLT_LOAD_0_POS { + CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_POS = 0, + CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_POS = 8, + CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_POS = 16, + CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_POS = 24 +}; + +enum CC2650_CCFG_VOLT_LOAD_0_MASK { + CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_MASK = 0x000000FF, + CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_MASK = 0x0000FF00, + CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_MASK = 0x00FF0000, + CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_MASK = 0xFF000000 +}; + +/* VOLT_LOAD_1 */ +enum CC2650_CCFG_VOLT_LOAD_1_POS { + CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_POS = 0, + CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_POS = 8, + CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_POS = 16, + CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_POS = 24 +}; + +enum CC2650_CCFG_VOLT_LOAD_1_MASK { + CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_MASK = 0x000000FF, + CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_MASK = 0x0000FF00, + CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_MASK = 0x00FF0000, + CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_MASK = 0xFF000000 +}; + +/* RTC_OFFSET */ +enum CC2650_CCFG_RTC_OFFSET_POS { + CC2650_CCFG_RTC_OFFSET_RTC_COMP_P2_POS = 0, + CC2650_CCFG_RTC_OFFSET_RTC_COMP_P1_POS = 8, + CC2650_CCFG_RTC_OFFSET_RTC_COMP_P0_POS = 16 +}; + +enum CC2650_CCFG_RTC_OFFSET_MASK { + CC2650_CCFG_RTC_OFFSET_RTC_COMP_P2_MASK = 0x000000FF, + CC2650_CCFG_RTC_OFFSET_RTC_COMP_P1_MASK = 0x0000FF00, + CC2650_CCFG_RTC_OFFSET_RTC_COMP_P0_MASK = 0xFFFF0000 +}; + +/* FREQ_OFFSET */ +enum CC2650_CCFG_FREQ_OFFSET_POS { + CC2650_CCFG_FREQ_OFFSET_HF_COMP_P2_POS = 0, + CC2650_CCFG_FREQ_OFFSET_HF_COMP_P1_POS = 8, + CC2650_CCFG_FREQ_OFFSET_HF_COMP_P0_POS = 16 +}; + +enum CC2650_CCFG_FREQ_OFFSET_MASK { + CC2650_CCFG_FREQ_OFFSET_HF_COMP_P2_MASK = 0x000000FF, + CC2650_CCFG_FREQ_OFFSET_HF_COMP_P1_MASK = 0x0000FF00, + CC2650_CCFG_FREQ_OFFSET_HF_COMP_P0_MASK = 0xFFFF0000 +}; + +/* IEEE_MAC_0 */ +enum CC2650_CCFG_IEEE_MAC_0_POS { + CC2650_CCFG_IEEE_MAC_0_ADDR_POS = 0 +}; + +enum CC2650_CCFG_IEEE_MAC_0_MASK { + CC2650_CCFG_IEEE_MAC_0_ADDR_MASK = 0xFFFFFFFF +}; + +/* IEEE_MAC_1 */ +enum CC2650_CCFG_IEEE_MAC_1_POS { + CC2650_CCFG_IEEE_MAC_1_ADDR_POS = 0 +}; + +enum CC2650_CCFG_IEEE_MAC_1_MASK { + CC2650_CCFG_IEEE_MAC_1_ADDR_MASK = 0xFFFFFFFF +}; + +/* IEEE_BLE_0 */ +enum CC2650_CCFG_IEEE_BLE_POS { + CC2650_CCFG_IEEE_BLE_0_ADDR_POS = 0 +}; + +enum CC2650_CCFG_IEEE_BLE_MASK { + CC2650_CCFG_IEEE_BLE_0_ADDR_MASK = 0xFFFFFFFF +}; + +/* IEEE_BLE_1 */ +enum CC2650_CCFG_IEEE_BLE_1_POS { + CC2650_CCFG_IEEE_BLE_1_ADDR_POS = 0 +}; + +enum CC2650_CCFG_IEEE_BLE_1_MASK { + CC2650_CCFG_IEEE_BLE_1_ADDR_MASK = 0xFFFFFFFF +}; + +/* BL_CONFIG */ +enum CC2650_CCFG_BL_CONFIG_POS { + CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS = 0, + CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_POS = 8, + CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS = 16, + CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS = 24 +}; + +enum CC2650_CCFG_BL_CONFIG_MASK { + CC2650_CCFG_BL_CONFIG_BL_ENABLE_MASK = 0x000000FF, + CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_MASK = 0x0000FF00, + CC2650_CCFG_BL_CONFIG_BL_LEVEL_MASK = 0x00010000, + CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_MASK = 0xFF000000 +}; + +enum CC2650_CCFG_BL_CONFIG_VALUES { + CC2650_CCFG_BACKDOOR_ENABLED = + 0xC5 << CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS, + CC2650_CCFG_BACKDOOR_DISABLED = + 0x00 << CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS, + CC2650_CCFG_BACKDOOR_ACTIVE_HIGH = + 0x1 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS, + CC2650_CCFG_BACKDOOR_ACTIVE_LOW = + 0x0 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS, + CC2650_CCFG_BOOTLOADER_ENABLED = + 0xC5 << CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS, + CC2650_CCFG_BOOTLOADER_DISABLED = + 0x00 << CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS +}; + +/* ERASE_CONF */ +enum CC2650_CCFG_ERASE_CONF_POS { + CC2650_CCFG_ERASE_CONF_BANK_ERASE_DIS_N_POS = 0, + CC2650_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_POS = 8 +}; + +enum CC2650_CCFG_ERASE_CONF_MASK { + CC2650_CCFG_ERASE_CONF_BANK_ERASE_DIS_N_MASK = 0x00000001, + CC2650_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_MASK = 0x00000100 +}; + +/* CCFG_TI_OPTIONS */ +enum CC2650_CCFG_TI_OPTIONS_POS { + CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS = 0 +}; + +enum CC2650_CCFG_TI_OPTIONS_MASK { + CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_MASK = 0x000000FF +}; + +enum CC2650_CCFG_TI_OPTIONS_VALUES { + CC2650_CCFG_TI_FA_ENABLED = + 0xC5 << CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS, + CC2650_CCFG_TI_FA_DISABLED = + 0x00 << CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS +}; + +/* CCFG_TAP_DAP_0 */ +enum CC2650_CCFG_TAP_DAP_0_POS { + CC2650_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_POS = 0, + CC2650_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_POS = 8, + CC2650_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_POS = 16 +}; + +enum CC2650_CCFG_TAP_DAP_0_MASK { + CC2650_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_MASK = + 0x000000FF, + CC2650_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_MASK = + 0x0000FF00, + CC2650_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_MASK = + 0x00FF0000 +}; + +/* CCFG_TAP_DAP_1 */ +enum CC2650_CCFG_CCFG_TAP_DAP_1_POS { + CC2650_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_POS = 0, + CC2650_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_POS = 8, + CC2650_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_POS = 16 +}; + +enum CC2650_CCFG_CCFG_TAP_DAP_1_MASK { + CC2650_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_MASK = + 0x000000FF, + CC2650_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_MASK = + 0x0000FF00, + CC2650_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_MASK = + 0x00FF0000 +}; + +/* IMAGE_VALID_CONF */ +enum CC2650_CCFG_IMAGE_VALID_CONF_POS { + CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_POS = 0 +}; + +enum CC2650_CCFG_IMAGE_VALID_CONF_MASK { + CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_MASK = 0xFFFFFFFF +}; + +enum CC2650_CCFG_IMAGE_VALID_CONF_VALUES { + CC2650_CCFG_IMAGE_IS_VALID = + 0x00000000 << CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_POS +}; + +/* CCFG_PROT_31_0 */ +enum CC2650_CCFG_CCFG_PROT_31_0_POS { + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_POS = 0, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_POS = 1, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_POS = 2, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_POS = 3, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_POS = 4, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_POS = 5, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_POS = 6, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_POS = 7, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_POS = 8, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_POS = 9, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_POS = 10, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_POS = 11, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_POS = 12, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_POS = 13, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_POS = 14, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_POS = 15, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_POS = 16, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_POS = 17, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_POS = 18, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_POS = 19, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_POS = 20, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_POS = 21, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_POS = 22, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_POS = 23, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_POS = 24, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_POS = 25, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_POS = 26, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_POS = 27, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_POS = 28, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_POS = 29, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_POS = 30, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_POS = 31 +}; + +enum CC2650_CCFG_CCFG_PROT_31_0_MASK { + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_MASK = + 0x00000001, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_MASK = + 0x00000002, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_MASK = + 0x00000004, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_MASK = + 0x00000008, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_MASK = + 0x00000010, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_MASK = + 0x00000020, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_MASK = + 0x00000040, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_MASK = + 0x00000080, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_MASK = + 0x00000100, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_MASK = + 0x00000200, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_MASK = + 0x00000400, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_MASK = + 0x00000800, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_MASK = + 0x00001000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_MASK = + 0x00002000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_MASK = + 0x00004000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_MASK = + 0x00008000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_MASK = + 0x00010000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_MASK = + 0x00020000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_MASK = + 0x00040000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_MASK = + 0x00080000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_MASK = + 0x00100000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_MASK = + 0x00200000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_MASK = + 0x00400000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_MASK = + 0x00800000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_MASK = + 0x01000000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_MASK = + 0x02000000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_MASK = + 0x04000000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_MASK = + 0x08000000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_MASK = + 0x10000000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_MASK = + 0x20000000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_MASK = + 0x40000000, + CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_MASK = + 0x80000000 +}; + +/* CCFG_PROT_63_32 */ +enum CC2650_CCFG_CCFG_PROT_63_32_POS { + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_POS = 32, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_POS = 33, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_POS = 34, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_POS = 35, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_POS = 36, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_POS = 37, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_POS = 38, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_POS = 39, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_POS = 40, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_POS = 41, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_POS = 42, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_POS = 43, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_POS = 44, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_POS = 45, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_POS = 46, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_POS = 47, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_POS = 48, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_POS = 49, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_POS = 50, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_POS = 51, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_POS = 52, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_POS = 53, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_POS = 54, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_POS = 55, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_POS = 56, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_POS = 57, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_POS = 58, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_POS = 59, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_POS = 60, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_POS = 61, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_POS = 62, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_POS = 63 +}; + +enum CC2650_CCFG_CCFG_PROT_63_32_MASK { + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_MASK = + 0x00000001, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_MASK = + 0x00000002, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_MASK = + 0x00000004, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_MASK = + 0x00000008, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_MASK = + 0x00000010, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_MASK = + 0x00000020, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_MASK = + 0x00000040, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_MASK = + 0x00000080, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_MASK = + 0x00000100, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_MASK = + 0x00000200, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_MASK = + 0x00000400, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_MASK = + 0x00000800, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_MASK = + 0x00001000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_MASK = + 0x00002000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_MASK = + 0x00004000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_MASK = + 0x00008000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_MASK = + 0x00010000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_MASK = + 0x00020000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_MASK = + 0x00040000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_MASK = + 0x00080000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_MASK = + 0x00100000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_MASK = + 0x00200000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_MASK = + 0x00400000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_MASK = + 0x00800000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_MASK = + 0x01000000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_MASK = + 0x02000000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_MASK = + 0x04000000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_MASK = + 0x08000000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_MASK = + 0x10000000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_MASK = + 0x20000000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_MASK = + 0x40000000, + CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_MASK = + 0x80000000 +}; + +/* CCFG_PROT_95_64 */ +enum CC2650_CCFG_CCFG_PROT_95_64_POS { + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_POS = 64, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_POS = 65, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_POS = 66, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_POS = 67, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_POS = 68, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_POS = 69, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_POS = 70, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_POS = 71, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_POS = 72, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_POS = 73, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_POS = 74, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_POS = 75, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_POS = 76, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_POS = 77, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_POS = 78, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_POS = 79, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_POS = 80, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_POS = 81, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_POS = 82, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_POS = 83, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_POS = 84, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_POS = 85, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_POS = 86, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_POS = 87, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_POS = 88, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_POS = 89, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_POS = 90, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_POS = 91, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_POS = 92, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_POS = 93, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_POS = 94, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_POS = 95 +}; + +enum CC2650_CCFG_CCFG_PROT_95_64_MASK { + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_MASK = + 0x00000001, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_MASK = + 0x00000002, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_MASK = + 0x00000004, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_MASK = + 0x00000008, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_MASK = + 0x00000010, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_MASK = + 0x00000020, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_MASK = + 0x00000040, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_MASK = + 0x00000080, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_MASK = + 0x00000100, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_MASK = + 0x00000200, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_MASK = + 0x00000400, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_MASK = + 0x00000800, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_MASK = + 0x00001000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_MASK = + 0x00002000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_MASK = + 0x00004000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_MASK = + 0x00008000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_MASK = + 0x00010000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_MASK = + 0x00020000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_MASK = + 0x00040000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_MASK = + 0x00080000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_MASK = + 0x00100000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_MASK = + 0x00200000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_MASK = + 0x00400000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_MASK = + 0x00800000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_MASK = + 0x01000000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_MASK = + 0x02000000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_MASK = + 0x04000000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_MASK = + 0x08000000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_MASK = + 0x10000000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_MASK = + 0x20000000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_MASK = + 0x40000000, + CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_MASK = + 0x80000000 +}; + +/* CCFG_PROT_127_96 */ +enum CC2650_CCFG_CCFG_PROT_127_96_POS { + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_POS = 96, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_POS = 97, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_POS = 98, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_POS = 99, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_POS = 100, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_POS = 101, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_POS = 102, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_POS = 103, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_POS = 104, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_POS = 105, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_POS = 106, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_POS = 107, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_POS = 108, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_POS = 109, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_POS = 110, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_POS = 111, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_POS = 112, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_POS = 113, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_POS = 114, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_POS = 115, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_POS = 116, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_POS = 117, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_POS = 118, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_POS = 119, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_POS = 120, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_POS = 121, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_POS = 122, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_POS = 123, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_POS = 124, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_POS = 125, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_POS = 126, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_POS = 127 +}; + +enum CC2650_CCFG_CCFG_PROT_127_96_MASK { + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_MASK = + 0x00000001, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_MASK = + 0x00000002, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_MASK = + 0x00000004, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_MASK = + 0x00000008, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_MASK = + 0x00000010, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_MASK = + 0x00000020, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_MASK = + 0x00000040, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_MASK = + 0x00000080, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_MASK = + 0x00000100, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_MASK = + 0x00000200, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_MASK = + 0x00000400, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_MASK = + 0x00000800, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_MASK = + 0x00001000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_MASK = + 0x00002000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_MASK = + 0x00004000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_MASK = + 0x00008000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_MASK = + 0x00010000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_MASK = + 0x00020000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_MASK = + 0x00040000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_MASK = + 0x00080000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_MASK = + 0x00100000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_MASK = + 0x00200000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_MASK = + 0x00400000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_MASK = + 0x00800000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_MASK = + 0x01000000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_MASK = + 0x02000000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_MASK = + 0x04000000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_MASK = + 0x08000000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_MASK = + 0x10000000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_MASK = + 0x20000000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_MASK = + 0x40000000, + CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_MASK = + 0x80000000 +}; + +#endif /* _CC2650_CCFG_H_ */ diff --git a/arch/arm/soc/ti_simplelink/cc2650/include/gpio.h b/arch/arm/soc/ti_simplelink/cc2650/include/gpio.h new file mode 100644 index 00000000000000..38e2c34709b060 --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/include/gpio.h @@ -0,0 +1,658 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * GPIO registers and bit offsets for the CC2650 System on Chip. + */ + + +#ifndef _CC2650_GPIO_H_ +#define _CC2650_GPIO_H_ + +/* Registers */ + +enum CC2650_GPIO_Registers { + CC2650_GPIO_DOUT3_0 = 0x0, + CC2650_GPIO_DOUT7_4 = 0x4, + CC2650_GPIO_DOUT11_8 = 0x8, + CC2650_GPIO_DOUT15_12 = 0xC, + CC2650_GPIO_DOUT19_16 = 0x10, + CC2650_GPIO_DOUT23_20 = 0x14, + CC2650_GPIO_DOUT27_24 = 0x18, + CC2650_GPIO_DOUT31_28 = 0x1C, + /* Reserved */ + CC2650_GPIO_DOUT31_0 = 0x80, + /* Reserved */ + CC2650_GPIO_DOUTSET31_0 = 0x90, + /* Reserved */ + CC2650_GPIO_DOUTCLR31_0 = 0XA0, + /* Reserved */ + CC2650_GPIO_DOUTTGL31_0 = 0xB0, + /* Reserved */ + CC2650_GPIO_DIN31_0 = 0xC0, + /* Reserved */ + CC2650_GPIO_DOE31_0 = 0xD0, + /* Reserved */ + CC2650_GPIO_EVFLAGS31_0 = 0xE0 +}; + + +/* Register-specific bits */ + +/* DOUT3_0 */ +enum CC2650_GPIO_DOUT3_0_POS { + CC2650_GPIO_DOUT3_0_DIO0_POS = 0, + CC2650_GPIO_DOUT3_0_DIO1_POS = 8, + CC2650_GPIO_DOUT3_0_DIO2_POS = 16, + CC2650_GPIO_DOUT3_0_DIO3_POS = 24 +}; + +enum CC2650_GPIO_DOUT3_0_MASK { + CC2650_GPIO_DOUT3_0_DIO0_MASK = 0x00000001, + CC2650_GPIO_DOUT3_0_DIO1_MASK = 0x00000100, + CC2650_GPIO_DOUT3_0_DIO2_MASK = 0x00010000, + CC2650_GPIO_DOUT3_0_DIO3_MASK = 0x01000000 +}; + +/* DOUT7_4 */ +enum CC2650_GPIO_DOUT7_4_POS { + CC2650_GPIO_DOUT7_4_DIO4_POS = 0, + CC2650_GPIO_DOUT7_4_DIO5_POS = 8, + CC2650_GPIO_DOUT7_4_DIO6_POS = 16, + CC2650_GPIO_DOUT7_4_DIO7_POS = 24 +}; + +enum CC2650_GPIO_DOUT7_4_MASK { + CC2650_GPIO_DOUT7_4_DIO4_MASK = 0x00000001, + CC2650_GPIO_DOUT7_4_DIO5_MASK = 0x00000100, + CC2650_GPIO_DOUT7_4_DIO6_MASK = 0x00010000, + CC2650_GPIO_DOUT7_4_DIO7_MASK = 0x01000000 +}; + +/* DOUT11_8 */ +enum CC2650_GPIO_DOUT11_8_POS { + CC2650_GPIO_DOUT11_8_DIO8_POS = 0, + CC2650_GPIO_DOUT11_8_DIO9_POS = 8, + CC2650_GPIO_DOUT11_8_DIO10_POS = 16, + CC2650_GPIO_DOUT11_8_DIO11_POS = 24 +}; + +enum CC2650_GPIO_DOUT11_8_MASK { + CC2650_GPIO_DOUT11_8_DIO8_MASK = 0x00000001, + CC2650_GPIO_DOUT11_8_DIO9_MASK = 0x00000100, + CC2650_GPIO_DOUT11_8_DIO10_MASK = 0x00010000, + CC2650_GPIO_DOUT11_8_DIO11_MASK = 0x01000000 +}; + +/* DOUT15_12 */ +enum CC2650_GPIO_DOUT15_12_POS { + CC2650_GPIO_DOUT15_12_DIO12_POS = 0, + CC2650_GPIO_DOUT15_12_DIO13_POS = 8, + CC2650_GPIO_DOUT15_12_DIO14_POS = 16, + CC2650_GPIO_DOUT15_12_DIO15_POS = 24 +}; + +enum CC2650_GPIO_DOUT15_12_MASK { + CC2650_GPIO_DOUT15_12_DIO12_MASK = 0x00000001, + CC2650_GPIO_DOUT15_12_DIO13_MASK = 0x00000100, + CC2650_GPIO_DOUT15_12_DIO14_MASK = 0x00010000, + CC2650_GPIO_DOUT15_12_DIO15_MASK = 0x01000000 +}; + +/* DOUT19_16 */ +enum CC2650_GPIO_DOUT19_16_POS { + CC2650_GPIO_DOUT19_16_DIO16_POS = 0, + CC2650_GPIO_DOUT19_16_DIO17_POS = 8, + CC2650_GPIO_DOUT19_16_DIO18_POS = 16, + CC2650_GPIO_DOUT19_16_DIO19_POS = 24 +}; + +enum CC2650_GPIO_DOUT19_16_MASK { + CC2650_GPIO_DOUT19_16_DIO16_MASK = 0x00000001, + CC2650_GPIO_DOUT19_16_DIO17_MASK = 0x00000100, + CC2650_GPIO_DOUT19_16_DIO18_MASK = 0x00010000, + CC2650_GPIO_DOUT19_16_DIO19_MASK = 0x01000000 +}; + +/* DOUT23_20 */ +enum CC2650_GPIO_DOUT23_20_POS { + CC2650_GPIO_DOUT23_20_DIO20_POS = 0, + CC2650_GPIO_DOUT23_20_DIO21_POS = 8, + CC2650_GPIO_DOUT23_20_DIO22_POS = 16, + CC2650_GPIO_DOUT23_20_DIO23_POS = 24 +}; + +enum CC2650_GPIO_DOUT23_20_MASK { + CC2650_GPIO_DOUT23_20_DIO20_MASK = 0x00000001, + CC2650_GPIO_DOUT23_20_DIO21_MASK = 0x00000100, + CC2650_GPIO_DOUT23_20_DIO22_MASK = 0x00010000, + CC2650_GPIO_DOUT23_20_DIO23_MASK = 0x01000000 +}; + +/* DOUT27_24 */ +enum CC2650_GPIO_DOUT27_24_POS { + CC2650_GPIO_DOUT27_24_DIO24_POS = 0, + CC2650_GPIO_DOUT27_24_DIO25_POS = 8, + CC2650_GPIO_DOUT27_24_DIO26_POS = 16, + CC2650_GPIO_DOUT27_24_DIO27_POS = 24 +}; + +enum CC2650_GPIO_DOUT27_24_MASK { + CC2650_GPIO_DOUT27_24_DIO24_MASK = 0x00000001, + CC2650_GPIO_DOUT27_24_DIO25_MASK = 0x00000100, + CC2650_GPIO_DOUT27_24_DIO26_MASK = 0x00010000, + CC2650_GPIO_DOUT27_24_DIO27_MASK = 0x01000000 +}; + +/* DOUT31_28 */ +enum CC2650_GPIO_DOUT31_28_POS { + CC2650_GPIO_DOUT31_28_DIO28_POS = 0, + CC2650_GPIO_DOUT31_28_DIO29_POS = 8, + CC2650_GPIO_DOUT31_28_DIO30_POS = 16, + CC2650_GPIO_DOUT31_28_DIO31_POS = 24 +}; + +enum CC2650_GPIO_DOUT31_28_MASK { + CC2650_GPIO_DOUT31_28_DIO28 = 0x00000001, + CC2650_GPIO_DOUT31_28_DIO29 = 0x00000100, + CC2650_GPIO_DOUT31_28_DIO30 = 0x00010000, + CC2650_GPIO_DOUT31_28_DIO31 = 0x01000000 +}; + +/* DOUT31_0 */ +enum CC2650_GPIO_DOUT31_0_POS { + CC2650_GPIO_DOUT31_0_DIO0_POS = 0, + CC2650_GPIO_DOUT31_0_DIO1_POS = 1, + CC2650_GPIO_DOUT31_0_DIO2_POS = 2, + CC2650_GPIO_DOUT31_0_DIO3_POS = 3, + CC2650_GPIO_DOUT31_0_DIO4_POS = 4, + CC2650_GPIO_DOUT31_0_DIO5_POS = 5, + CC2650_GPIO_DOUT31_0_DIO6_POS = 6, + CC2650_GPIO_DOUT31_0_DIO7_POS = 7, + CC2650_GPIO_DOUT31_0_DIO8_POS = 8, + CC2650_GPIO_DOUT31_0_DIO9_POS = 9, + CC2650_GPIO_DOUT31_0_DIO10_POS = 10, + CC2650_GPIO_DOUT31_0_DIO11_POS = 11, + CC2650_GPIO_DOUT31_0_DIO12_POS = 12, + CC2650_GPIO_DOUT31_0_DIO13_POS = 13, + CC2650_GPIO_DOUT31_0_DIO14_POS = 14, + CC2650_GPIO_DOUT31_0_DIO15_POS = 15, + CC2650_GPIO_DOUT31_0_DIO16_POS = 16, + CC2650_GPIO_DOUT31_0_DIO17_POS = 17, + CC2650_GPIO_DOUT31_0_DIO18_POS = 18, + CC2650_GPIO_DOUT31_0_DIO19_POS = 19, + CC2650_GPIO_DOUT31_0_DIO20_POS = 20, + CC2650_GPIO_DOUT31_0_DIO21_POS = 21, + CC2650_GPIO_DOUT31_0_DIO22_POS = 22, + CC2650_GPIO_DOUT31_0_DIO23_POS = 23, + CC2650_GPIO_DOUT31_0_DIO24_POS = 24, + CC2650_GPIO_DOUT31_0_DIO25_POS = 25, + CC2650_GPIO_DOUT31_0_DIO26_POS = 26, + CC2650_GPIO_DOUT31_0_DIO27_POS = 27, + CC2650_GPIO_DOUT31_0_DIO28_POS = 28, + CC2650_GPIO_DOUT31_0_DIO29_POS = 29, + CC2650_GPIO_DOUT31_0_DIO30_POS = 30, + CC2650_GPIO_DOUT31_0_DIO31_POS = 31 +}; + +enum CC2650_GPIO_DOUT31_0_MASK { + CC2650_GPIO_DOUT31_0_DIO0_MASK = 0x00000001, + CC2650_GPIO_DOUT31_0_DIO1_MASK = 0x00000002, + CC2650_GPIO_DOUT31_0_DIO2_MASK = 0x00000004, + CC2650_GPIO_DOUT31_0_DIO3_MASK = 0x00000008, + CC2650_GPIO_DOUT31_0_DIO4_MASK = 0x00000010, + CC2650_GPIO_DOUT31_0_DIO5_MASK = 0x00000020, + CC2650_GPIO_DOUT31_0_DIO6_MASK = 0x00000040, + CC2650_GPIO_DOUT31_0_DIO7_MASK = 0x00000080, + CC2650_GPIO_DOUT31_0_DIO8_MASK = 0x00000100, + CC2650_GPIO_DOUT31_0_DIO9_MASK = 0x00000200, + CC2650_GPIO_DOUT31_0_DIO10_MASK = 0x00000400, + CC2650_GPIO_DOUT31_0_DIO11_MASK = 0x00000800, + CC2650_GPIO_DOUT31_0_DIO12_MASK = 0x00001000, + CC2650_GPIO_DOUT31_0_DIO13_MASK = 0x00002000, + CC2650_GPIO_DOUT31_0_DIO14_MASK = 0x00004000, + CC2650_GPIO_DOUT31_0_DIO15_MASK = 0x00008000, + CC2650_GPIO_DOUT31_0_DIO16_MASK = 0x00010000, + CC2650_GPIO_DOUT31_0_DIO17_MASK = 0x00020000, + CC2650_GPIO_DOUT31_0_DIO18_MASK = 0x00040000, + CC2650_GPIO_DOUT31_0_DIO19_MASK = 0x00080000, + CC2650_GPIO_DOUT31_0_DIO20_MASK = 0x00100000, + CC2650_GPIO_DOUT31_0_DIO21_MASK = 0x00200000, + CC2650_GPIO_DOUT31_0_DIO22_MASK = 0x00400000, + CC2650_GPIO_DOUT31_0_DIO23_MASK = 0x00800000, + CC2650_GPIO_DOUT31_0_DIO24_MASK = 0x01000000, + CC2650_GPIO_DOUT31_0_DIO25_MASK = 0x02000000, + CC2650_GPIO_DOUT31_0_DIO26_MASK = 0x04000000, + CC2650_GPIO_DOUT31_0_DIO27_MASK = 0x08000000, + CC2650_GPIO_DOUT31_0_DIO28_MASK = 0x10000000, + CC2650_GPIO_DOUT31_0_DIO29_MASK = 0x20000000, + CC2650_GPIO_DOUT31_0_DIO30_MASK = 0x40000000, + CC2650_GPIO_DOUT31_0_DIO31_MASK = 0x80000000 +}; + +/* DOUTSET31_0 */ +enum CC2650_GPIO_DOUTSET31_0_POS { + CC2650_GPIO_DOUTSET31_0_DIO0_POS = 0, + CC2650_GPIO_DOUTSET31_0_DIO1_POS = 1, + CC2650_GPIO_DOUTSET31_0_DIO2_POS = 2, + CC2650_GPIO_DOUTSET31_0_DIO3_POS = 3, + CC2650_GPIO_DOUTSET31_0_DIO4_POS = 4, + CC2650_GPIO_DOUTSET31_0_DIO5_POS = 5, + CC2650_GPIO_DOUTSET31_0_DIO6_POS = 6, + CC2650_GPIO_DOUTSET31_0_DIO7_POS = 7, + CC2650_GPIO_DOUTSET31_0_DIO8_POS = 8, + CC2650_GPIO_DOUTSET31_0_DIO9_POS = 9, + CC2650_GPIO_DOUTSET31_0_DIO10_POS = 10, + CC2650_GPIO_DOUTSET31_0_DIO11_POS = 11, + CC2650_GPIO_DOUTSET31_0_DIO12_POS = 12, + CC2650_GPIO_DOUTSET31_0_DIO13_POS = 13, + CC2650_GPIO_DOUTSET31_0_DIO14_POS = 14, + CC2650_GPIO_DOUTSET31_0_DIO15_POS = 15, + CC2650_GPIO_DOUTSET31_0_DIO16_POS = 16, + CC2650_GPIO_DOUTSET31_0_DIO17_POS = 17, + CC2650_GPIO_DOUTSET31_0_DIO18_POS = 18, + CC2650_GPIO_DOUTSET31_0_DIO19_POS = 19, + CC2650_GPIO_DOUTSET31_0_DIO20_POS = 20, + CC2650_GPIO_DOUTSET31_0_DIO21_POS = 21, + CC2650_GPIO_DOUTSET31_0_DIO22_POS = 22, + CC2650_GPIO_DOUTSET31_0_DIO23_POS = 23, + CC2650_GPIO_DOUTSET31_0_DIO24_POS = 24, + CC2650_GPIO_DOUTSET31_0_DIO25_POS = 25, + CC2650_GPIO_DOUTSET31_0_DIO26_POS = 26, + CC2650_GPIO_DOUTSET31_0_DIO27_POS = 27, + CC2650_GPIO_DOUTSET31_0_DIO28_POS = 28, + CC2650_GPIO_DOUTSET31_0_DIO29_POS = 29, + CC2650_GPIO_DOUTSET31_0_DIO30_POS = 30, + CC2650_GPIO_DOUTSET31_0_DIO31_POS = 31 +}; + +enum CC2650_GPIO_DOUTSET31_0_MASK { + CC2650_GPIO_DOUTSET31_0_DIO0_MASK = 0x00000001, + CC2650_GPIO_DOUTSET31_0_DIO1_MASK = 0x00000002, + CC2650_GPIO_DOUTSET31_0_DIO2_MASK = 0x00000004, + CC2650_GPIO_DOUTSET31_0_DIO3_MASK = 0x00000008, + CC2650_GPIO_DOUTSET31_0_DIO4_MASK = 0x00000010, + CC2650_GPIO_DOUTSET31_0_DIO5_MASK = 0x00000020, + CC2650_GPIO_DOUTSET31_0_DIO6_MASK = 0x00000040, + CC2650_GPIO_DOUTSET31_0_DIO7_MASK = 0x00000080, + CC2650_GPIO_DOUTSET31_0_DIO8_MASK = 0x00000100, + CC2650_GPIO_DOUTSET31_0_DIO9_MASK = 0x00000200, + CC2650_GPIO_DOUTSET31_0_DIO10_MASK = 0x00000400, + CC2650_GPIO_DOUTSET31_0_DIO11_MASK = 0x00000800, + CC2650_GPIO_DOUTSET31_0_DIO12_MASK = 0x00001000, + CC2650_GPIO_DOUTSET31_0_DIO13_MASK = 0x00002000, + CC2650_GPIO_DOUTSET31_0_DIO14_MASK = 0x00004000, + CC2650_GPIO_DOUTSET31_0_DIO15_MASK = 0x00008000, + CC2650_GPIO_DOUTSET31_0_DIO16_MASK = 0x00010000, + CC2650_GPIO_DOUTSET31_0_DIO17_MASK = 0x00020000, + CC2650_GPIO_DOUTSET31_0_DIO18_MASK = 0x00040000, + CC2650_GPIO_DOUTSET31_0_DIO19_MASK = 0x00080000, + CC2650_GPIO_DOUTSET31_0_DIO20_MASK = 0x00100000, + CC2650_GPIO_DOUTSET31_0_DIO21_MASK = 0x00200000, + CC2650_GPIO_DOUTSET31_0_DIO22_MASK = 0x00400000, + CC2650_GPIO_DOUTSET31_0_DIO23_MASK = 0x00800000, + CC2650_GPIO_DOUTSET31_0_DIO24_MASK = 0x01000000, + CC2650_GPIO_DOUTSET31_0_DIO25_MASK = 0x02000000, + CC2650_GPIO_DOUTSET31_0_DIO26_MASK = 0x04000000, + CC2650_GPIO_DOUTSET31_0_DIO27_MASK = 0x08000000, + CC2650_GPIO_DOUTSET31_0_DIO28_MASK = 0x10000000, + CC2650_GPIO_DOUTSET31_0_DIO29_MASK = 0x20000000, + CC2650_GPIO_DOUTSET31_0_DIO30_MASK = 0x40000000, + CC2650_GPIO_DOUTSET31_0_DIO31_MASK = 0x80000000 +}; + +/* DOUTCLR31_0 */ +enum CC2650_GPIO_DOUTCLR31_0_POS { + CC2650_GPIO_DOUTCLR31_0_DIO0_POS = 0, + CC2650_GPIO_DOUTCLR31_0_DIO1_POS = 1, + CC2650_GPIO_DOUTCLR31_0_DIO2_POS = 2, + CC2650_GPIO_DOUTCLR31_0_DIO3_POS = 3, + CC2650_GPIO_DOUTCLR31_0_DIO4_POS = 4, + CC2650_GPIO_DOUTCLR31_0_DIO5_POS = 5, + CC2650_GPIO_DOUTCLR31_0_DIO6_POS = 6, + CC2650_GPIO_DOUTCLR31_0_DIO7_POS = 7, + CC2650_GPIO_DOUTCLR31_0_DIO8_POS = 8, + CC2650_GPIO_DOUTCLR31_0_DIO9_POS = 9, + CC2650_GPIO_DOUTCLR31_0_DIO10_POS = 10, + CC2650_GPIO_DOUTCLR31_0_DIO11_POS = 11, + CC2650_GPIO_DOUTCLR31_0_DIO12_POS = 12, + CC2650_GPIO_DOUTCLR31_0_DIO13_POS = 13, + CC2650_GPIO_DOUTCLR31_0_DIO14_POS = 14, + CC2650_GPIO_DOUTCLR31_0_DIO15_POS = 15, + CC2650_GPIO_DOUTCLR31_0_DIO16_POS = 16, + CC2650_GPIO_DOUTCLR31_0_DIO17_POS = 17, + CC2650_GPIO_DOUTCLR31_0_DIO18_POS = 18, + CC2650_GPIO_DOUTCLR31_0_DIO19_POS = 19, + CC2650_GPIO_DOUTCLR31_0_DIO20_POS = 20, + CC2650_GPIO_DOUTCLR31_0_DIO21_POS = 21, + CC2650_GPIO_DOUTCLR31_0_DIO22_POS = 22, + CC2650_GPIO_DOUTCLR31_0_DIO23_POS = 23, + CC2650_GPIO_DOUTCLR31_0_DIO24_POS = 24, + CC2650_GPIO_DOUTCLR31_0_DIO25_POS = 25, + CC2650_GPIO_DOUTCLR31_0_DIO26_POS = 26, + CC2650_GPIO_DOUTCLR31_0_DIO27_POS = 27, + CC2650_GPIO_DOUTCLR31_0_DIO28_POS = 28, + CC2650_GPIO_DOUTCLR31_0_DIO29_POS = 29, + CC2650_GPIO_DOUTCLR31_0_DIO30_POS = 30, + CC2650_GPIO_DOUTCLR31_0_DIO31_POS = 31 +}; + +enum CC2650_GPIO_DOUTCLR31_0_MASK { + CC2650_GPIO_DOUTCLR31_0_DIO0_MASK = 0x00000001, + CC2650_GPIO_DOUTCLR31_0_DIO1_MASK = 0x00000002, + CC2650_GPIO_DOUTCLR31_0_DIO2_MASK = 0x00000004, + CC2650_GPIO_DOUTCLR31_0_DIO3_MASK = 0x00000008, + CC2650_GPIO_DOUTCLR31_0_DIO4_MASK = 0x00000010, + CC2650_GPIO_DOUTCLR31_0_DIO5_MASK = 0x00000020, + CC2650_GPIO_DOUTCLR31_0_DIO6_MASK = 0x00000040, + CC2650_GPIO_DOUTCLR31_0_DIO7_MASK = 0x00000080, + CC2650_GPIO_DOUTCLR31_0_DIO8_MASK = 0x00000100, + CC2650_GPIO_DOUTCLR31_0_DIO9_MASK = 0x00000200, + CC2650_GPIO_DOUTCLR31_0_DIO10_MASK = 0x00000400, + CC2650_GPIO_DOUTCLR31_0_DIO11_MASK = 0x00000800, + CC2650_GPIO_DOUTCLR31_0_DIO12_MASK = 0x00001000, + CC2650_GPIO_DOUTCLR31_0_DIO13_MASK = 0x00002000, + CC2650_GPIO_DOUTCLR31_0_DIO14_MASK = 0x00004000, + CC2650_GPIO_DOUTCLR31_0_DIO15_MASK = 0x00008000, + CC2650_GPIO_DOUTCLR31_0_DIO16_MASK = 0x00010000, + CC2650_GPIO_DOUTCLR31_0_DIO17_MASK = 0x00020000, + CC2650_GPIO_DOUTCLR31_0_DIO18_MASK = 0x00040000, + CC2650_GPIO_DOUTCLR31_0_DIO19_MASK = 0x00080000, + CC2650_GPIO_DOUTCLR31_0_DIO20_MASK = 0x00100000, + CC2650_GPIO_DOUTCLR31_0_DIO21_MASK = 0x00200000, + CC2650_GPIO_DOUTCLR31_0_DIO22_MASK = 0x00400000, + CC2650_GPIO_DOUTCLR31_0_DIO23_MASK = 0x00800000, + CC2650_GPIO_DOUTCLR31_0_DIO24_MASK = 0x01000000, + CC2650_GPIO_DOUTCLR31_0_DIO25_MASK = 0x02000000, + CC2650_GPIO_DOUTCLR31_0_DIO26_MASK = 0x04000000, + CC2650_GPIO_DOUTCLR31_0_DIO27_MASK = 0x08000000, + CC2650_GPIO_DOUTCLR31_0_DIO28_MASK = 0x10000000, + CC2650_GPIO_DOUTCLR31_0_DIO29_MASK = 0x20000000, + CC2650_GPIO_DOUTCLR31_0_DIO30_MASK = 0x40000000, + CC2650_GPIO_DOUTCLR31_0_DIO31_MASK = 0x80000000 +}; + +/* DOUTTGL31_0 */ +enum CC2650_GPIO_DOUTTGL31_0_POS { + CC2650_GPIO_DOUTTGL31_0_DIO0_POS = 0, + CC2650_GPIO_DOUTTGL31_0_DIO1_POS = 1, + CC2650_GPIO_DOUTTGL31_0_DIO2_POS = 2, + CC2650_GPIO_DOUTTGL31_0_DIO3_POS = 3, + CC2650_GPIO_DOUTTGL31_0_DIO4_POS = 4, + CC2650_GPIO_DOUTTGL31_0_DIO5_POS = 5, + CC2650_GPIO_DOUTTGL31_0_DIO6_POS = 6, + CC2650_GPIO_DOUTTGL31_0_DIO7_POS = 7, + CC2650_GPIO_DOUTTGL31_0_DIO8_POS = 8, + CC2650_GPIO_DOUTTGL31_0_DIO9_POS = 9, + CC2650_GPIO_DOUTTGL31_0_DIO10_POS = 10, + CC2650_GPIO_DOUTTGL31_0_DIO11_POS = 11, + CC2650_GPIO_DOUTTGL31_0_DIO12_POS = 12, + CC2650_GPIO_DOUTTGL31_0_DIO13_POS = 13, + CC2650_GPIO_DOUTTGL31_0_DIO14_POS = 14, + CC2650_GPIO_DOUTTGL31_0_DIO15_POS = 15, + CC2650_GPIO_DOUTTGL31_0_DIO16_POS = 16, + CC2650_GPIO_DOUTTGL31_0_DIO17_POS = 17, + CC2650_GPIO_DOUTTGL31_0_DIO18_POS = 18, + CC2650_GPIO_DOUTTGL31_0_DIO19_POS = 19, + CC2650_GPIO_DOUTTGL31_0_DIO20_POS = 20, + CC2650_GPIO_DOUTTGL31_0_DIO21_POS = 21, + CC2650_GPIO_DOUTTGL31_0_DIO22_POS = 22, + CC2650_GPIO_DOUTTGL31_0_DIO23_POS = 23, + CC2650_GPIO_DOUTTGL31_0_DIO24_POS = 24, + CC2650_GPIO_DOUTTGL31_0_DIO25_POS = 25, + CC2650_GPIO_DOUTTGL31_0_DIO26_POS = 26, + CC2650_GPIO_DOUTTGL31_0_DIO27_POS = 27, + CC2650_GPIO_DOUTTGL31_0_DIO28_POS = 28, + CC2650_GPIO_DOUTTGL31_0_DIO29_POS = 29, + CC2650_GPIO_DOUTTGL31_0_DIO30_POS = 30, + CC2650_GPIO_DOUTTGL31_0_DIO31_POS = 31 +}; + +enum CC2650_GPIO_DOUTTGL31_0_MASK { + CC2650_GPIO_DOUTTGL31_0_DIO0_MASK = 0x00000001, + CC2650_GPIO_DOUTTGL31_0_DIO1_MASK = 0x00000002, + CC2650_GPIO_DOUTTGL31_0_DIO2_MASK = 0x00000004, + CC2650_GPIO_DOUTTGL31_0_DIO3_MASK = 0x00000008, + CC2650_GPIO_DOUTTGL31_0_DIO4_MASK = 0x00000010, + CC2650_GPIO_DOUTTGL31_0_DIO5_MASK = 0x00000020, + CC2650_GPIO_DOUTTGL31_0_DIO6_MASK = 0x00000040, + CC2650_GPIO_DOUTTGL31_0_DIO7_MASK = 0x00000080, + CC2650_GPIO_DOUTTGL31_0_DIO8_MASK = 0x00000100, + CC2650_GPIO_DOUTTGL31_0_DIO9_MASK = 0x00000200, + CC2650_GPIO_DOUTTGL31_0_DIO10_MASK = 0x00000400, + CC2650_GPIO_DOUTTGL31_0_DIO11_MASK = 0x00000800, + CC2650_GPIO_DOUTTGL31_0_DIO12_MASK = 0x00001000, + CC2650_GPIO_DOUTTGL31_0_DIO13_MASK = 0x00002000, + CC2650_GPIO_DOUTTGL31_0_DIO14_MASK = 0x00004000, + CC2650_GPIO_DOUTTGL31_0_DIO15_MASK = 0x00008000, + CC2650_GPIO_DOUTTGL31_0_DIO16_MASK = 0x00010000, + CC2650_GPIO_DOUTTGL31_0_DIO17_MASK = 0x00020000, + CC2650_GPIO_DOUTTGL31_0_DIO18_MASK = 0x00040000, + CC2650_GPIO_DOUTTGL31_0_DIO19_MASK = 0x00080000, + CC2650_GPIO_DOUTTGL31_0_DIO20_MASK = 0x00100000, + CC2650_GPIO_DOUTTGL31_0_DIO21_MASK = 0x00200000, + CC2650_GPIO_DOUTTGL31_0_DIO22_MASK = 0x00400000, + CC2650_GPIO_DOUTTGL31_0_DIO23_MASK = 0x00800000, + CC2650_GPIO_DOUTTGL31_0_DIO24_MASK = 0x01000000, + CC2650_GPIO_DOUTTGL31_0_DIO25_MASK = 0x02000000, + CC2650_GPIO_DOUTTGL31_0_DIO26_MASK = 0x04000000, + CC2650_GPIO_DOUTTGL31_0_DIO27_MASK = 0x08000000, + CC2650_GPIO_DOUTTGL31_0_DIO28_MASK = 0x10000000, + CC2650_GPIO_DOUTTGL31_0_DIO29_MASK = 0x20000000, + CC2650_GPIO_DOUTTGL31_0_DIO30_MASK = 0x40000000, + CC2650_GPIO_DOUTTGL31_0_DIO31_MASK = 0x80000000 +}; + +/* DIN31_0 */ +enum CC2650_GPIO_DIN31_0_POS { + CC2650_GPIO_DIN31_0_DIO0_POS = 0, + CC2650_GPIO_DIN31_0_DIO1_POS = 1, + CC2650_GPIO_DIN31_0_DIO2_POS = 2, + CC2650_GPIO_DIN31_0_DIO3_POS = 3, + CC2650_GPIO_DIN31_0_DIO4_POS = 4, + CC2650_GPIO_DIN31_0_DIO5_POS = 5, + CC2650_GPIO_DIN31_0_DIO6_POS = 6, + CC2650_GPIO_DIN31_0_DIO7_POS = 7, + CC2650_GPIO_DIN31_0_DIO8_POS = 8, + CC2650_GPIO_DIN31_0_DIO9_POS = 9, + CC2650_GPIO_DIN31_0_DIO10_POS = 10, + CC2650_GPIO_DIN31_0_DIO11_POS = 11, + CC2650_GPIO_DIN31_0_DIO12_POS = 12, + CC2650_GPIO_DIN31_0_DIO13_POS = 13, + CC2650_GPIO_DIN31_0_DIO14_POS = 14, + CC2650_GPIO_DIN31_0_DIO15_POS = 15, + CC2650_GPIO_DIN31_0_DIO16_POS = 16, + CC2650_GPIO_DIN31_0_DIO17_POS = 17, + CC2650_GPIO_DIN31_0_DIO18_POS = 18, + CC2650_GPIO_DIN31_0_DIO19_POS = 19, + CC2650_GPIO_DIN31_0_DIO20_POS = 20, + CC2650_GPIO_DIN31_0_DIO21_POS = 21, + CC2650_GPIO_DIN31_0_DIO22_POS = 22, + CC2650_GPIO_DIN31_0_DIO23_POS = 23, + CC2650_GPIO_DIN31_0_DIO24_POS = 24, + CC2650_GPIO_DIN31_0_DIO25_POS = 25, + CC2650_GPIO_DIN31_0_DIO26_POS = 26, + CC2650_GPIO_DIN31_0_DIO27_POS = 27, + CC2650_GPIO_DIN31_0_DIO28_POS = 28, + CC2650_GPIO_DIN31_0_DIO29_POS = 29, + CC2650_GPIO_DIN31_0_DIO30_POS = 30, + CC2650_GPIO_DIN31_0_DIO31_POS = 31 +}; + +enum CC2650_GPIO_DIN31_0_MASK { + CC2650_GPIO_DIN31_0_DIO0_MASK = 0x00000001, + CC2650_GPIO_DIN31_0_DIO1_MASK = 0x00000002, + CC2650_GPIO_DIN31_0_DIO2_MASK = 0x00000004, + CC2650_GPIO_DIN31_0_DIO3_MASK = 0x00000008, + CC2650_GPIO_DIN31_0_DIO4_MASK = 0x00000010, + CC2650_GPIO_DIN31_0_DIO5_MASK = 0x00000020, + CC2650_GPIO_DIN31_0_DIO6_MASK = 0x00000040, + CC2650_GPIO_DIN31_0_DIO7_MASK = 0x00000080, + CC2650_GPIO_DIN31_0_DIO8_MASK = 0x00000100, + CC2650_GPIO_DIN31_0_DIO9_MASK = 0x00000200, + CC2650_GPIO_DIN31_0_DIO10_MASK = 0x00000400, + CC2650_GPIO_DIN31_0_DIO11_MASK = 0x00000800, + CC2650_GPIO_DIN31_0_DIO12_MASK = 0x00001000, + CC2650_GPIO_DIN31_0_DIO13_MASK = 0x00002000, + CC2650_GPIO_DIN31_0_DIO14_MASK = 0x00004000, + CC2650_GPIO_DIN31_0_DIO15_MASK = 0x00008000, + CC2650_GPIO_DIN31_0_DIO16_MASK = 0x00010000, + CC2650_GPIO_DIN31_0_DIO17_MASK = 0x00020000, + CC2650_GPIO_DIN31_0_DIO18_MASK = 0x00040000, + CC2650_GPIO_DIN31_0_DIO19_MASK = 0x00080000, + CC2650_GPIO_DIN31_0_DIO20_MASK = 0x00100000, + CC2650_GPIO_DIN31_0_DIO21_MASK = 0x00200000, + CC2650_GPIO_DIN31_0_DIO22_MASK = 0x00400000, + CC2650_GPIO_DIN31_0_DIO23_MASK = 0x00800000, + CC2650_GPIO_DIN31_0_DIO24_MASK = 0x01000000, + CC2650_GPIO_DIN31_0_DIO25_MASK = 0x02000000, + CC2650_GPIO_DIN31_0_DIO26_MASK = 0x04000000, + CC2650_GPIO_DIN31_0_DIO27_MASK = 0x08000000, + CC2650_GPIO_DIN31_0_DIO28_MASK = 0x10000000, + CC2650_GPIO_DIN31_0_DIO29_MASK = 0x20000000, + CC2650_GPIO_DIN31_0_DIO30_MASK = 0x40000000, + CC2650_GPIO_DIN31_0_DIO31_MASK = 0x80000000 +}; + +/* DOE31_0 */ +enum CC2650_GPIO_DOE31_0_POS { + CC2650_GPIO_DOE31_0_DIO0_POS = 0, + CC2650_GPIO_DOE31_0_DIO1_POS = 1, + CC2650_GPIO_DOE31_0_DIO2_POS = 2, + CC2650_GPIO_DOE31_0_DIO3_POS = 3, + CC2650_GPIO_DOE31_0_DIO4_POS = 4, + CC2650_GPIO_DOE31_0_DIO5_POS = 5, + CC2650_GPIO_DOE31_0_DIO6_POS = 6, + CC2650_GPIO_DOE31_0_DIO7_POS = 7, + CC2650_GPIO_DOE31_0_DIO8_POS = 8, + CC2650_GPIO_DOE31_0_DIO9_POS = 9, + CC2650_GPIO_DOE31_0_DIO10_POS = 10, + CC2650_GPIO_DOE31_0_DIO11_POS = 11, + CC2650_GPIO_DOE31_0_DIO12_POS = 12, + CC2650_GPIO_DOE31_0_DIO13_POS = 13, + CC2650_GPIO_DOE31_0_DIO14_POS = 14, + CC2650_GPIO_DOE31_0_DIO15_POS = 15, + CC2650_GPIO_DOE31_0_DIO16_POS = 16, + CC2650_GPIO_DOE31_0_DIO17_POS = 17, + CC2650_GPIO_DOE31_0_DIO18_POS = 18, + CC2650_GPIO_DOE31_0_DIO19_POS = 19, + CC2650_GPIO_DOE31_0_DIO20_POS = 20, + CC2650_GPIO_DOE31_0_DIO21_POS = 21, + CC2650_GPIO_DOE31_0_DIO22_POS = 22, + CC2650_GPIO_DOE31_0_DIO23_POS = 23, + CC2650_GPIO_DOE31_0_DIO24_POS = 24, + CC2650_GPIO_DOE31_0_DIO25_POS = 25, + CC2650_GPIO_DOE31_0_DIO26_POS = 26, + CC2650_GPIO_DOE31_0_DIO27_POS = 27, + CC2650_GPIO_DOE31_0_DIO28_POS = 28, + CC2650_GPIO_DOE31_0_DIO29_POS = 29, + CC2650_GPIO_DOE31_0_DIO30_POS = 30, + CC2650_GPIO_DOE31_0_DIO31_POS = 31 +}; + +enum CC2650_GPIO_DOE31_0_MASK { + CC2650_GPIO_DOE31_0_DIO0_MASK = 0x00000001, + CC2650_GPIO_DOE31_0_DIO1_MASK = 0x00000002, + CC2650_GPIO_DOE31_0_DIO2_MASK = 0x00000004, + CC2650_GPIO_DOE31_0_DIO3_MASK = 0x00000008, + CC2650_GPIO_DOE31_0_DIO4_MASK = 0x00000010, + CC2650_GPIO_DOE31_0_DIO5_MASK = 0x00000020, + CC2650_GPIO_DOE31_0_DIO6_MASK = 0x00000040, + CC2650_GPIO_DOE31_0_DIO7_MASK = 0x00000080, + CC2650_GPIO_DOE31_0_DIO8_MASK = 0x00000100, + CC2650_GPIO_DOE31_0_DIO9_MASK = 0x00000200, + CC2650_GPIO_DOE31_0_DIO10_MASK = 0x00000400, + CC2650_GPIO_DOE31_0_DIO11_MASK = 0x00000800, + CC2650_GPIO_DOE31_0_DIO12_MASK = 0x00001000, + CC2650_GPIO_DOE31_0_DIO13_MASK = 0x00002000, + CC2650_GPIO_DOE31_0_DIO14_MASK = 0x00004000, + CC2650_GPIO_DOE31_0_DIO15_MASK = 0x00008000, + CC2650_GPIO_DOE31_0_DIO16_MASK = 0x00010000, + CC2650_GPIO_DOE31_0_DIO17_MASK = 0x00020000, + CC2650_GPIO_DOE31_0_DIO18_MASK = 0x00040000, + CC2650_GPIO_DOE31_0_DIO19_MASK = 0x00080000, + CC2650_GPIO_DOE31_0_DIO20_MASK = 0x00100000, + CC2650_GPIO_DOE31_0_DIO21_MASK = 0x00200000, + CC2650_GPIO_DOE31_0_DIO22_MASK = 0x00400000, + CC2650_GPIO_DOE31_0_DIO23_MASK = 0x00800000, + CC2650_GPIO_DOE31_0_DIO24_MASK = 0x01000000, + CC2650_GPIO_DOE31_0_DIO25_MASK = 0x02000000, + CC2650_GPIO_DOE31_0_DIO26_MASK = 0x04000000, + CC2650_GPIO_DOE31_0_DIO27_MASK = 0x08000000, + CC2650_GPIO_DOE31_0_DIO28_MASK = 0x10000000, + CC2650_GPIO_DOE31_0_DIO29_MASK = 0x20000000, + CC2650_GPIO_DOE31_0_DIO30_MASK = 0x40000000, + CC2650_GPIO_DOE31_0_DIO31_MASK = 0x80000000 +}; + +/* EVFLAGS31_0 */ +enum CC2650_GPIO_EVFLAGS31_0_POS { + CC2650_GPIO_EVFLAGS31_0_DIO0_POS = 0, + CC2650_GPIO_EVFLAGS31_0_DIO1_POS = 1, + CC2650_GPIO_EVFLAGS31_0_DIO2_POS = 2, + CC2650_GPIO_EVFLAGS31_0_DIO3_POS = 3, + CC2650_GPIO_EVFLAGS31_0_DIO4_POS = 4, + CC2650_GPIO_EVFLAGS31_0_DIO5_POS = 5, + CC2650_GPIO_EVFLAGS31_0_DIO6_POS = 6, + CC2650_GPIO_EVFLAGS31_0_DIO7_POS = 7, + CC2650_GPIO_EVFLAGS31_0_DIO8_POS = 8, + CC2650_GPIO_EVFLAGS31_0_DIO9_POS = 9, + CC2650_GPIO_EVFLAGS31_0_DIO10_POS = 10, + CC2650_GPIO_EVFLAGS31_0_DIO11_POS = 11, + CC2650_GPIO_EVFLAGS31_0_DIO12_POS = 12, + CC2650_GPIO_EVFLAGS31_0_DIO13_POS = 13, + CC2650_GPIO_EVFLAGS31_0_DIO14_POS = 14, + CC2650_GPIO_EVFLAGS31_0_DIO15_POS = 15, + CC2650_GPIO_EVFLAGS31_0_DIO16_POS = 16, + CC2650_GPIO_EVFLAGS31_0_DIO17_POS = 17, + CC2650_GPIO_EVFLAGS31_0_DIO18_POS = 18, + CC2650_GPIO_EVFLAGS31_0_DIO19_POS = 19, + CC2650_GPIO_EVFLAGS31_0_DIO20_POS = 20, + CC2650_GPIO_EVFLAGS31_0_DIO21_POS = 21, + CC2650_GPIO_EVFLAGS31_0_DIO22_POS = 22, + CC2650_GPIO_EVFLAGS31_0_DIO23_POS = 23, + CC2650_GPIO_EVFLAGS31_0_DIO24_POS = 24, + CC2650_GPIO_EVFLAGS31_0_DIO25_POS = 25, + CC2650_GPIO_EVFLAGS31_0_DIO26_POS = 26, + CC2650_GPIO_EVFLAGS31_0_DIO27_POS = 27, + CC2650_GPIO_EVFLAGS31_0_DIO28_POS = 28, + CC2650_GPIO_EVFLAGS31_0_DIO29_POS = 29, + CC2650_GPIO_EVFLAGS31_0_DIO30_POS = 30, + CC2650_GPIO_EVFLAGS31_0_DIO31_POS = 31 +}; + +enum CC2650_GPIO_EVFLAGS31_0_MASK { + CC2650_GPIO_EVFLAGS31_0_DIO0_MASK = 0x00000001, + CC2650_GPIO_EVFLAGS31_0_DIO1_MASK = 0x00000002, + CC2650_GPIO_EVFLAGS31_0_DIO2_MASK = 0x00000004, + CC2650_GPIO_EVFLAGS31_0_DIO3_MASK = 0x00000008, + CC2650_GPIO_EVFLAGS31_0_DIO4_MASK = 0x00000010, + CC2650_GPIO_EVFLAGS31_0_DIO5_MASK = 0x00000020, + CC2650_GPIO_EVFLAGS31_0_DIO6_MASK = 0x00000040, + CC2650_GPIO_EVFLAGS31_0_DIO7_MASK = 0x00000080, + CC2650_GPIO_EVFLAGS31_0_DIO8_MASK = 0x00000100, + CC2650_GPIO_EVFLAGS31_0_DIO9_MASK = 0x00000200, + CC2650_GPIO_EVFLAGS31_0_DIO10_MASK = 0x00000400, + CC2650_GPIO_EVFLAGS31_0_DIO11_MASK = 0x00000800, + CC2650_GPIO_EVFLAGS31_0_DIO12_MASK = 0x00001000, + CC2650_GPIO_EVFLAGS31_0_DIO13_MASK = 0x00002000, + CC2650_GPIO_EVFLAGS31_0_DIO14_MASK = 0x00004000, + CC2650_GPIO_EVFLAGS31_0_DIO15_MASK = 0x00008000, + CC2650_GPIO_EVFLAGS31_0_DIO16_MASK = 0x00010000, + CC2650_GPIO_EVFLAGS31_0_DIO17_MASK = 0x00020000, + CC2650_GPIO_EVFLAGS31_0_DIO18_MASK = 0x00040000, + CC2650_GPIO_EVFLAGS31_0_DIO19_MASK = 0x00080000, + CC2650_GPIO_EVFLAGS31_0_DIO20_MASK = 0x00100000, + CC2650_GPIO_EVFLAGS31_0_DIO21_MASK = 0x00200000, + CC2650_GPIO_EVFLAGS31_0_DIO22_MASK = 0x00400000, + CC2650_GPIO_EVFLAGS31_0_DIO23_MASK = 0x00800000, + CC2650_GPIO_EVFLAGS31_0_DIO24_MASK = 0x01000000, + CC2650_GPIO_EVFLAGS31_0_DIO25_MASK = 0x02000000, + CC2650_GPIO_EVFLAGS31_0_DIO26_MASK = 0x04000000, + CC2650_GPIO_EVFLAGS31_0_DIO27_MASK = 0x08000000, + CC2650_GPIO_EVFLAGS31_0_DIO28_MASK = 0x10000000, + CC2650_GPIO_EVFLAGS31_0_DIO29_MASK = 0x20000000, + CC2650_GPIO_EVFLAGS31_0_DIO30_MASK = 0x40000000, + CC2650_GPIO_EVFLAGS31_0_DIO31_MASK = 0x80000000 +}; + +#endif /* _CC2650_GPIO_H_ */ diff --git a/arch/arm/soc/ti_simplelink/cc2650/include/ioc.h b/arch/arm/soc/ti_simplelink/cc2650/include/ioc.h new file mode 100644 index 00000000000000..8200612d2dedef --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/include/ioc.h @@ -0,0 +1,270 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * GPIO & I/O controller registers and bit offsets for the + * CC2650 System on Chip. + */ + + +#ifndef _CC2650_IOC_H_ +#define _CC2650_IOC_H_ + +/* Registers */ + +enum CC2650_IOC_Registers { + CC2650_IOC_IOCFG0 = 0x0, + CC2650_IOC_IOCFG1 = 0x4, + CC2650_IOC_IOCFG2 = 0x8, + CC2650_IOC_IOCFG3 = 0xC, + CC2650_IOC_IOCFG4 = 0x10, + CC2650_IOC_IOCFG5 = 0x14, + CC2650_IOC_IOCFG6 = 0x18, + CC2650_IOC_IOCFG7 = 0x1C, + CC2650_IOC_IOCFG8 = 0x20, + CC2650_IOC_IOCFG9 = 0x24, + CC2650_IOC_IOCFG10 = 0x28, + CC2650_IOC_IOCFG11 = 0x2C, + CC2650_IOC_IOCFG12 = 0x30, + CC2650_IOC_IOCFG13 = 0x34, + CC2650_IOC_IOCFG14 = 0x38, + CC2650_IOC_IOCFG15 = 0x3C, + CC2650_IOC_IOCFG16 = 0x40, + CC2650_IOC_IOCFG17 = 0x44, + CC2650_IOC_IOCFG18 = 0x48, + CC2650_IOC_IOCFG19 = 0x4C, + CC2650_IOC_IOCFG20 = 0x50, + CC2650_IOC_IOCFG21 = 0x54, + CC2650_IOC_IOCFG22 = 0x58, + CC2650_IOC_IOCFG23 = 0x5C, + CC2650_IOC_IOCFG24 = 0x60, + CC2650_IOC_IOCFG25 = 0x64, + CC2650_IOC_IOCFG26 = 0x68, + CC2650_IOC_IOCFG27 = 0x6C, + CC2650_IOC_IOCFG28 = 0x70, + CC2650_IOC_IOCFG29 = 0x74, + CC2650_IOC_IOCFG30 = 0x78, + CC2650_IOC_IOCFG31 = 0x7C +}; + + +/* Register-specific bits */ + +/* I/O Controller */ +/* All IOCFGx registers are the same. */ +enum CC2650_IOC_IOCFGX_POS { + CC2650_IOC_IOCFGX_PORT_ID_POS = 0, + CC2650_IOC_IOCFGX_IOSTR_POS = 8, + CC2650_IOC_IOCFGX_IOCURR_POS = 10, + CC2650_IOC_IOCFGX_SLEW_RED_POS = 12, + CC2650_IOC_IOCFGX_PULL_CTL_POS = 13, + CC2650_IOC_IOCFGX_EDGE_DET_POS = 16, + CC2650_IOC_IOCFGX_EDGE_IRQ_EN_POS = 18, + CC2650_IOC_IOCFGX_IOMODE_POS = 24, + CC2650_IOC_IOCFGX_WU_CFG_POS = 27, + CC2650_IOC_IOCFGX_IE_POS = 29, + CC2650_IOC_IOCFGX_HYST_EN_POS = 30 +}; + +enum CC2650_IOC_IOCFGX_MASK { + CC2650_IOC_IOCFGX_PORT_ID_MASK = 0x0000003F, + CC2650_IOC_IOCFGX_IOSTR_MASK = 0x00000300, + CC2650_IOC_IOCFGX_IOCURR_MASK = 0x00000C00, + CC2650_IOC_IOCFGX_SLEW_RED_MASK = 0x00001000, + CC2650_IOC_IOCFGX_PULL_CTL_MASK = 0x00006000, + CC2650_IOC_IOCFGX_EDGE_DET_MASK = 0x00030000, + CC2650_IOC_IOCFGX_EDGE_IRQ_EN_MASK = 0x00040000, + CC2650_IOC_IOCFGX_IOMODE_MASK = 0x07000000, + CC2650_IOC_IOCFGX_WU_CFG_MASK = 0x18000000, + CC2650_IOC_IOCFGX_IE_MASK = 0x20000000, + CC2650_IOC_IOCFGX_HYST_EN_MASK = 0x40000000 +}; + + + +/* Port-IDs available */ +enum CC2650_IOC_PORTID { + CC2650_IOC_GPIO = + 0 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_AON_SCS = + 1 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_AON_SCK = + 2 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_AON_SDI = + 3 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_AON_SDO = + 4 << CC2650_IOC_IOCFGX_PORT_ID_POS, + /* Reserved */ + CC2650_IOC_AON_CLK32K = + 7 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_AUX_IO = + 8 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_SSI0_RX = + 9 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_SSI0_TX = + 10 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_SSI0_FSS = + 11 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_SSI0_CLK = + 12 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_I2C_MSSDA = + 13 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_I2C_MSSCL = + 14 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_UART0_RX = + 15 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_UART0_TX = + 16 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_UART0_CTS = + 17 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_UART0_RTS = + 18 << CC2650_IOC_IOCFGX_PORT_ID_POS, + /* Reserved */ + CC2650_IOC_MCU_GPTM_GPTM0 = + 23 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_GPTM_GPTM1 = + 24 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_GPTM_GPTM2 = + 25 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_GPTM_GPTM3 = + 26 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_GPTM_GPTM4 = + 27 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_GPTM_GPTM5 = + 28 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_GPTM_GPTM6 = + 29 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_GPTM_GPTM7 = + 30 << CC2650_IOC_IOCFGX_PORT_ID_POS, + /* Reserved */ + CC2650_IOC_MCU_CM3_SWV = + 32 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_SSI1_RX = + 33 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_SSI1_TX = + 34 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_SSI1_FSS = + 35 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_SSI1_CLK = + 36 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_I2S_AD0 = + 37 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_I2S_AD1 = + 38 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_I2S_WCLK = + 39 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_I2S_BCLK = + 40 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_MCU_I2S_MCLK = + 41 << CC2650_IOC_IOCFGX_PORT_ID_POS, + /* Reserved */ + CC2650_IOC_RFC_GP0 = + 47 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_RFC_GP1 = + 48 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_RFC_GP2 = + 49 << CC2650_IOC_IOCFGX_PORT_ID_POS, + CC2650_IOC_RFC_GP3 = + 50 << CC2650_IOC_IOCFGX_PORT_ID_POS + /* Reserved */ +}; + +/* IOSTR (drive strength) values available */ +enum CC2650_IOC_IOSTR { + CC2650_IOC_AUTO_DRIVE_STRENGTH = + 0 << CC2650_IOC_IOCFGX_IOSTR_POS, + CC2650_IOC_MIN_DRIVE_STRENGTH = + 1 << CC2650_IOC_IOCFGX_IOSTR_POS, + CC2650_IOC_MED_DRIVE_STRENGTH = + 2 << CC2650_IOC_IOCFGX_IOSTR_POS, + CC2650_IOC_MAX_DRIVE_STRENGTH = + 3 << CC2650_IOC_IOCFGX_IOSTR_POS +}; + +/* IOCURR (IO current) values available */ +enum CC2650_IOC_IOCURR { + CC2650_IOC_LOW_CURRENT_MODE = + 0 << CC2650_IOC_IOCFGX_IOCURR_POS, + CC2650_IOC_HIGH_CURRENT_MODE = + 1 << CC2650_IOC_IOCFGX_IOCURR_POS, + CC2650_IOC_EXTENDED_CURRENT_MODE = + 2 << CC2650_IOC_IOCFGX_IOCURR_POS +}; + +/* SLEW_RED (slew rate) values available */ +enum CC2650_IOC_SLEW_RED { + CC2650_IOC_NORMAL_SLEW_RATE = + 0 << CC2650_IOC_IOCFGX_SLEW_RED_POS, + CC2650_IOC_REDUCED_SLEW_RATE = + 1 << CC2650_IOC_IOCFGX_SLEW_RED_POS +}; + +/* PULL_CTL (pull-* modes) values available */ +enum CC2650_IOC_PULL_CTL { + CC2650_IOC_PULL_DOWN = + 1 << CC2650_IOC_IOCFGX_PULL_CTL_POS, + CC2650_IOC_PULL_UP = + 2 << CC2650_IOC_IOCFGX_PULL_CTL_POS, + CC2650_IOC_NO_PULL = + 3 << CC2650_IOC_IOCFGX_PULL_CTL_POS +}; + +/* EDGE_DET (edge detection) values available */ +enum CC2650_IOC_EDGE_DET { + CC2650_IOC_NO_EDGE_DET = + 0 << CC2650_IOC_IOCFGX_EDGE_DET_POS, + CC2650_IOC_NEG_EDGE_DET = + 1 << CC2650_IOC_IOCFGX_EDGE_DET_POS, + CC2650_IOC_POS_EDGE_DET = + 2 << CC2650_IOC_IOCFGX_EDGE_DET_POS, + CC2650_IOC_NEG_AND_POS_EDGE_DET = + 3 << CC2650_IOC_IOCFGX_EDGE_DET_POS +}; + +/* IOMODE values available */ +enum CC2650_IOC_IOMODE { + CC2650_IOC_NORMAL_IO = + 0 << CC2650_IOC_IOCFGX_IOMODE_POS, + CC2650_IOC_INVERTED_IO = + 1 << CC2650_IOC_IOCFGX_IOMODE_POS, + CC2650_IOC_OPEN_DRAIN_IO = + 4 << CC2650_IOC_IOCFGX_IOMODE_POS, + CC2650_IOC_OPEN_DRAIN_INVERTED_IO = + 5 << CC2650_IOC_IOCFGX_IOMODE_POS, + CC2650_IOC_OPEN_SOURCE_IO = + 6 << CC2650_IOC_IOCFGX_IOMODE_POS, + CC2650_IOC_OPEN_SOURCE_INVERTED_IO = + 7 << CC2650_IOC_IOCFGX_IOMODE_POS +}; + +/* WU_CFG (Wake-up control) values available */ +enum CC2650_IOC_WU_CFG { +/* Values' meaning change with PORT_ID, so here we only + * give very generic names... + */ + CC2650_IOC_WAKE_UP_0 = + 0 << CC2650_IOC_IOCFGX_WU_CFG_POS, + CC2650_IOC_WAKE_UP_1 = + 1 << CC2650_IOC_IOCFGX_WU_CFG_POS, + CC2650_IOC_WAKE_UP_2 = + 2 << CC2650_IOC_IOCFGX_WU_CFG_POS, + CC2650_IOC_WAKE_UP_3 = + 3 << CC2650_IOC_IOCFGX_WU_CFG_POS +}; + +/* IE (Input control) values available */ +enum CC2650_IOC_IE { + CC2650_IOC_INPUT_DISABLED = + 0 << CC2650_IOC_IOCFGX_IE_POS, + CC2650_IOC_INPUT_ENABLED = + 1 << CC2650_IOC_IOCFGX_IE_POS +}; + +/* HYST_EN (Hysteresis control) values available */ +enum CC2650_IOC_HYST_EN { + CC2650_IOC_HYSTERESIS_DISABLED = + 0 << CC2650_IOC_IOCFGX_HYST_EN_POS, + CC2650_IOC_HYSTERESIS_ENABLED = + 1 << CC2650_IOC_IOCFGX_HYST_EN_POS +}; + +#endif /* _CC2650_IOC_H_ */ diff --git a/arch/arm/soc/ti_simplelink/cc2650/include/prcm.h b/arch/arm/soc/ti_simplelink/cc2650/include/prcm.h new file mode 100644 index 00000000000000..472cf03eb96c15 --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/include/prcm.h @@ -0,0 +1,108 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Offsets for the Power, Reset, and Clock Management module + * registers, in the CC2650 System on Chip. + */ + + +#ifndef _CC2650_PRCM_H_ +#define _CC2650_PRCM_H_ + +/* Registers */ + +enum CC2650_PRCM_Registers { + CC2650_PRCM_CLKLOADCTL = 0x28, + CC2650_PRCM_SECDMACLKGR = 0x3C, + CC2650_PRCM_GPIOCLKGR = 0x48, + CC2650_PRCM_UARTCLKGR = 0x6C, + CC2650_PRCM_UARTCLKGS = 0x70, + CC2650_PRCM_UARTCLKGDS = 0x74, + CC2650_PRCM_PDCTL0 = 0x12C, + CC2650_PRCM_PDSTAT0 = 0x140 +}; + + +/* Register-specific bits */ + +/* CLKLOADCTL */ +enum CC2650_PRCM_CLKLOADCT_POS { + CC2650_PRCM_CLKLOADCTL_LOAD_POS = 0, + CC2650_PRCM_CLKLOADCTL_LOAD_DONE_POS = 1 +}; + +enum CC2650_PRCM_CLKLOADCTL_MASK { + CC2650_PRCM_CLKLOADCTL_LOAD_MASK = 0x00000001, + CC2650_PRCM_CLKLOADCTL_LOAD_DONE_MASK = 0x00000002 +}; + +/* SECDMACLKGR */ +enum CC2650_PRCM_SECDMACLKGR_POS { + CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_POS = 1 +}; + +enum CC2650_PRCM_SECDMACLKGR_MASK { + CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_MASK = 0x00000002 +}; + +/* GPIOCLKGR */ +enum CC2650_PRCM_GPIOCLKGR_POS { + CC2650_PRCM_GPIOCLKGR_CLK_EN_POS = 0 +}; + +enum CC2650_PRCM_GPIOCLKGR_MASK { + CC2650_PRCM_GPIOCLKGR_CLK_EN_MASK = 0x00000001 +}; + +/* UARTCLKGR */ +enum CC2650_PRCM_UARTCLKGR_POS { + CC2650_PRCM_UARTCLKGR_CLK_EN_POS = 0 +}; + +enum CC2650_PRCM_UARTCLKGR_MASK { + CC2650_PRCM_UARTCLKGR_CLK_EN_MASK = 0x00000001 +}; + +/* UARTCLKGS */ +enum CC2650_PRCM_UARTCLKGS_POS { + CC2650_PRCM_UARTCLKGS_CLK_EN_POS = 0 +}; + +enum CC2650_PRCM_UARTCLKGS_MASK { + CC2650_PRCM_UARTCLKGS_CLK_EN_MASK = 0x00000001 +}; + +/* UARTCLKGDS */ +enum CC2650_PRCM_UARTCLKGDS_POS { + CC2650_PRCM_UARTCLKGDS_CLK_EN_POS = 0 +}; + +enum CC2650_PRCM_UARTCLKGDS_MASK { + CC2650_PRCM_UARTCLKGDS_CLK_EN_MASK = 0x00000001 +}; + +/* PDCTL0 */ +enum CC2650_PRCM_PDCTL0_POS { + CC2650_PRCM_PDCTL0_SERIAL_ON_POS = 1, + CC2650_PRCM_PDCTL0_PERIPH_ON_POS = 2 +}; + +enum CC2650_PRCM_PDCTL0_MASK { + CC2650_PRCM_PDCTL0_SERIAL_ON_MASK = 0x00000002, + CC2650_PRCM_PDCTL0_PERIPH_ON_MASK = 0x00000004 +}; + +/* PDSTAT0 */ +enum CC2650_PRCM_PDSTAT0_POS { + CC2650_PRCM_PDSTAT0_RFC_ON_POS = 0, + CC2650_PRCM_PDSTAT0_SERIAL_ON_POS = 1, + CC2650_PRCM_PDSTAT0_PERIPH_ON_POS = 2 +}; + +enum CC2650_PRCM_PDSTAT0_MASK { + CC2650_PRCM_PDSTAT0_RFC_ON_MASK = 0x00000001, + CC2650_PRCM_PDSTAT0_SERIAL_ON_MASK = 0x00000002, + CC2650_PRCM_PDSTAT0_PERIPH_ON_MASK = 0x00000004 +}; + +#endif /* _CC2650_PRCM_H_ */ diff --git a/arch/arm/soc/ti_simplelink/cc2650/linker.ld b/arch/arm/soc/ti_simplelink/cc2650/linker.ld new file mode 100644 index 00000000000000..3929e3c5d6add8 --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/linker.ld @@ -0,0 +1,7 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * linker.ld - Linker command/script file + */ + +#include diff --git a/arch/arm/soc/ti_simplelink/cc2650/soc.c b/arch/arm/soc/ti_simplelink/cc2650/soc.c new file mode 100644 index 00000000000000..f8eec419a5de5e --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/soc.c @@ -0,0 +1,146 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Basic initialization for the CC2650 System on Chip. + */ + + +#include +#include +#include + +#include "soc.h" + + +#define CCFG_SIZE 88 + +/* The bootloader of the SoC (in ROM) reads configuration + * data (CCFG) at a fixed address (last page of flash). + * The most notable information being whether to run the + * code stored in flash or not. + * + * We put configuration data in a specific section so that + * the linker script can map it accordingly. + */ +const u32_t +__ti_ccfg_section +ti_ccfg[CCFG_SIZE / sizeof(u32_t)] = { + 0x00008001, /* EXT_LF_CLK: default values */ + 0xFF13FFFF, /* MODE_CONF_1: default values */ + 0x0058FFFF, /* SIZE_AND_DIS_FLAGS: 88 bytes long, no external osc. */ + 0xFFFFFFFF, /* MODE_CONF: default values */ + 0xFFFFFFFF, /* VOLT_LOAD_0: default values */ + 0xFFFFFFFF, /* VOLT_LOAD_1: default values */ + 0xFFFFFFFF, /* RTC_OFFSET: default values */ + 0xFFFFFFFF, /* FREQ_OFFSET: default values */ + 0xFFFFFFFF, /* IEEE_MAC_0: use MAC address from FCFG */ + 0xFFFFFFFF, /* IEEE_MAC_1: use MAC address from FCFG */ + 0xFFFFFFFF, /* IEEE_BLE_0: use BLE address from FCFG */ + 0xFFFFFFFF, /* IEEE_BLE_1: use BLE address from FCFG */ + /* BL_CONFIG: disable backdoor and bootloader, + * default pin, default active level (high) + */ + CC2650_CCFG_BACKDOOR_DISABLED | + (0xFF << CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_POS) | + (0x1 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS) | + 0x00FE0000 | /* reserved */ + CC2650_CCFG_BOOTLOADER_DISABLED, + 0xFFFFFFFF, /* ERASE_CONF: default values (banks + chip erase) */ + /* CCFG_TI_OPTIONS: disable TI failure analysis */ + CC2650_CCFG_TI_FA_DISABLED | + 0xFFFFFF00, /* reserved */ + 0xFFC5C5C5, /* CCFG_TAP_DAP_0: default values */ + 0xFFC5C5C5, /* CCFG_TAP_DAP_1: default values */ + /* IMAGE_VALID_CONF: authorize program on flash to run */ + CC2650_CCFG_IMAGE_IS_VALID, + /* Make all flash chip programmable + erasable + * (which is default) + */ + 0xFFFFFFFF, /* CCFG_PROT_31_0 */ + 0xFFFFFFFF, /* CCFG_PROT_61_32 */ + 0xFFFFFFFF, /* CCFG_PROT_95_64 */ + 0xFFFFFFFF /* CCFG_PROT_127_96 */ +}; + +/* PRCM Registers */ +static const u32_t clkloadctl = + REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, + CC2650_PRCM_CLKLOADCTL); +static const u32_t secdmaclkgr = + REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, + CC2650_PRCM_SECDMACLKGR); +static const u32_t gpioclkgr = + REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, + CC2650_PRCM_GPIOCLKGR); +static const u32_t pdctl0 = + REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, + CC2650_PRCM_PDCTL0); +static const u32_t pdstat0 = + REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, + CC2650_PRCM_PDSTAT0); +static const u32_t uartclkgr = + REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, + CC2650_PRCM_UARTCLKGR); + +/* Setup power and clock for needed hardware modules. */ +static void setup_modules_prcm(void) +{ +#if defined(CONFIG_GPIO_CC2650) || \ + defined(CONFIG_CC2650_TRNG_RANDOM_GENERATOR) || \ + defined(CONFIG_SERIAL) + + /* Setup power */ +#if defined(CONFIG_GPIO_CC2650) || defined(CONFIG_CC2650_TRNG_RANDOM_GENERATOR) + sys_set_bit(pdctl0, CC2650_PRCM_PDCTL0_PERIPH_ON_POS); +#endif +#ifdef CONFIG_SERIAL + sys_set_bit(pdctl0, CC2650_PRCM_PDCTL0_SERIAL_ON_POS); +#endif + + /* Setup clocking */ +#ifdef CONFIG_GPIO_CC2650 + sys_set_bit(gpioclkgr, CC2650_PRCM_GPIOCLKGR_CLK_EN_POS); +#endif +#ifdef CONFIG_CC2650_TRNG_RANDOM_GENERATOR + sys_set_bit(secdmaclkgr, CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_POS); +#endif +#ifdef CONFIG_SERIAL + sys_set_bit(uartclkgr, CC2650_PRCM_UARTCLKGR_CLK_EN_POS); +#endif + /* Reload clocking configuration for device */ + sys_set_bit(clkloadctl, CC2650_PRCM_CLKLOADCTL_LOAD_POS); + + /* Wait for power to be completely on, to avoid bus faults + * when accessing modules' registers. + */ +#if defined(CONFIG_GPIO_CC2650) || defined(CONFIG_CC2650_TRNG_RANDOM_GENERATOR) + while (!(sys_read32(pdstat0) & + BIT(CC2650_PRCM_PDSTAT0_PERIPH_ON_POS))) { + continue; + } +#endif +#if defined(CONFIG_SERIAL) + while (!(sys_read32(pdstat0) & + BIT(CC2650_PRCM_PDSTAT0_SERIAL_ON_POS))) { + continue; + } +#endif + +#endif +} + +static int ti_cc2650(struct device *dev) +{ + ARG_UNUSED(dev); + + NMI_INIT(); + setup_modules_prcm(); + return 0; +} + +SYS_INIT(ti_cc2650, PRE_KERNEL_1, 0); + +int bit_is_set(u32_t reg, u8_t bit) +{ + return sys_read32(reg) & BIT(bit); +} diff --git a/arch/arm/soc/ti_simplelink/cc2650/soc.h b/arch/arm/soc/ti_simplelink/cc2650/soc.h new file mode 100644 index 00000000000000..bcbbc84f00c806 --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc2650/soc.h @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * General header for the CC2650 System on Chip. + */ + + +#ifndef _CC2650_SOC_H_ +#define _CC2650_SOC_H_ + +#include +#include "include/ccfg.h" +#include "include/gpio.h" +#include "include/ioc.h" +#include "include/prcm.h" + + +/* Helper functions and macros */ + +#define REG_ADDR(Base, Offset) (u32_t)(Base + (u32_t)Offset) + +int bit_is_set(u32_t reg, u8_t bit); + + +#endif /* _CC2650_SOC_H_ */ diff --git a/dts/arm/ti/cc2650.dtsi b/dts/arm/ti/cc2650.dtsi new file mode 100644 index 00000000000000..bb70c71d6ad4da --- /dev/null +++ b/dts/arm/ti/cc2650.dtsi @@ -0,0 +1,66 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Device Tree include file for CC2650 SoC from Texas Instruments. + */ + +#include "armv7-m.dtsi" + +/ { + soc { + cpus { + cpu@0 { + compatible = "arm,cortex-m3"; + }; + }; + + sram0: memory { + compatible = "sram"; + reg = <0x20000000 0x5000>; + }; + + flash0: serial-flash { + compatible = "serial-flash"; + reg = <0x0 0x20000>; + }; + + gpioa: gpio@40022000 { + compatible = "ti,cc2650-gpio"; + reg = <0x40022000 0xE4>; + interrupts = <0 0>; + zephyr,irq-prio = <0>; + status = "disabled"; + + gpio-controller; + #gpio-cells = <1>; + }; + + pinmux_a: pinmux@40081000 { + compatible = "ti,cc2650-pinmux"; + reg = <0x40081000 0x80>; + }; + + prcm0: prcm@40082000 { + compatible = "ti,cc2650-prcm"; + reg = <0x40082000 0x228>; + }; + + trng0: trng@40028000 { + compatible = "ti,cc2650-trng"; + reg = <0x40028000 0x1FFC>; + interrupts = <33 0>; + status = "disabled"; + }; + + uart0: uart@40001000 { + compatible = "ti,stellaris-uart"; + reg = <0x40001000 0x4C>; + interrupts = <5 0>, <6 0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/yaml/ti,cc2650-prcm.yaml b/dts/arm/yaml/ti,cc2650-prcm.yaml new file mode 100644 index 00000000000000..529ecc1586e3d6 --- /dev/null +++ b/dts/arm/yaml/ti,cc2650-prcm.yaml @@ -0,0 +1,22 @@ +--- +# SPDX-License-Identifier: Apache-2.0 +title: TI CC2650 PRCM +version: 0.1 + +description: > + This binding gives a base representation of the TI CC2650 + Power, Reset, and Clock control Module. + +properties: + - compatible: + type: string + category: required + description: compatible strings + constraint: "ti,cc2650-prcm" + + - reg: + type: array + description: mmio register space + generation: define + category: required +... From 4b1667448ab1053a6c0ab5052b84303a205887d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Geoffrey=20Le=20Gourri=C3=A9rec?= Date: Fri, 16 Jun 2017 17:42:05 +0200 Subject: [PATCH 11/29] sensortag: Add TI's SensorTag board. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for TI's SensorTag board, which uses a CC2650 SoC. Signed-off-by: Geoffrey Le Gourriérec --- boards/arm/cc2650_sensortag/Kconfig | 8 +++ boards/arm/cc2650_sensortag/Kconfig.board | 8 +++ boards/arm/cc2650_sensortag/Kconfig.defconfig | 11 ++++ boards/arm/cc2650_sensortag/Makefile | 4 ++ boards/arm/cc2650_sensortag/board.h | 58 +++++++++++++++++++ .../cc2650_sensortag_defconfig | 46 +++++++++++++++ boards/arm/cc2650_sensortag/pinmux.c | 43 ++++++++++++++ dts/arm/Makefile | 2 +- dts/arm/cc2650_sensortag.dts | 37 ++++++++++++ dts/arm/cc2650_sensortag.fixup | 8 +++ dts/arm/ti/cc2650.dtsi | 1 + 11 files changed, 225 insertions(+), 1 deletion(-) create mode 100644 boards/arm/cc2650_sensortag/Kconfig create mode 100644 boards/arm/cc2650_sensortag/Kconfig.board create mode 100644 boards/arm/cc2650_sensortag/Kconfig.defconfig create mode 100644 boards/arm/cc2650_sensortag/Makefile create mode 100644 boards/arm/cc2650_sensortag/board.h create mode 100644 boards/arm/cc2650_sensortag/cc2650_sensortag_defconfig create mode 100644 boards/arm/cc2650_sensortag/pinmux.c create mode 100644 dts/arm/cc2650_sensortag.dts create mode 100644 dts/arm/cc2650_sensortag.fixup diff --git a/boards/arm/cc2650_sensortag/Kconfig b/boards/arm/cc2650_sensortag/Kconfig new file mode 100644 index 00000000000000..9500cc0f3869aa --- /dev/null +++ b/boards/arm/cc2650_sensortag/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Kconfig - TI CC2650 SensorTag configuration +# + +if BOARD_CC2650_SENSORTAG + +endif # BOARD_CC2650_SENSORTAG diff --git a/boards/arm/cc2650_sensortag/Kconfig.board b/boards/arm/cc2650_sensortag/Kconfig.board new file mode 100644 index 00000000000000..9567ae64bd996c --- /dev/null +++ b/boards/arm/cc2650_sensortag/Kconfig.board @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Kconfig - TI SimpleLink CC2650 SensorTag Board +# + +config BOARD_CC2650_SENSORTAG + bool "TI CC2650 SensorTag" + depends on SOC_CC2650 diff --git a/boards/arm/cc2650_sensortag/Kconfig.defconfig b/boards/arm/cc2650_sensortag/Kconfig.defconfig new file mode 100644 index 00000000000000..50afc605789977 --- /dev/null +++ b/boards/arm/cc2650_sensortag/Kconfig.defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Kconfig - TI CC2650 SensorTag board configuration +# + +if BOARD_CC2650_SENSORTAG + +config BOARD + default cc2650_sensortag + +endif # BOARD_CC2650_SENSORTAG diff --git a/boards/arm/cc2650_sensortag/Makefile b/boards/arm/cc2650_sensortag/Makefile new file mode 100644 index 00000000000000..16f5448ec87858 --- /dev/null +++ b/boards/arm/cc2650_sensortag/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Temporary solution: always launch pinmux init +obj-y += pinmux.o diff --git a/boards/arm/cc2650_sensortag/board.h b/boards/arm/cc2650_sensortag/board.h new file mode 100644 index 00000000000000..2adc914cf75da3 --- /dev/null +++ b/boards/arm/cc2650_sensortag/board.h @@ -0,0 +1,58 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Board-specific information for Texas Instruments' + * SensorTag device. + */ + + +#ifndef _CC2650_SENSORTAG_BOARD_H_ +#define _CC2650_SENSORTAG_BOARD_H_ + +/* Match a feature on the board to an I/O pin + * (DIOx in local jargon) + */ +#define SENSORTAG_BUTTON2 0 +#define SENSORTAG_TMP_RDY 1 +#define SENSORTAG_AUDIO_D 2 +#define SENSORTAG_REED 3 +#define SENSORTAG_BUTTON1 4 +#define SENSORTAG_SDA 5 +#define SENSORTAG_SCL 6 +#define SENSORTAG_MPU_INT 7 +#define SENSORTAG_SDA_HP 8 +#define SENSORTAG_SCL_HP 9 +#define SENSORTAG_LED1 10 +#define SENSORTAG_DP7 11 +#define SENSORTAG_AUDIO_CLK SENSORTAG_DP7 +#define SENSORTAG_MPU_PWR 12 +#define SENSORTAG_MIC_PWR 13 +#define SENSORTAG_FLASH_CS 14 +#define SENSORTAG_LED2 15 +#define SENSORTAG_DP12 16 +#define SENSORTAG_AUDIO_FS SENSORTAG_DP12 +#define SENSORTAG_TDO SENSORTAG_DP12 +#define SENSORTAG_DP8 17 +#define SENSORTAG_SCLK SENSORTAG_DP8 +#define SENSORTAG_TDI SENSORTAG_DP8 +#define SENSORTAG_DP9 18 +#define SENSORTAG_MISO SENSORTAG_DP9 +#define SENSORTAG_DP10 19 +#define SENSORTAG_MOSI SENSORTAG_DP10 +#define SENSORTAG_DP11 20 +#define SENSORTAG_CSN SENSORTAG_DP11 +#define SENSORTAG_BUZZER 21 +#define SENSORTAG_DP6 22 +#define SENSORTAG_AUDIO_DO SENSORTAG_DP6 +#define SENSORTAG_DP2 23 +#define SENSORTAG_DP1 24 +#define SENSORTAG_DP0 25 +#define SENSORTAG_VDD 26 +#define SENSORTAG_DP3 27 +#define SENSORTAG_DP4 28 +#define SENSORTAG_UART_RX SENSORTAG_DP4 +#define SENSORTAG_DP5 29 +#define SENSORTAG_UART_TX SENSORTAG_DP5 +#define SENSORTAG_DP_D 30 + +#endif /* _CC2650_SENSORTAG_BOARD_H_ */ diff --git a/boards/arm/cc2650_sensortag/cc2650_sensortag_defconfig b/boards/arm/cc2650_sensortag/cc2650_sensortag_defconfig new file mode 100644 index 00000000000000..4926f74545141a --- /dev/null +++ b/boards/arm/cc2650_sensortag/cc2650_sensortag_defconfig @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: Apache-2.0 + +# General options + +CONFIG_HAS_DTS=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_FLASH=y +CONFIG_FLASH_BASE_ADDRESS=0x00000000 +CONFIG_SRAM_BASE_ADDRESS=0x20000000 +CONFIG_BOOTLOADER_SRAM_SIZE=0 +CONFIG_XIP=y +CONFIG_PRINTK=y + +# Platform-specific options + +CONFIG_ARM=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_BOARD_CC2650_SENSORTAG=y +CONFIG_SOC_FAMILY_TISIMPLELINK=y +CONFIG_SOC_SERIES_CC2650=y +CONFIG_SOC_CC2650=y + +# Pinmux driver +CONFIG_PINMUX=y +CONFIG_PINMUX_CC2650=y +CONFIG_PINMUX_CC2650_INIT_PRIO=1 + +# GPIO driver +CONFIG_GPIO=y +CONFIG_GPIO_CC2650=y +CONFIG_GPIO_CC2650_INIT_PRIO=0 + +# UART driver +CONFIG_SERIAL=y +CONFIG_SERIAL_HAS_DRIVER=y +CONFIG_UART_STELLARIS=y +CONFIG_UART_STELLARIS_PORT_0=y + +# Console driver +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Random number generator driver +CONFIG_RANDOM_GENERATOR=y +CONFIG_CC2650_TRNG_RANDOM_GENERATOR=y +CONFIG_CC2650_TRNG_IRQ_PRIO=0 diff --git a/boards/arm/cc2650_sensortag/pinmux.c b/boards/arm/cc2650_sensortag/pinmux.c new file mode 100644 index 00000000000000..b722f0445ea5be --- /dev/null +++ b/boards/arm/cc2650_sensortag/pinmux.c @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Board-specific pin multiplexing for Texas Instruments' + * SensorTag device. + * + * For now, this only setups a default configuration + * at initialization (not a real pinmux driver). + */ + +#include +#include +#include +#include + +#include "board.h" + + +static int sensortag_pinmux_init(struct device *dev) +{ + dev = device_get_binding(CONFIG_PINMUX_NAME); + + /* DIO10 is LED 1 */ + pinmux_pin_set(dev, SENSORTAG_LED1, CC2650_IOC_GPIO); + pinmux_pin_input_enable(dev, SENSORTAG_LED1, PINMUX_OUTPUT_ENABLED); + + /* DIO15 is LED 2 */ + pinmux_pin_set(dev, SENSORTAG_LED2, CC2650_IOC_GPIO); + pinmux_pin_input_enable(dev, SENSORTAG_LED2, PINMUX_OUTPUT_ENABLED); + + /* UART RX */ + pinmux_pin_set(dev, SENSORTAG_UART_RX, CC2650_IOC_MCU_UART0_RX); + pinmux_pin_input_enable(dev, SENSORTAG_UART_RX, PINMUX_INPUT_ENABLED); + + /* UART TX */ + pinmux_pin_set(dev, SENSORTAG_UART_TX, CC2650_IOC_MCU_UART0_TX); + pinmux_pin_input_enable(dev, SENSORTAG_UART_TX, PINMUX_OUTPUT_ENABLED); + + return 0; +} + +SYS_INIT(sensortag_pinmux_init, PRE_KERNEL_1, + CONFIG_PINMUX_INIT_PRIORITY); diff --git a/dts/arm/Makefile b/dts/arm/Makefile index 7df3c98877d258..f84c23bb68003c 100644 --- a/dts/arm/Makefile +++ b/dts/arm/Makefile @@ -41,6 +41,6 @@ dtb-$(CONFIG_BOARD_SAM_E70_XPLAINED) = sam_e70_xplained.dts_compiled dtb-$(CONFIG_BOARD_ARDUINO_DUE) = arduino_due.dts_compiled dtb-$(CONFIG_BOARD_SAM4S_XPLAINED) = sam4s_xplained.dts_compiled dtb-$(CONFIG_BOARD_OLIMEX_STM32_E407) = olimex_stm32_e407.dts_compiled - +dtb-$(CONFIG_BOARD_CC2650_SENSORTAG) = cc2650_sensortag.dts_compiled always := $(dtb-y) endif diff --git a/dts/arm/cc2650_sensortag.dts b/dts/arm/cc2650_sensortag.dts new file mode 100644 index 00000000000000..82c1e41f1d2540 --- /dev/null +++ b/dts/arm/cc2650_sensortag.dts @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include "ti/cc2650.dtsi" + +/ { + model = "TI CC2650 SensorTag"; + compatible = "ti,cc2650"; + + aliases { + gpio_a = &gpioa; + pinmux_a = &pinmux_a; + prcm0 = &prcm0; + trng0 = &trng0; + uart_0 = &uart0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&gpioa { + status = "ok"; +}; + +&trng0 { + status = "ok"; +}; + +&uart0 { + status = "ok"; + current-speed = <115200>; +}; + diff --git a/dts/arm/cc2650_sensortag.fixup b/dts/arm/cc2650_sensortag.fixup new file mode 100644 index 00000000000000..fc0383227d342d --- /dev/null +++ b/dts/arm/cc2650_sensortag.fixup @@ -0,0 +1,8 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +#define TI_STELLARIS_UART_4000C000_BASE_ADDRESS TI_STELLARIS_UART_40001000_BASE_ADDRESS +#define TI_STELLARIS_UART_4000C000_CURRENT_SPEED TI_STELLARIS_UART_40001000_CURRENT_SPEED +#define UART_STELLARIS_CLK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define TI_STELLARIS_UART_4000C000_IRQ_0 TI_STELLARIS_UART_40001000_IRQ_0 +#define TI_STELLARIS_UART_4000C000_IRQ_0_PRIORITY TI_STELLARIS_UART_40001000_IRQ_0_PRIORITY +#define TI_STELLARIS_UART_4000C000_LABEL TI_STELLARIS_UART_40001000_LABEL diff --git a/dts/arm/ti/cc2650.dtsi b/dts/arm/ti/cc2650.dtsi index bb70c71d6ad4da..7255f831ba9fcf 100644 --- a/dts/arm/ti/cc2650.dtsi +++ b/dts/arm/ti/cc2650.dtsi @@ -57,6 +57,7 @@ reg = <0x40001000 0x4C>; interrupts = <5 0>, <6 0>; status = "disabled"; + label = "UART_0"; }; }; }; From 7404dd1443840ce2059d2121fa0ccdbeb6b7072b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Geoffrey=20Le=20Gourri=C3=A9rec?= Date: Fri, 16 Jun 2017 17:42:06 +0200 Subject: [PATCH 12/29] cc2650: Add GPIO driver. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Geoffrey Le Gourriérec --- drivers/gpio/Kconfig | 2 + drivers/gpio/Kconfig.cc2650 | 26 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio_cc2650.c | 348 +++++++++++++++++++++++++++++++ dts/arm/yaml/ti,cc2650-gpio.yaml | 27 +++ 5 files changed, 404 insertions(+) create mode 100644 drivers/gpio/Kconfig.cc2650 create mode 100644 drivers/gpio/gpio_cc2650.c create mode 100644 dts/arm/yaml/ti,cc2650-gpio.yaml diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index be77e3c79e34ad..e84ae06e755fc9 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -61,4 +61,6 @@ source "drivers/gpio/Kconfig.pulpino" source "drivers/gpio/Kconfig.fe310" +source "drivers/gpio/Kconfig.cc2650" + endif # GPIO diff --git a/drivers/gpio/Kconfig.cc2650 b/drivers/gpio/Kconfig.cc2650 new file mode 100644 index 00000000000000..d091c6165d7362 --- /dev/null +++ b/drivers/gpio/Kconfig.cc2650 @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# GPIO configuration options for the CC2650 SoC (Texas Instruments). + +menuconfig GPIO_CC2650 + bool "TI CC2650 GPIO driver" + depends on GPIO && SOC_SERIES_CC2650 + default n + help + Enable the GPIO driver on boards equipped with TI CC2650. + +if GPIO_CC2650 + +# A single block of GPIO exist. + +config GPIO_CC2650_NAME + string + default "GPIO_0" + prompt "GPIO driver name." + +config GPIO_CC2650_INIT_PRIO + int + default 40 + prompt "GPIO driver initialization priority." + +endif # GPIO_CC2650 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 142eae1eadaead..ada9000fcd7d03 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_GPIO_CMSDK_AHB) += gpio_cmsdk_ahb.o obj-$(CONFIG_GPIO_CC32XX) += gpio_cc32xx.o obj-$(CONFIG_GPIO_PULPINO) += gpio_pulpino.o obj-$(CONFIG_GPIO_FE310) += gpio_fe310.o +obj-$(CONFIG_GPIO_CC2650) += gpio_cc2650.o diff --git a/drivers/gpio/gpio_cc2650.c b/drivers/gpio/gpio_cc2650.c new file mode 100644 index 00000000000000..de5cd896807c15 --- /dev/null +++ b/drivers/gpio/gpio_cc2650.c @@ -0,0 +1,348 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * GPIO driver for the CC2650 SOC from Texas Instruments. + */ + +#include +#include +#include +#include +#include +#include + +#include "gpio_utils.h" + + +struct gpio_cc2650_data { + u32_t pin_callback_enables; + sys_slist_t callbacks; +}; + +/* Pre-declarations */ +static int gpio_cc2650_init(struct device *dev); +static int gpio_cc2650_config(struct device *port, int access_op, + u32_t pin, int flags); +static int gpio_cc2650_write(struct device *port, int access_op, + u32_t pin, u32_t value); + +static int gpio_cc2650_read(struct device *port, int access_op, + u32_t pin, u32_t *value); +static int gpio_cc2650_manage_callback(struct device *port, + struct gpio_callback *callback, + bool set); +static int gpio_cc2650_enable_callback(struct device *port, + int access_op, + u32_t pin); +static int gpio_cc2650_disable_callback(struct device *port, + int access_op, + u32_t pin); +static u32_t gpio_cc2650_get_pending_int(struct device *dev); + +/* GPIO registers */ +static const u32_t doutset31_0 = + REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, + CC2650_GPIO_DOUTSET31_0); +static const u32_t doutclr31_0 = + REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, + CC2650_GPIO_DOUTCLR31_0); +static const u32_t din31_0 = + REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, + CC2650_GPIO_DIN31_0); +static const u32_t doe31_0 = + REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, + CC2650_GPIO_DOE31_0); +static const u32_t evflags31_0 = + REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, + CC2650_GPIO_EVFLAGS31_0); + +static struct gpio_cc2650_data gpio_cc2650_data = { + .pin_callback_enables = 0 +}; + +static const struct gpio_driver_api gpio_cc2650_funcs = { + .config = gpio_cc2650_config, + .write = gpio_cc2650_write, + .read = gpio_cc2650_read, + .manage_callback = gpio_cc2650_manage_callback, + .enable_callback = gpio_cc2650_enable_callback, + .disable_callback = gpio_cc2650_disable_callback, + .get_pending_int = gpio_cc2650_get_pending_int +}; + +DEVICE_AND_API_INIT(gpio_cc2650_0, CONFIG_GPIO_CC2650_NAME, + gpio_cc2650_init, &gpio_cc2650_data, NULL, + PRE_KERNEL_1, CONFIG_GPIO_CC2650_INIT_PRIO, + &gpio_cc2650_funcs); +static void disconnect(const int pin, u32_t *gpiodoe31_0, + u32_t *iocfg) +{ + *gpiodoe31_0 &= ~BIT(pin); + + *iocfg &= ~(CC2650_IOC_IOCFGX_PULL_CTL_MASK | + CC2650_IOC_IOCFGX_IE_MASK); + *iocfg |= CC2650_IOC_INPUT_DISABLED | + CC2650_IOC_NO_PULL; +} + +/* Configure a single pin. + * If any asked option is not implementable, rollback entirely to + * previous configuration. + * + * Note: For pin drive strength, the CC2650 devices only support + * symmetric sink/source capabilities. + * Thus, you may ONLY determine the common drive strength with + * GPIO *low output state* flags. Flags for *high output state* + * will be ignored. + */ +static int gpio_cc2650_config_pin(int pin, int flags) +{ + const u32_t iocfg = REG_ADDR(TI_CC2650_PINMUX_40081000_BASE_ADDRESS, + CC2650_IOC_IOCFG0 + 0x4 * pin); + u32_t iocfg_config = sys_read32(iocfg); + u32_t gpio_doe31_0_config = sys_read32(doe31_0); + + /* Reset all configurable fields to 0 */ + iocfg_config &= ~(CC2650_IOC_IOCFGX_IOSTR_MASK | + CC2650_IOC_IOCFGX_PULL_CTL_MASK | + CC2650_IOC_IOCFGX_EDGE_DET_MASK | + CC2650_IOC_IOCFGX_EDGE_IRQ_EN_MASK | + CC2650_IOC_IOCFGX_IOMODE_MASK | + CC2650_IOC_IOCFGX_IE_MASK | + CC2650_IOC_IOCFGX_HYST_EN_MASK); + + if (flags & GPIO_PIN_DISABLE) { + disconnect(pin, &gpio_doe31_0_config, &iocfg_config); + goto commit_config; + } + + if (flags & GPIO_DIR_OUT) { + gpio_doe31_0_config |= BIT(pin); + iocfg_config |= CC2650_IOC_INPUT_DISABLED; + } else { + gpio_doe31_0_config &= ~BIT(pin); + iocfg_config |= CC2650_IOC_INPUT_ENABLED; + } + + if (flags & GPIO_INT) { + if (!(flags & GPIO_INT_EDGE) && + !(flags & GPIO_INT_DOUBLE_EDGE)) { + /* Can't do level-based interrupt */ + /* Don't commit changes */ + return -ENOTSUP; + } + + iocfg_config |= BIT(CC2650_IOC_IOCFGX_EDGE_IRQ_EN_POS); + + if (flags & GPIO_INT_EDGE) { + if (flags & GPIO_INT_ACTIVE_HIGH) { + iocfg_config |= CC2650_IOC_POS_EDGE_DET; + } else { + iocfg_config |= CC2650_IOC_NEG_EDGE_DET; + } + } else if (flags & GPIO_INT_DOUBLE_EDGE) { + iocfg_config |= CC2650_IOC_NEG_AND_POS_EDGE_DET; + } + + if (flags & GPIO_INT_CLOCK_SYNC) { + /* Don't commit changes */ + return -ENOTSUP; + } + + if (flags & GPIO_INT_DEBOUNCE) { + iocfg_config |= CC2650_IOC_HYSTERESIS_ENABLED; + } else { + iocfg_config |= CC2650_IOC_HYSTERESIS_DISABLED; + } + } + + if (flags & GPIO_POL_INV) { + iocfg_config |= CC2650_IOC_INVERTED_IO; + } else { + iocfg_config |= CC2650_IOC_NORMAL_IO; + } + + if (flags & GPIO_PUD_NORMAL) { + iocfg_config |= CC2650_IOC_NO_PULL; + } else if (flags & GPIO_PUD_PULL_UP) { + iocfg_config |= CC2650_IOC_PULL_UP; + } else if (flags & GPIO_PUD_PULL_DOWN) { + iocfg_config |= CC2650_IOC_PULL_DOWN; + } + + /* Remember, we only look at GPIO_DS_*_LOW ! */ + if (flags & GPIO_DS_DISCONNECT_LOW) { + disconnect(pin, &gpio_doe31_0_config, &iocfg_config); + } + if (flags & GPIO_DS_DFLT_LOW) { + iocfg_config |= CC2650_IOC_MIN_DRIVE_STRENGTH; + } else { + iocfg_config |= CC2650_IOC_MAX_DRIVE_STRENGTH; + } + + /* Commit changes */ +commit_config: + sys_write32(iocfg_config, iocfg); + sys_write32(gpio_doe31_0_config, doe31_0); + return 0; +} + +static inline void gpio_cc2650_write_pin(int pin, u32_t value) +{ + value ? sys_write32(BIT(pin), doutset31_0) : + sys_write32(BIT(pin), doutclr31_0); +} + +static inline void gpio_cc2650_read_pin(int pin, u32_t *value) +{ + *value = sys_read32(din31_0) & BIT(pin); +} + +static void gpio_cc2650_isr(void *arg) +{ + struct device *dev = (struct device *)arg; + struct gpio_cc2650_data *data = dev->driver_data; + + const u32_t events = sys_read32(evflags31_0); + const u32_t call_mask = events & data->pin_callback_enables; + + /* Clear GPIO trigger events */ + u32_t evflags = sys_read32(evflags31_0); + + sys_write32(evflags | call_mask, evflags31_0); + + _gpio_fire_callbacks(&data->callbacks, dev, call_mask); +} + + +static int gpio_cc2650_init(struct device *dev) +{ + ARG_UNUSED(dev); + + /* ISR setup */ + IRQ_CONNECT(TI_CC2650_GPIO_40022000_IRQ_0, + TI_CC2650_GPIO_40022000_IRQ_0_PRIORITY, + gpio_cc2650_isr, DEVICE_GET(gpio_cc2650_0), + 0); + irq_enable(TI_CC2650_GPIO_40022000_IRQ_0); + + return 0; +} + +static int gpio_cc2650_config(struct device *port, int access_op, + u32_t pin, int flags) +{ + ARG_UNUSED(port); + + if (access_op == GPIO_ACCESS_BY_PIN) { + return gpio_cc2650_config_pin(pin, flags); + } + + const u32_t nb_pins = 32; + + for (u8_t i = 0; i < nb_pins; ++i) { + if (pin & 0x1 && + gpio_cc2650_config_pin(i, flags) == -ENOTSUP) { + /* The flags being treated the same for + * every pin, if we get here then it's + * necessarily the first pin on which we act. + * + * We expect gpio_cc2650_config_pin() to + * NOT commit its changes if any problem + * arises, thus we do nothing special here + * to implement rollback to previous + * configuration. + */ + return -ENOTSUP; + } + pin >>= 1; + } + return 0; +} + +static int gpio_cc2650_write(struct device *port, int access_op, + u32_t pin, u32_t value) +{ + ARG_UNUSED(port); + + if (access_op == GPIO_ACCESS_BY_PIN) { + gpio_cc2650_write_pin(pin, value); + } else { + const u32_t nb_pins = 32; + + for (u32_t i = 0; i < nb_pins; ++i) { + if (pin & 0x1) { + gpio_cc2650_write_pin(i, value); + } + pin >>= 1; + } + } + + return 0; +} + +static int gpio_cc2650_read(struct device *port, int access_op, + u32_t pin, u32_t *value) +{ + ARG_UNUSED(port); + + if (access_op == GPIO_ACCESS_BY_PIN) { + gpio_cc2650_read_pin(pin, value); + *value >>= pin; + } else { + const u32_t nb_pins = 32; + + for (u32_t i = 0; i < nb_pins; ++i) { + if (pin & 0x1) { + gpio_cc2650_read_pin(i, value); + } + pin >>= 1; + } + } + return 0; +} + +static int gpio_cc2650_manage_callback(struct device *port, + struct gpio_callback *callback, + bool set) +{ + struct gpio_cc2650_data *data = port->driver_data; + + _gpio_manage_callback(&data->callbacks, callback, set); + return 0; +} + +static int gpio_cc2650_enable_callback(struct device *port, + int access_op, + u32_t pin) +{ + struct gpio_cc2650_data *data = port->driver_data; + + if (access_op == GPIO_ACCESS_BY_PIN) { + data->pin_callback_enables |= BIT(pin); + } else { + data->pin_callback_enables |= pin; + } + return 0; +} + +static int gpio_cc2650_disable_callback(struct device *port, + int access_op, + u32_t pin) +{ + struct gpio_cc2650_data *data = port->driver_data; + + if (access_op == GPIO_ACCESS_BY_PIN) { + data->pin_callback_enables &= ~BIT(pin); + } else { + data->pin_callback_enables &= ~pin; + } + return 0; +} + +static u32_t gpio_cc2650_get_pending_int(struct device *dev) +{ + ARG_UNUSED(dev); + + return sys_read32(evflags31_0); +} diff --git a/dts/arm/yaml/ti,cc2650-gpio.yaml b/dts/arm/yaml/ti,cc2650-gpio.yaml new file mode 100644 index 00000000000000..f24f3bda966c5f --- /dev/null +++ b/dts/arm/yaml/ti,cc2650-gpio.yaml @@ -0,0 +1,27 @@ +--- +# SPDX-License-Identifier: Apache-2.0 +title: TI CC2650 GPIO +version: 0.1 + +description: > + This is a representation of the TI CC2650 GPIO node + +properties: + - compatible: + type: string + category: required + description: compatible strings + constraint: "ti,cc2650-gpio" + + - reg: + type: int + description: mmio register space + generation: define + category: required + + - interrupts: + type: compound + category: required + description: required interrupts + generation: define +... From c1ad307f953c8759dae84dc87216673796d7bfd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Geoffrey=20Le=20Gourri=C3=A9rec?= Date: Fri, 16 Jun 2017 17:42:07 +0200 Subject: [PATCH 13/29] cc2650: Add pinmux driver. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Geoffrey Le Gourriérec --- drivers/pinmux/Kconfig | 2 + drivers/pinmux/Kconfig.cc2650 | 16 +++ drivers/pinmux/Makefile | 1 + drivers/pinmux/pinmux_cc2650.c | 155 +++++++++++++++++++++++++++++ dts/arm/yaml/ti,cc2650-pinmux.yaml | 27 +++++ 5 files changed, 201 insertions(+) create mode 100644 drivers/pinmux/Kconfig.cc2650 create mode 100644 drivers/pinmux/pinmux_cc2650.c create mode 100644 dts/arm/yaml/ti,cc2650-pinmux.yaml diff --git a/drivers/pinmux/Kconfig b/drivers/pinmux/Kconfig index a9f9062fe1abc8..8f6b5348b4ebd6 100644 --- a/drivers/pinmux/Kconfig +++ b/drivers/pinmux/Kconfig @@ -54,4 +54,6 @@ source "drivers/pinmux/Kconfig.beetle" source "drivers/pinmux/Kconfig.fe310" +source "drivers/pinmux/Kconfig.cc2650" + endif # PINMUX diff --git a/drivers/pinmux/Kconfig.cc2650 b/drivers/pinmux/Kconfig.cc2650 new file mode 100644 index 00000000000000..db7b85a79f985e --- /dev/null +++ b/drivers/pinmux/Kconfig.cc2650 @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Kconfig for TI CC2650 SoC pinmux driver. + +config PINMUX_CC2650 + bool "Pinmux driver for CC2650 SoC" + depends on PINMUX && SOC_SERIES_CC2650 + select GPIO + select GPIO_CC2650 + help + Enable pin multiplexer for CC2650 SoC. + + For hardware reasons, the pinmux depends on the GPIO module + being activated; it must initialize *before* the pinmux does. + Please take care that the pinmux init priority value is *lower* + that the GPIO driver init priority. diff --git a/drivers/pinmux/Makefile b/drivers/pinmux/Makefile index 717eac16db45f2..2d5c2ebdf7e3a3 100644 --- a/drivers/pinmux/Makefile +++ b/drivers/pinmux/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_BOARD_OLIMEXINO_STM32) += stm32/pinmux_board_olimexino_stm32.o obj-$(CONFIG_BOARD_STM32_MINI_A15) += stm32/pinmux_board_stm32_mini_a15.o obj-$(CONFIG_PINMUX_QMSI) += pinmux_qmsi.o obj-$(CONFIG_PINMUX_FE310) += pinmux_fe310.o +obj-$(CONFIG_PINMUX_CC2650) += pinmux_cc2650.o # "runtime" pinmux obj-$(CONFIG_PINMUX_DEV) += dev/ diff --git a/drivers/pinmux/pinmux_cc2650.c b/drivers/pinmux/pinmux_cc2650.c new file mode 100644 index 00000000000000..64d89c8b13b988 --- /dev/null +++ b/drivers/pinmux/pinmux_cc2650.c @@ -0,0 +1,155 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Driver for the I/O controller (pinmux) for + * Texas Instrument's CC2650 SoC. + * + * For these SoCs, available pin functions are as follows: + * + * 0x00 - GPIO + * 0x07 - AON 32 Khz clock + * 0x08 - AUX IO + * 0x09 - SSI0 RX + * 0x0A - SSI0 TX + * 0x0B - SSI0 FSS + * 0x0C - SSI0 CLK + * 0x0D - I2C SDA + * 0x0E - I2C SCL + * 0x0F - UART0 RX + * 0x10 - UART0 TX + * 0x11 - UART0 CTS + * 0x12 - UART0 RTS + * 0x17 - Port event 0 + * 0x18 - Port event 1 + * 0x19 - Port event 2 + * 0x1A - Port event 3 + * 0x1B - Port event 4 + * 0x1C - Port event 5 + * 0x1D - Port event 6 + * 0x1E - Port event 7 + * 0x20 - CPU SWV + * 0x21 - SSI1 RX + * 0x22 - SSI1 TX + * 0x23 - SSI1 FSS + * 0x24 - SSI1 CLK + * 0x25 - I2S data 0 + * 0x26 - I2S data 1 + * 0x27 - I2S WCLK + * 0x28 - I2S BCLK + * 0x29 - I2S MCLK + * 0x2E - RF Core Trace + * 0x2F - RF Core data out 0 + * 0x30 - RF Core data out 1 + * 0x31 - RF Core data out 2 + * 0x32 - RF Core data out 3 + * 0x33 - RF Core data in 0 + * 0x34 - RF Core data in 1 + * 0x35 - RF Core SMI data link out + * 0x36 - RF Core SMI data link in + * 0x37 - RF Core SMI command link out + * 0x38 - RF Core SMI command link in + */ + +#include +#include +#include +#include +#include +#include +#include + + +#define IOCFG_REG(Func) \ + REG_ADDR(TI_CC2650_PINMUX_40081000_BASE_ADDRESS, \ + CC2650_IOC_IOCFG0 + 0x4 * Func) + +static int pinmux_cc2650_init(struct device *dev) +{ + /* Do nothing */ + ARG_UNUSED(dev); + return 0; +} + +static int pinmux_cc2650_set(struct device *dev, u32_t pin, + u32_t func) +{ + const u32_t iocfg = IOCFG_REG(pin); + u32_t conf = sys_read32(iocfg); + + conf &= ~CC2650_IOC_IOCFGX_PORT_ID_MASK; + conf |= func & CC2650_IOC_IOCFGX_PORT_ID_MASK; + sys_write32(conf, iocfg); + + return 0; +}; + +static int pinmux_cc2650_get(struct device *dev, u32_t pin, + u32_t *func) +{ + const u32_t iocfg = IOCFG_REG(pin); + u32_t conf = sys_read32(iocfg); + + *func = conf & CC2650_IOC_IOCFGX_PORT_ID_MASK; + return 0; +} + +static int pinmux_cc2650_pullup(struct device *dev, u32_t pin, + u8_t func) +{ + __ASSERT((func == PINMUX_PULLUP_ENABLE) | + (func == PINMUX_PULLUP_DISABLE), + "Pullup mode is invalid"); + + const u32_t iocfg = IOCFG_REG(pin); + u32_t conf = sys_read32(iocfg); + + conf &= ~CC2650_IOC_IOCFGX_PULL_CTL_MASK; + if (func == PINMUX_PULLUP_ENABLE) { + conf |= CC2650_IOC_PULL_UP; + } else { + conf |= CC2650_IOC_NO_PULL; + } + sys_write32(conf, iocfg); + + return 0; +} + +static int pinmux_cc2650_input(struct device *dev, u32_t pin, + u8_t func) +{ + __ASSERT((func == PINMUX_INPUT_ENABLED) | + (func == PINMUX_OUTPUT_ENABLED), + "I/O mode is invalid"); + + const u32_t iocfg = IOCFG_REG(pin); + const u32_t gpio_doe = TI_CC2650_GPIO_40022000_BASE_ADDRESS + + CC2650_GPIO_DOE31_0; + u32_t iocfg_conf = sys_read32(iocfg); + u32_t gpio_doe_conf = sys_read32(gpio_doe); + + iocfg_conf &= ~CC2650_IOC_IOCFGX_IE_MASK; + if (func == PINMUX_INPUT_ENABLED) { + iocfg_conf |= CC2650_IOC_INPUT_ENABLED; + gpio_doe_conf &= ~BIT(pin); + } else { + iocfg_conf |= CC2650_IOC_INPUT_DISABLED; + gpio_doe_conf |= BIT(pin); + } + sys_write32(iocfg_conf, iocfg); + sys_write32(gpio_doe_conf, gpio_doe); + + return 0; + +} + +const struct pinmux_driver_api pinmux_cc2650_funcs = { + .set = pinmux_cc2650_set, + .get = pinmux_cc2650_get, + .pullup = pinmux_cc2650_pullup, + .input = pinmux_cc2650_input +}; + +DEVICE_AND_API_INIT(pinmux_cc2650_0, CONFIG_PINMUX_NAME, + pinmux_cc2650_init, NULL, NULL, + PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY, + &pinmux_cc2650_funcs); diff --git a/dts/arm/yaml/ti,cc2650-pinmux.yaml b/dts/arm/yaml/ti,cc2650-pinmux.yaml new file mode 100644 index 00000000000000..e18362e403a69b --- /dev/null +++ b/dts/arm/yaml/ti,cc2650-pinmux.yaml @@ -0,0 +1,27 @@ +--- +# SPDX-License-Identifier: Apache-2.0 +title: TI CC2650 Pinmux +version: 0.1 + +description: > + This is a representation of the TI CC2650 pinmux node + +properties: + - compatible: + type: string + category: required + description: compatible strings + constraint: "ti,cc2650-pinmux" + + - reg: + type: int + description: mmio register space + generation: define + category: required + +cell_string: PINMUX + +"#cells": + - pin + - function +... From 1277f8fa251219b642d129dc3bad9dc244ef434e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Geoffrey=20Le=20Gourri=C3=A9rec?= Date: Fri, 16 Jun 2017 17:42:09 +0200 Subject: [PATCH 14/29] samples: gpio: Add support for SensorTag board. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add extra #defines in samples/drivers/gpio to test TI SensorTag board. Signed-off-by: Geoffrey Le Gourriérec --- samples/drivers/gpio/src/main.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/samples/drivers/gpio/src/main.c b/samples/drivers/gpio/src/main.c index 07ce642339d32d..b95cb192f68ccc 100644 --- a/samples/drivers/gpio/src/main.c +++ b/samples/drivers/gpio/src/main.c @@ -7,6 +7,18 @@ /** * @file Sample app to utilize GPIO on Arduino 101 and Arduino Due. * + * Sensortag CC2650 - ARM + * -------------------- + * + * LED1 is on DIO_10 + * LED2 is on DIO_15 + * BUTTON1 is on DIO_4 + * BUTTON2 is on DIO_0 + * + * This sample toogles LED1 and wait interrupt on BUTTON1. + * Note that an internet pull-up is set on BUTTON1 as the button + * only drives low when pressed. + * * Arduino 101 - x86 * -------------------- * @@ -122,6 +134,10 @@ #define GPIO_OUT_PIN 8 #define GPIO_INT_PIN 24 #define GPIO_NAME "GPIO_" +#elif defined(CONFIG_SOC_CC2650) +#define GPIO_OUT_PIN 10 +#define GPIO_INT_PIN 4 +#define GPIO_NAME "GPIO_" #endif #if defined(CONFIG_GPIO_DW_0) @@ -163,9 +179,17 @@ void main(void) } /* Setup GPIO input, and triggers on rising edge. */ +#ifdef CONFIG_SOC_CC2650 + ret = gpio_pin_configure(gpio_dev, GPIO_INT_PIN, + (GPIO_DIR_IN | GPIO_INT | + GPIO_INT_EDGE | GPIO_INT_ACTIVE_HIGH | + GPIO_INT_DEBOUNCE | GPIO_PUD_PULL_UP)); +#else ret = gpio_pin_configure(gpio_dev, GPIO_INT_PIN, - (GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE - | GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE)); + (GPIO_DIR_IN | GPIO_INT | + GPIO_INT_EDGE | GPIO_INT_ACTIVE_HIGH | + GPIO_INT_DEBOUNCE)); +#endif if (ret) { printk("Error configuring " GPIO_NAME "%d!\n", GPIO_INT_PIN); } From ddfd216513d228d4abbf330aa9b8bda7a10c9619 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 13 Jun 2017 09:44:41 -0500 Subject: [PATCH 15/29] boards: 96b_nitrogen: Add support for flash/debug with pyOCD Signed-off-by: Kumar Gala --- boards/arm/96b_nitrogen/Makefile.board | 6 ++++++ boards/arm/96b_nitrogen/doc/96b_nitrogen.rst | 19 +++++++++++-------- 2 files changed, 17 insertions(+), 8 deletions(-) create mode 100644 boards/arm/96b_nitrogen/Makefile.board diff --git a/boards/arm/96b_nitrogen/Makefile.board b/boards/arm/96b_nitrogen/Makefile.board new file mode 100644 index 00000000000000..5e13e3f0877b75 --- /dev/null +++ b/boards/arm/96b_nitrogen/Makefile.board @@ -0,0 +1,6 @@ +FLASH_SCRIPT = pyocd.sh +DEBUG_SCRIPT = pyocd.sh + +PYOCD_TARGET = nrf52 + +export FLASH_SCRIPT PYOCD_TARGET diff --git a/boards/arm/96b_nitrogen/doc/96b_nitrogen.rst b/boards/arm/96b_nitrogen/doc/96b_nitrogen.rst index cf6c25631c6243..434fce8ea2781a 100644 --- a/boards/arm/96b_nitrogen/doc/96b_nitrogen.rst +++ b/boards/arm/96b_nitrogen/doc/96b_nitrogen.rst @@ -267,22 +267,25 @@ and install a more recent version of pyOCD. Flashing an Application to 96Boards Nitrogen ============================================ -The sample application :ref:`hello_world` is being used in this tutorial: +This example uses the :ref:`hello_world` sample with the +:ref:`nxp_opensda_pyocd` tools. Use the ``make flash`` build target to build +your Zephyr application, invoke the pyOCD flash tool and program your Zephyr +application to flash. .. code-block:: console - $/samples/hello_world + $ cd + $ . zephyr-env.sh + $ cd samples/hello_world/ + $ make BOARD=96b_nitrogen -To build the Zephyr kernel and application, enter: +You can either flash the board by using the `make flash` target: .. code-block:: console - $ cd - $ source zephyr-env.sh - $ cd $ZEPHYR_BASE/samples/hello_world/ - $ make BOARD=96b_nitrogen + $ make flash -Connect the micro-USB cable to the 96Boards Nitrogen and to your computer. +or you can invoke the pyocd commands directly, as described below. Erase the flash memory in the nRF52832: From bd30f173a2ed83e96f316f769f4abda9b98ffe5f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 13 Jun 2017 14:16:43 -0500 Subject: [PATCH 16/29] scripts: bossa-flash.sh: fix variable usage We define a variable to pickup a default for the bossa binary, however we weren't using it. Lets do so now. Signed-off-by: Kumar Gala --- scripts/support/bossa-flash.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/support/bossa-flash.sh b/scripts/support/bossa-flash.sh index 348f59b2b4fcd9..0c1fee709cc63d 100755 --- a/scripts/support/bossa-flash.sh +++ b/scripts/support/bossa-flash.sh @@ -7,7 +7,7 @@ BOSSAC_CMD="${BOSSAC:-bossac}" if [ `uname` = "Linux" ]; then stty -F /dev/ttyACM0 raw ispeed 1200 ospeed 1200 cs8 \ -cstopb ignpar eol 255 eof 255 - ${BOSSAC} -R -e -w -v -b "${O}/${KERNEL_BIN_NAME}" + ${BOSSAC_CMD} -R -e -w -v -b "${O}/${KERNEL_BIN_NAME}" else echo "CAUTION: No flash tool for your host system found!" fi From 942c1fc619138dea4f0f6cd004b53fc401b92958 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 15 Jun 2017 08:59:13 -0500 Subject: [PATCH 17/29] scripts: pyocd.sh: Add support for passing board_id to pyocd commands If we have more than one board of a given type we need to be able to specify the board_id to select which specific board that the pyocd command should target. Introduce an environment variable PYOCD_BOARD_ID to we can set that will get passed to the pyocd command that needs it. Here's an example: $ make -C samples/hello_world/ BOARD=frdm_k64f flash PYOCD_BOARD_ID=1234 Signed-off-by: Kumar Gala --- scripts/support/pyocd.sh | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/scripts/support/pyocd.sh b/scripts/support/pyocd.sh index 11f4fdc1203496..be9fcc0d638573 100755 --- a/scripts/support/pyocd.sh +++ b/scripts/support/pyocd.sh @@ -9,6 +9,11 @@ BIN_NAME=${O}/${KERNEL_BIN_NAME} ELF_NAME=${O}/${KERNEL_ELF_NAME} GDB_PORT=${GDB_PORT:-3333} +PYOCD_BOARD_ID_ARG="" +if [ -n "${PYOCD_BOARD_ID}" ]; then + PYOCD_BOARD_ID_ARG="-b ${PYOCD_BOARD_ID}" +fi + test_config() { if ! which ${PYOCD_FLASHTOOL} >/dev/null 2>&1; then echo "Error: Unable to locate pyOCD flash tool: ${PYOCD_FLASHTOOL}" @@ -33,7 +38,7 @@ do_flash() { # flash device with specified image echo "Flashing Target Device" - ${PYOCD_FLASHTOOL} -t ${PYOCD_TARGET} ${BIN_NAME} + ${PYOCD_FLASHTOOL} -t ${PYOCD_TARGET} ${PYOCD_BOARD_ID_ARG} ${BIN_NAME} } @@ -59,7 +64,7 @@ do_debugserver() { SETSID= fi echo "pyOCD GDB server running on port ${GDB_PORT}" - ${SETSID} ${PYOCD_GDBSERVER} -p ${GDB_PORT} -t ${PYOCD_TARGET} + ${SETSID} ${PYOCD_GDBSERVER} -p ${GDB_PORT} -t ${PYOCD_TARGET} ${PYOCD_BOARD_ID_ARG} } CMD="$1" From 1ec8ac74051a439f49e8c17d1ff737d0eed0c6fa Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 15 Jun 2017 08:59:36 -0500 Subject: [PATCH 18/29] board: frdm_k64f: allow overriding default debug/flash scripts As there are multiple ways to flash or debug (pyOCD or openOCD) allow the user to override the default. Signed-off-by: Kumar Gala --- boards/arm/frdm_k64f/Makefile.board | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/arm/frdm_k64f/Makefile.board b/boards/arm/frdm_k64f/Makefile.board index 4849365ff2f6b0..ea49c71288a2de 100644 --- a/boards/arm/frdm_k64f/Makefile.board +++ b/boards/arm/frdm_k64f/Makefile.board @@ -1,5 +1,5 @@ -FLASH_SCRIPT = pyocd.sh -DEBUG_SCRIPT = pyocd.sh +FLASH_SCRIPT ?= pyocd.sh +DEBUG_SCRIPT ?= pyocd.sh OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}" OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}" From 091176ef4f2da4bd523549acd07d75c1ff1827c9 Mon Sep 17 00:00:00 2001 From: Piotr Mienkowski Date: Wed, 14 Jun 2017 23:40:31 +0200 Subject: [PATCH 19/29] boards: sam_e70_xplained: allow flashing via JTAG header Allow to use an external debug adapter such as J-Link or ULINK connected to a 20-pin JTAG header to flash the image. SWD is the actual protocol used by the debug interface. Signed-off-by: Piotr Mienkowski --- .../sam_e70_xplained/doc/sam_e70_xplained.rst | 10 +++++++ .../arm/sam_e70_xplained/support/openocd.cfg | 27 ++++++++++++++----- 2 files changed, 31 insertions(+), 6 deletions(-) diff --git a/boards/arm/sam_e70_xplained/doc/sam_e70_xplained.rst b/boards/arm/sam_e70_xplained/doc/sam_e70_xplained.rst index f62c13917a1986..ef3c8789cfffbb 100644 --- a/boards/arm/sam_e70_xplained/doc/sam_e70_xplained.rst +++ b/boards/arm/sam_e70_xplained/doc/sam_e70_xplained.rst @@ -141,6 +141,16 @@ Flashing The command will also verify that the image was programmed correctly, reset the board and run the Zephyr application. + You can flash the image using an external debug adapter such as J-Link or + ULINK, connected to the 20-pin JTAG header. Supply the name of the debug + adapter (e.g., `jlink`) to the make command via an OPENOCD_INTERFACE + variable. OpenOCD will look for the appropriate interface configuration in an + `interface/$(OPENOCD_INTERFACE).cfg` file on its internal search path. + + .. code-block:: console + + $ make BOARD=sam_e70_xplained OPENOCD_INTERFACE=jlink flash + You should see "Hello World!" in your terminal. Debugging diff --git a/boards/arm/sam_e70_xplained/support/openocd.cfg b/boards/arm/sam_e70_xplained/support/openocd.cfg index f7e7b78e58fcd2..8437e84451025b 100644 --- a/boards/arm/sam_e70_xplained/support/openocd.cfg +++ b/boards/arm/sam_e70_xplained/support/openocd.cfg @@ -1,12 +1,27 @@ -source [find board/atmel_same70_xplained.cfg] +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the EDBG chip + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME atsame70q21 + +source [find target/atsamv.cfg] + +reset_config srst_only $_TARGETNAME configure -event gdb-attach { - echo "Debugger attaching: halting execution" - reset halt - gdb_breakpoint_override hard + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard } $_TARGETNAME configure -event gdb-detach { - echo "Debugger detaching: resuming execution" - resume + echo "Debugger detaching: resuming execution" + resume } From c6c738906138071868f4a6e7a5b50e797f623274 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Tue, 23 May 2017 14:44:38 +0200 Subject: [PATCH 20/29] stm32cube: Fix warning when SPI LL API is compiled Current implementation of LL_SPI_TransmitData16 on F3/F7/L4 family generates following warning: "warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]" Besides being forbidden by rule, this cast is not needed, as register is 16 bits wide. Modification has been tested on L4 SoC. stm32yyxx_ll_spi.h being included in soc.h file, warning is generated at each compiled object, this commit allows a clean build. This issue is referenced in ST and tracked under reference 13359. Code will be updated on upcoming stm32cube updates. Change-Id: I3ca54a81d849d4852eca86b52b6825b60e18b752 Signed-off-by: Erwan Gouriou Signed-off-by: Neil Armstrong --- .../stm32f3xx/drivers/include/stm32f3xx_ll_spi.h | 2 +- .../stm32f7xx/drivers/include/stm32f7xx_ll_spi.h | 14 +++++++------- .../stm32l4xx/drivers/include/stm32l4xx_ll_spi.h | 14 +++++++------- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/ext/hal/st/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h b/ext/hal/st/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h index bdfc780cb1bb94..485a77494d6fc4 100644 --- a/ext/hal/st/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h +++ b/ext/hal/st/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h @@ -1388,7 +1388,7 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) */ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) { - *((__IO uint16_t *)&SPIx->DR) = TxData; + SPIx->DR = TxData; } /** diff --git a/ext/hal/st/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_spi.h b/ext/hal/st/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_spi.h index de709779189574..8c7abab32c58b4 100644 --- a/ext/hal/st/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_spi.h +++ b/ext/hal/st/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_spi.h @@ -1384,13 +1384,13 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) * @param SPIx SPI Instance * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) -{ - *((__IO uint16_t *)&SPIx->DR) = TxData; -} - -/** + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + SPIx->DR = TxData; +} + +/** * @} */ #if defined(USE_FULL_LL_DRIVER) diff --git a/ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h b/ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h index 29aad2d3958362..851106a6c16248 100644 --- a/ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h +++ b/ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h @@ -1384,13 +1384,13 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) * @param SPIx SPI Instance * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) -{ - *((__IO uint16_t *)&SPIx->DR) = TxData; -} - -/** + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + SPIx->DR = TxData; +} + +/** * @} */ #if defined(USE_FULL_LL_DRIVER) From fa633c0aa336ceedb6bc7e4e0f1aae13fa8fbd02 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Wed, 24 May 2017 14:56:48 +0200 Subject: [PATCH 21/29] stm32cube: build stm32xxx_ll_spi if CONFIG_SPI Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Neil Armstrong --- arch/arm/soc/st_stm32/stm32f3/soc.h | 1 + arch/arm/soc/st_stm32/stm32f4/soc.h | 1 + arch/arm/soc/st_stm32/stm32l4/soc.h | 1 + ext/hal/st/stm32cube/Kbuild | 3 +++ 4 files changed, 6 insertions(+) diff --git a/arch/arm/soc/st_stm32/stm32f3/soc.h b/arch/arm/soc/st_stm32/stm32f3/soc.h index 85bdd58cd9b9e7..3c39aafd48a099 100644 --- a/arch/arm/soc/st_stm32/stm32f3/soc.h +++ b/arch/arm/soc/st_stm32/stm32f3/soc.h @@ -57,6 +57,7 @@ enum stm32f3x_pin_config_mode { #include #include #include +#include #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ #endif /* !_ASMLANGUAGE */ diff --git a/arch/arm/soc/st_stm32/stm32f4/soc.h b/arch/arm/soc/st_stm32/stm32f4/soc.h index d611d1b07e5b6e..8954e5a72eab31 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc.h +++ b/arch/arm/soc/st_stm32/stm32f4/soc.h @@ -57,6 +57,7 @@ enum stm32f4x_pin_config_mode { #include #include #include +#include #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ #endif /* !_ASMLANGUAGE */ diff --git a/arch/arm/soc/st_stm32/stm32l4/soc.h b/arch/arm/soc/st_stm32/stm32l4/soc.h index 2b86ce753ce2d9..78cd56d9031859 100644 --- a/arch/arm/soc/st_stm32/stm32l4/soc.h +++ b/arch/arm/soc/st_stm32/stm32l4/soc.h @@ -40,6 +40,7 @@ #include #include #include +#include #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ #endif /* !_ASMLANGUAGE */ diff --git a/ext/hal/st/stm32cube/Kbuild b/ext/hal/st/stm32cube/Kbuild index a0c8be8f2fd2dc..0d3542b78a7f1e 100644 --- a/ext/hal/st/stm32cube/Kbuild +++ b/ext/hal/st/stm32cube/Kbuild @@ -14,6 +14,7 @@ obj-y += stm32f3xx/drivers/src/stm32f3xx_hal.o obj-y += stm32f3xx/drivers/src/stm32f3xx_hal_rcc.o obj-$(CONFIG_CLOCK_CONTROL_STM32_CUBE) += stm32f3xx/drivers/src/stm32f3xx_ll_utils.o obj-$(CONFIG_SERIAL_HAS_DRIVER) += stm32f3xx/drivers/src/stm32f3xx_hal_uart.o +obj-$(CONFIG_SPI) += stm32f3xx/drivers/src/stm32f3xx_ll_spi.o obj-y += stm32f3xx/soc/system_stm32f3xx.o endif @@ -23,6 +24,7 @@ obj-y += stm32f4xx/drivers/src/stm32f4xx_hal_rcc.o obj-$(CONFIG_CLOCK_CONTROL_STM32_CUBE) += stm32f4xx/drivers/src/stm32f4xx_ll_utils.o obj-$(CONFIG_PWM) += stm32f4xx/drivers/src/stm32f4xx_hal_tim.o obj-$(CONFIG_SERIAL_HAS_DRIVER) += stm32f4xx/drivers/src/stm32f4xx_hal_uart.o +obj-$(CONFIG_SPI) += stm32f4xx/drivers/src/stm32f4xx_ll_spi.o obj-y += stm32f4xx/soc/system_stm32f4xx.o endif @@ -37,6 +39,7 @@ obj-y += stm32l4xx/drivers/src/stm32l4xx_hal_rcc.o obj-$(CONFIG_CLOCK_CONTROL_STM32_CUBE) += stm32l4xx/drivers/src/stm32l4xx_ll_utils.o obj-$(CONFIG_PWM) += stm32l4xx/drivers/src/stm32l4xx_hal_tim.o obj-$(CONFIG_SERIAL_HAS_DRIVER) += stm32l4xx/drivers/src/stm32l4xx_hal_uart.o +obj-$(CONFIG_SPI) += stm32l4xx/drivers/src/stm32l4xx_ll_spi.o obj-y += stm32l4xx/soc/system_stm32l4xx.o endif From ac9ad8fc120fd10c7bc5ab848d524eedb7f9bb2d Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Wed, 24 May 2017 15:10:43 +0200 Subject: [PATCH 22/29] pinmux: stm32f4: Add SPI1 pins on PA4, PA5, PA6 & PA7 Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Neil Armstrong --- arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c | 24 ++++++++++++++++++++++ drivers/pinmux/stm32/pinmux_stm32f4.h | 8 ++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c b/arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c index 5731526eb1d64a..f4df690e53f262 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c +++ b/arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c @@ -112,6 +112,26 @@ static const stm32_pin_func_t pin_pa3_funcs[] = { PINMUX_UART(PA3, UART2, RX) }; +static const stm32_pin_func_t pin_pa4_funcs[] = { + [STM32F4_PINMUX_FUNC_PA4_SPI1_NSS - 1] = + STM32F4X_PIN_CONFIG_AF_PUSH_PULL, +}; + +static const stm32_pin_func_t pin_pa5_funcs[] = { + [STM32F4_PINMUX_FUNC_PA5_SPI1_SCK - 1] = + STM32F4X_PIN_CONFIG_AF_PUSH_PULL, +}; + +static const stm32_pin_func_t pin_pa6_funcs[] = { + [STM32F4_PINMUX_FUNC_PA6_SPI1_MISO - 1] = + STM32F4X_PIN_CONFIG_AF_PUSH_PULL, +}; + +static const stm32_pin_func_t pin_pa7_funcs[] = { + [STM32F4_PINMUX_FUNC_PA7_SPI1_MOSI - 1] = + STM32F4X_PIN_CONFIG_AF_PUSH_PULL, +}; + static const stm32_pin_func_t pin_pa8_funcs[] = { PINMUX_UART(PA8, UART7, RX) }; @@ -325,6 +345,10 @@ static const struct stm32_pinmux_conf pins[] = { STM32_PIN_CONF(STM32_PIN_PA1, pin_pa1_funcs), STM32_PIN_CONF(STM32_PIN_PA2, pin_pa2_funcs), STM32_PIN_CONF(STM32_PIN_PA3, pin_pa3_funcs), + STM32_PIN_CONF(STM32_PIN_PA4, pin_pa4_funcs), + STM32_PIN_CONF(STM32_PIN_PA5, pin_pa5_funcs), + STM32_PIN_CONF(STM32_PIN_PA6, pin_pa6_funcs), + STM32_PIN_CONF(STM32_PIN_PA7, pin_pa7_funcs), STM32_PIN_CONF(STM32_PIN_PA8, pin_pa8_funcs), STM32_PIN_CONF(STM32_PIN_PA9, pin_pa9_funcs), STM32_PIN_CONF(STM32_PIN_PA10, pin_pa10_funcs), diff --git a/drivers/pinmux/stm32/pinmux_stm32f4.h b/drivers/pinmux/stm32/pinmux_stm32f4.h index 818b32aaedce38..2bc1d8fd70a666 100644 --- a/drivers/pinmux/stm32/pinmux_stm32f4.h +++ b/drivers/pinmux/stm32/pinmux_stm32f4.h @@ -21,6 +21,14 @@ #define STM32F4_PINMUX_FUNC_PA3_USART2_RX STM32_PINMUX_FUNC_ALT_7 +#define STM32F4_PINMUX_FUNC_PA4_SPI1_NSS STM32_PINMUX_FUNC_ALT_5 + +#define STM32F4_PINMUX_FUNC_PA5_SPI1_SCK STM32_PINMUX_FUNC_ALT_5 + +#define STM32F4_PINMUX_FUNC_PA6_SPI1_MISO STM32_PINMUX_FUNC_ALT_5 + +#define STM32F4_PINMUX_FUNC_PA7_SPI1_MOSI STM32_PINMUX_FUNC_ALT_5 + #define STM32F4_PINMUX_FUNC_PA8_UART7_RX STM32_PINMUX_FUNC_ALT_8 #define STM32F4_PINMUX_FUNC_PA9_USART1_TX STM32_PINMUX_FUNC_ALT_7 From e8c5f5dc867394312f90ab10dfdacbf0504fbacb Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Wed, 24 May 2017 13:28:24 +0200 Subject: [PATCH 23/29] pinmux: stm32f4: Add SPI2 pins on PB12, PB13, PB14 & PB15 Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Neil Armstrong --- arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c | 17 +++++++++++++++++ drivers/pinmux/stm32/pinmux_stm32f4.h | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c b/arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c index f4df690e53f262..638ed884cb0bf0 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c +++ b/arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c @@ -112,6 +112,7 @@ static const stm32_pin_func_t pin_pa3_funcs[] = { PINMUX_UART(PA3, UART2, RX) }; +/* SPI 1*/ static const stm32_pin_func_t pin_pa4_funcs[] = { [STM32F4_PINMUX_FUNC_PA4_SPI1_NSS - 1] = STM32F4X_PIN_CONFIG_AF_PUSH_PULL, @@ -200,10 +201,24 @@ static const stm32_pin_func_t pin_pb11_funcs[] = { static const stm32_pin_func_t pin_pb12_funcs[] = { PINMUX_UART(PB12, UART5, RX) + [STM32F4_PINMUX_FUNC_PB12_SPI2_NSS - 1] = + STM32F4X_PIN_CONFIG_AF_PUSH_PULL, }; static const stm32_pin_func_t pin_pb13_funcs[] = { PINMUX_UART(PB13, UART5, TX) + [STM32F4_PINMUX_FUNC_PB13_SPI2_SCK - 1] = + STM32F4X_PIN_CONFIG_AF_PUSH_PULL, +}; + +static const stm32_pin_func_t pin_pb14_funcs[] = { + [STM32F4_PINMUX_FUNC_PB14_SPI2_MISO - 1] = + STM32F4X_PIN_CONFIG_AF_PUSH_PULL, +}; + +static const stm32_pin_func_t pin_pb15_funcs[] = { + [STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI - 1] = + STM32F4X_PIN_CONFIG_AF_PUSH_PULL, }; /* Port C */ @@ -368,6 +383,8 @@ static const struct stm32_pinmux_conf pins[] = { STM32_PIN_CONF(STM32_PIN_PB11, pin_pb11_funcs), STM32_PIN_CONF(STM32_PIN_PB12, pin_pb12_funcs), STM32_PIN_CONF(STM32_PIN_PB13, pin_pb13_funcs), + STM32_PIN_CONF(STM32_PIN_PB14, pin_pb14_funcs), + STM32_PIN_CONF(STM32_PIN_PB15, pin_pb15_funcs), /* Port C */ STM32_PIN_CONF(STM32_PIN_PC5, pin_pc5_funcs), diff --git a/drivers/pinmux/stm32/pinmux_stm32f4.h b/drivers/pinmux/stm32/pinmux_stm32f4.h index 2bc1d8fd70a666..d586bd22ec9476 100644 --- a/drivers/pinmux/stm32/pinmux_stm32f4.h +++ b/drivers/pinmux/stm32/pinmux_stm32f4.h @@ -65,10 +65,16 @@ #define STM32F4_PINMUX_FUNC_PB11_USART3_RX STM32_PINMUX_FUNC_ALT_7 +#define STM32F4_PINMUX_FUNC_PB12_SPI2_NSS STM32_PINMUX_FUNC_ALT_5 #define STM32F4_PINMUX_FUNC_PB12_UART5_RX STM32_PINMUX_FUNC_ALT_11 +#define STM32F4_PINMUX_FUNC_PB13_SPI2_SCK STM32_PINMUX_FUNC_ALT_5 #define STM32F4_PINMUX_FUNC_PB13_UART5_TX STM32_PINMUX_FUNC_ALT_11 +#define STM32F4_PINMUX_FUNC_PB14_SPI2_MISO STM32_PINMUX_FUNC_ALT_5 + +#define STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI STM32_PINMUX_FUNC_ALT_5 + /* Port C */ #define STM32F4_PINMUX_FUNC_PC5_USART3_RX STM32_PINMUX_FUNC_ALT_7 From 392e7544ba39c9fe890b35c62da67fef064fdb2a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 16 Sep 2016 15:24:19 +0200 Subject: [PATCH 24/29] spi: add SPI driver for STM32 family Add a SPI master and slave driver for the L4, F4 and F3 STM SoCs families. Change-Id: I1faf5c97f992c91eba852fd126e7d3b83158993d Origin: Original Signed-off-by: Neil Armstrong Tested-by: Lee Jones --- drivers/spi/Kconfig | 54 +++++ drivers/spi/Makefile | 1 + drivers/spi/spi_ll_stm32.c | 359 +++++++++++++++++++++++++++++ drivers/spi/spi_ll_stm32.h | 46 ++++ include/drivers/spi/spi_ll_stm32.h | 24 ++ 5 files changed, 484 insertions(+) create mode 100644 drivers/spi/spi_ll_stm32.c create mode 100644 drivers/spi/spi_ll_stm32.h create mode 100644 include/drivers/spi/spi_ll_stm32.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 68b154f513cfdc..9161943e344675 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -50,6 +50,22 @@ config SPI_INTEL was formerly found on XScale chips. It can be found nowadays on CEXXXX Intel media controller and Quark CPU (2 of them). +config SPI_STM32 + bool + prompt "STM32 MCU SPI controller driver" + depends on SPI && SOC_FAMILY_STM32 + depends on SOC_SERIES_STM32L4X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F3X + default n + help + Enable SPI support on the STM32 family of processors. + +config SPI_STM32_INTERRUPT + bool + prompt "STM32 MCU SPI Interrupt Support" + depends on SPI_STM32 + default n + help + Enable Interrupt support for the SPI Driver of STM32 family. if SPI config SPI_INIT_PRIORITY @@ -195,6 +211,44 @@ config SPI_2_CS_GPIO_PIN depends on SPI_2 && SPI_CS_GPIO default 0 +config SPI_3 + bool + prompt "SPI port 3" + default n + help + Enable SPI controller port 3. + +config SPI_3_NAME + string + prompt "SPI port 3 device name" + depends on SPI_3 + default "SPI_3" + +config SPI_3_IRQ_PRI + int + prompt "Port 3 interrupt priority" + depends on SPI_3 + +config SPI_3_DEFAULT_CFG + hex "Port 3 default configuration" + depends on SPI_3 + default 0x80 + +config SPI_3_DEFAULT_BAUD_RATE + int "Port 3 default baud rate" + depends on SPI_3 + default 500000 + +config SPI_3_CS_GPIO_PORT + string + prompt "The GPIO port which is used to control CS" + depends on SPI_3 && SPI_CS_GPIO + default "GPIO_0" + +config SPI_3_CS_GPIO_PIN + int "The GPIO PIN which is used to act as a CS pin" + depends on SPI_3 && SPI_CS_GPIO + config SPI_SS_INIT_PRIORITY int "Init priority" depends on SPI_QMSI_SS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ff146199d042a1..ea30b82fb2b1e0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_SPIM_NRF52) += spim_nrf52.o obj-$(CONFIG_SPIS_NRF5) += spis_nrf5.o obj-$(CONFIG_SPI_QMSI) += spi_qmsi.o obj-$(CONFIG_SPI_QMSI_SS) += spi_qmsi_ss.o +obj-$(CONFIG_SPI_STM32) += spi_ll_stm32.o diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c new file mode 100644 index 00000000000000..9d975ce5e22ba4 --- /dev/null +++ b/drivers/spi/spi_ll_stm32.c @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2016 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define SYS_LOG_LEVEL CONFIG_SYS_LOG_SPI_LEVEL +#include + +#define DEV_CFG(dev) \ +((const struct spi_stm32_config * const )(dev)->config->config_info) + +#define DEV_DATA(dev) \ +((struct spi_stm32_data * const)(dev)->driver_data) + +#ifdef CONFIG_SPI_STM32_INTERRUPT +static void spi_stm32_isr(void *arg) +{ + struct device * const dev = (struct device *) arg; + const struct spi_stm32_config *cfg = DEV_CFG(dev); + struct spi_stm32_data *data = DEV_DATA(dev); + SPI_TypeDef *spi = cfg->spi; + + if (LL_SPI_IsActiveFlag_TXE(spi)) { + data->tx.process(spi, &data->tx); + } + + if (LL_SPI_IsActiveFlag_RXNE(spi)) { + data->rx.process(spi, &data->rx); + } + + if (!data->rx.len && !data->tx.len) { + LL_SPI_DisableIT_RXNE(spi); + LL_SPI_DisableIT_TXE(spi); + k_sem_give(&data->sync); + } +} +#endif + +static int spi_stm32_configure(struct device *dev, struct spi_config *config) +{ + const struct spi_stm32_config *cfg = DEV_CFG(dev); + struct spi_stm32_data *data = DEV_DATA(dev); + const u32_t scaler[] = { + LL_SPI_BAUDRATEPRESCALER_DIV2, + LL_SPI_BAUDRATEPRESCALER_DIV4, + LL_SPI_BAUDRATEPRESCALER_DIV8, + LL_SPI_BAUDRATEPRESCALER_DIV16, + LL_SPI_BAUDRATEPRESCALER_DIV32, + LL_SPI_BAUDRATEPRESCALER_DIV64, + LL_SPI_BAUDRATEPRESCALER_DIV128, + LL_SPI_BAUDRATEPRESCALER_DIV256 + }; + u32_t flags = config->config; + SPI_TypeDef *spi = cfg->spi; + u32_t clock; + int br; + + if (SPI_WORD_SIZE_GET(flags) != 8) { + return -ENOTSUP; + } + + clock_control_get_rate(device_get_binding(STM32_CLOCK_CONTROL_NAME), + (clock_control_subsys_t) &cfg->pclken, &clock); + + for (br = 1 ; br <= ARRAY_SIZE(scaler) ; ++br) { + u32_t clk = clock >> br; + if (clk < config->max_sys_freq) { + break; + } + } + + if (br > ARRAY_SIZE(scaler)) { + return -ENOTSUP; + } + + LL_SPI_Disable(spi); + + LL_SPI_SetBaudRatePrescaler(spi, scaler[br - 1]); + + if (flags & SPI_MODE_CPOL) { + LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_HIGH); + } else { + LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_LOW); + } + + if (flags & SPI_MODE_CPHA) { + LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_2EDGE); + } else { + LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_1EDGE); + } + + LL_SPI_SetTransferDirection(spi, LL_SPI_FULL_DUPLEX); + + + if (flags & SPI_TRANSFER_MASK) { + LL_SPI_SetTransferBitOrder(spi, LL_SPI_LSB_FIRST); + } else { + LL_SPI_SetTransferBitOrder(spi, LL_SPI_MSB_FIRST); + } + + LL_SPI_DisableCRC(spi); + + if (flags & STM32_SPI_MODE_SLAVE) { + LL_SPI_SetMode(spi, LL_SPI_MODE_SLAVE); + } else { + LL_SPI_SetMode(spi, LL_SPI_MODE_MASTER); + } + + if (flags & STM32_SPI_NSS_IGNORE) { + LL_SPI_SetNSSMode(spi, LL_SPI_NSS_SOFT); + } else if (flags & STM32_SPI_MODE_SLAVE) { + LL_SPI_SetNSSMode(spi, LL_SPI_NSS_HARD_OUTPUT); + } else { + LL_SPI_SetNSSMode(spi, LL_SPI_NSS_HARD_INPUT); + } + + LL_SPI_SetDataWidth(spi, LL_SPI_DATAWIDTH_8BIT); + +#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X) + LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER); +#endif + + LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA); + + data->rx.len = 0; + data->rx.buf = NULL; + data->tx.len = 0; + data->tx.buf = NULL; + + return 0; +} + +static void spi_stm32_transmit(SPI_TypeDef *spi, struct spi_stm32_buffer_tx *p) +{ + if (!p->len) { + return; + } + + LL_SPI_TransmitData8(spi, *p->buf); + + p->buf++; + p->len--; +} + +static void spi_stm32_receive(SPI_TypeDef *spi, struct spi_stm32_buffer_rx *p) +{ + if (!p->len) { + return; + } + + *p->buf = LL_SPI_ReceiveData8(spi); + + p->buf++; + p->len--; +} + +static int spi_stm32_transceive(struct device *dev, const void *tx_buf, + u32_t tx_buf_len,void *rx_buf, u32_t rx_buf_len) +{ + const struct spi_stm32_config *cfg = DEV_CFG(dev); + struct spi_stm32_data *data = DEV_DATA(dev); + SPI_TypeDef *spi = cfg->spi; + + __ASSERT(!(rx.buf_len && (rx.buf == NULL)), + "spi_stm32_transceive: ERROR - rx NULL buffer"); + + __ASSERT(!(tx.buf_len && (tx.buf == NULL)), + "spi_stm32_transceive: ERROR - tx NULL buffer"); + + data->rx.process = spi_stm32_receive; + data->rx.len = rx_buf_len; + data->rx.buf = rx_buf; + + data->tx.process = spi_stm32_transmit; + data->tx.len = tx_buf_len; + data->tx.buf = tx_buf; + + LL_SPI_Enable(spi); + +#ifdef CONFIG_SPI_STM32_INTERRUPT + if (rx_buf_len) { + LL_SPI_EnableIT_RXNE(spi); + } + + if (tx_buf_len) { + LL_SPI_EnableIT_TXE(spi); + } + + k_sem_take(&data->sync, K_FOREVER); +#else + do { + if (LL_SPI_IsActiveFlag_TXE(spi)) { + data->tx.process(spi, &data->tx); + } + + if (LL_SPI_IsActiveFlag_RXNE(spi) && data->rx.len) { + data->rx.process(spi, &data->rx); + } + } while (data->tx.len || data->rx.len); +#endif + +#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X) + while (LL_SPI_GetTxFIFOLevel(spi) != LL_SPI_TX_FIFO_EMPTY) { + (void) LL_SPI_ReceiveData8(spi); + } +#endif + if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) { + while (LL_SPI_IsActiveFlag_BSY(spi)) { + /* NOP */ + } + LL_SPI_Disable(spi); + } + + return 0; +} + +static const struct spi_driver_api api_funcs = { + .transceive = spi_stm32_transceive, + .configure = spi_stm32_configure, +}; + +static int spi_stm32_init(struct device *dev) +{ + struct spi_stm32_data *data __attribute__((unused)) = DEV_DATA(dev); + const struct spi_stm32_config *cfg = DEV_CFG(dev); + + __ASSERT_NO_MSG(device_get_binding(STM32_CLOCK_CONTROL_NAME)); + + + clock_control_on(device_get_binding(STM32_CLOCK_CONTROL_NAME), + (clock_control_subsys_t) &cfg->pclken); + + +#ifdef CONFIG_SPI_STM32_INTERRUPT + k_sem_init(&data->sync, 0, UINT_MAX); + + cfg->irq_config(dev); +#endif + + return 0; +} + +#ifdef CONFIG_SPI_1 + +#ifdef CONFIG_SPI_STM32_INTERRUPT +static void spi_stm32_irq_config_func_1(struct device *port); +#endif + +static const struct spi_stm32_config spi_stm32_cfg_1 = { + .spi = (SPI_TypeDef *) SPI1_BASE, + .pclken = { + .enr = LL_APB2_GRP1_PERIPH_SPI1, + .bus = STM32_CLOCK_BUS_APB2 + }, +#ifdef CONFIG_SPI_STM32_INTERRUPT + .irq_config = spi_stm32_irq_config_func_1, +#endif +}; + +static struct spi_stm32_data spi_stm32_dev_data_1; + +DEVICE_AND_API_INIT(spi_stm32_1, CONFIG_SPI_1_NAME, &spi_stm32_init, + &spi_stm32_dev_data_1, &spi_stm32_cfg_1, + POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, + &api_funcs); + +#ifdef CONFIG_SPI_STM32_INTERRUPT +static void spi_stm32_irq_config_func_1(struct device *dev) +{ + IRQ_CONNECT(SPI1_IRQn, CONFIG_SPI_1_IRQ_PRI, + spi_stm32_isr, DEVICE_GET(spi_stm32_1), 0); + irq_enable(SPI1_IRQn); +} +#endif + +#endif /* CONFIG_SPI_1 */ + +#ifdef CONFIG_SPI_2 + +#ifdef CONFIG_SPI_STM32_INTERRUPT +static void spi_stm32_irq_config_func_2(struct device *port); +#endif + +static const struct spi_stm32_config spi_stm32_cfg_2 = { + .spi = (SPI_TypeDef *) SPI2_BASE, + .pclken = { + .enr = LL_APB1_GRP1_PERIPH_SPI2, + .bus = STM32_CLOCK_BUS_APB1 + }, +#ifdef CONFIG_SPI_STM32_INTERRUPT + .irq_config = spi_stm32_irq_config_func_2, +#endif +}; + +static struct spi_stm32_data spi_stm32_dev_data_2; + +DEVICE_AND_API_INIT(spi_stm32_2, CONFIG_SPI_2_NAME, &spi_stm32_init, + &spi_stm32_dev_data_2, &spi_stm32_cfg_2, + POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, + &api_funcs); + +#ifdef CONFIG_SPI_STM32_INTERRUPT +static void spi_stm32_irq_config_func_2(struct device *dev) +{ + IRQ_CONNECT(SPI2_IRQn, CONFIG_SPI_2_IRQ_PRI, + spi_stm32_isr, DEVICE_GET(spi_stm32_2), 0); + irq_enable(SPI2_IRQn); +} +#endif + +#endif /* CONFIG_SPI_2 */ + +#ifdef CONFIG_SPI_3 + +#ifdef CONFIG_SPI_STM32_INTERRUPT +static void spi_stm32_irq_config_func_3(struct device *port); +#endif + +static const struct spi_stm32_config spi_stm32_cfg_3 = { + .spi = (SPI_TypeDef *) SPI3_BASE, + .pclken = { + .enr = LL_APB1_GRP1_PERIPH_SPI3, + .bus = STM32_CLOCK_BUS_APB1 + }, +#ifdef CONFIG_SPI_STM32_INTERRUPT + .irq_config = spi_stm32_irq_config_func_3, +#endif +}; + +static struct spi_stm32_data spi_stm32_dev_data_3; + +DEVICE_AND_API_INIT(spi_stm32_3, CONFIG_SPI_3_NAME, &spi_stm32_init, + &spi_stm32_dev_data_3, &spi_stm32_cfg_3, + POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, + &api_funcs); + +#ifdef CONFIG_SPI_STM32_INTERRUPT +static void spi_stm32_irq_config_func_3(struct device *dev) +{ + IRQ_CONNECT(SPI3_IRQn, CONFIG_SPI_3_IRQ_PRI, + spi_stm32_isr, DEVICE_GET(spi_stm32_3), 0); + irq_enable(SPI3_IRQn); +} +#endif + +#endif /* CONFIG_SPI_3 */ diff --git a/drivers/spi/spi_ll_stm32.h b/drivers/spi/spi_ll_stm32.h new file mode 100644 index 00000000000000..36009f28744c22 --- /dev/null +++ b/drivers/spi/spi_ll_stm32.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2016 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _STM32_SPI_H_ +#define _STM32_SPI_H_ + +typedef void (*irq_config_func_t)(struct device *port); + +struct spi_stm32_config { + struct stm32_pclken pclken; + SPI_TypeDef *spi; +#ifdef CONFIG_SPI_STM32_INTERRUPT + irq_config_func_t irq_config; +#endif +}; + +struct spi_stm32_buffer_rx; +struct spi_stm32_buffer_tx; + +typedef void (*rx_func_t)(SPI_TypeDef *spi, struct spi_stm32_buffer_rx *p); +typedef void (*tx_func_t)(SPI_TypeDef *spi, struct spi_stm32_buffer_tx *p); + +struct spi_stm32_buffer_rx { + rx_func_t process; + unsigned int len; + u8_t *buf; +}; + +struct spi_stm32_buffer_tx { + tx_func_t process; + unsigned int len; + const u8_t *buf; +}; + +struct spi_stm32_data { + struct spi_stm32_buffer_tx tx; + struct spi_stm32_buffer_rx rx; +#ifdef CONFIG_SPI_STM32_INTERRUPT + struct k_sem sync; +#endif +}; + +#endif /* _STM32_SPI_H_ */ diff --git a/include/drivers/spi/spi_ll_stm32.h b/include/drivers/spi/spi_ll_stm32.h new file mode 100644 index 00000000000000..e296477746678e --- /dev/null +++ b/include/drivers/spi/spi_ll_stm32.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2016 BayLibre, SAS + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _DRIVERS_STM32_SPI_H_ +#define _DRIVERS_STM32_SPI_H_ + +#define STM32_SPI_MODE_MASTER (1 << 24) +#define STM32_SPI_MODE_SLAVE (1 << 25) +#define STM32_SPI_NSS_IGNORE (1 << 26) + +#endif /* _DRIVERS_STM32_SPI_H_ */ From 580313cd7bc84eeec5686b8c53be77f7fdbbeab0 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Wed, 24 May 2017 14:56:04 +0200 Subject: [PATCH 25/29] pinmux: stm32: nucleo_f401re: Add support for SPI Add SPI pin for the nucleo_f401re pinmux. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Neil Armstrong --- drivers/pinmux/stm32/pinmux_board_nucleo_f401re.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pinmux/stm32/pinmux_board_nucleo_f401re.c b/drivers/pinmux/stm32/pinmux_board_nucleo_f401re.c index 9314bf7b78f07e..622578e705b088 100644 --- a/drivers/pinmux/stm32/pinmux_board_nucleo_f401re.c +++ b/drivers/pinmux/stm32/pinmux_board_nucleo_f401re.c @@ -26,6 +26,18 @@ static const struct pin_config pinconf[] = { #ifdef CONFIG_PWM_STM32_2 {STM32_PIN_PA0, STM32F4_PINMUX_FUNC_PA0_PWM2_CH1}, #endif /* CONFIG_PWM_STM32_2 */ +#ifdef CONFIG_SPI_1 + {STM32_PIN_PA4, STM32F4_PINMUX_FUNC_PA4_SPI1_NSS}, + {STM32_PIN_PA5, STM32F4_PINMUX_FUNC_PA5_SPI1_SCK}, + {STM32_PIN_PA6, STM32F4_PINMUX_FUNC_PA6_SPI1_MISO}, + {STM32_PIN_PA7, STM32F4_PINMUX_FUNC_PA7_SPI1_MOSI}, +#endif /* CONFIG_SPI_1 */ +#ifdef CONFIG_SPI_2 + {STM32_PIN_PB12, STM32F4_PINMUX_FUNC_PB12_SPI2_NSS}, + {STM32_PIN_PB13, STM32F4_PINMUX_FUNC_PB13_SPI2_SCK}, + {STM32_PIN_PB14, STM32F4_PINMUX_FUNC_PB14_SPI2_MISO}, + {STM32_PIN_PB15, STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI}, +#endif /* CONFIG_SPI_1 */ }; static int pinmux_stm32_init(struct device *port) From cf2ba9f65f712d5e1c5b8b81fb6d38c5b5adac0e Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Tue, 23 May 2017 14:58:19 +0200 Subject: [PATCH 26/29] pinmux: stm32: nucleo_f334r8: add support for SPI Following implementation of LL based SPI driver, add SPI support on nucleo_f334r8 board of STM32F3 series. Change-Id: Ifbe39b1f2cecdd7db23be9c6943a914a155ebd77 Signed-off-by: Erwan Gouriou Signed-off-by: Neil Armstrong --- drivers/pinmux/stm32/pinmux_board_nucleo_f334r8.c | 6 ++++++ drivers/pinmux/stm32/pinmux_stm32f3.h | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/drivers/pinmux/stm32/pinmux_board_nucleo_f334r8.c b/drivers/pinmux/stm32/pinmux_board_nucleo_f334r8.c index 59feda59dcf9e8..12e36f938afec1 100644 --- a/drivers/pinmux/stm32/pinmux_board_nucleo_f334r8.c +++ b/drivers/pinmux/stm32/pinmux_board_nucleo_f334r8.c @@ -23,6 +23,12 @@ static const struct pin_config pinconf[] = { {STM32_PIN_PA2, STM32F3_PINMUX_FUNC_PA2_USART2_TX}, {STM32_PIN_PA3, STM32F3_PINMUX_FUNC_PA3_USART2_RX}, #endif /* CONFIG_UART_STM32_PORT_2 */ +#ifdef CONFIG_SPI_1 + {STM32_PIN_PA4, STM32F3_PINMUX_FUNC_PA4_SPI1_NSS}, + {STM32_PIN_PA5, STM32F3_PINMUX_FUNC_PA5_SPI1_SCK}, + {STM32_PIN_PA6, STM32F3_PINMUX_FUNC_PA6_SPI1_MISO}, + {STM32_PIN_PA7, STM32F3_PINMUX_FUNC_PA7_SPI1_MOSI}, +#endif /* CONFIG_SPI_1 */ #ifdef CONFIG_UART_STM32_PORT_3 {STM32_PIN_PB10, STM32F3_PINMUX_FUNC_PB10_USART3_TX}, {STM32_PIN_PB11, STM32F3_PINMUX_FUNC_PB11_USART3_RX}, diff --git a/drivers/pinmux/stm32/pinmux_stm32f3.h b/drivers/pinmux/stm32/pinmux_stm32f3.h index b80d3b1a042c34..d5b100780c5190 100644 --- a/drivers/pinmux/stm32/pinmux_stm32f3.h +++ b/drivers/pinmux/stm32/pinmux_stm32f3.h @@ -36,4 +36,9 @@ #define STM32F3_PINMUX_FUNC_PB10_USART3_TX STM32_PINMUX_FUNC_ALT_7 #endif +#define STM32F3_PINMUX_FUNC_PA4_SPI1_NSS STM32_PINMUX_FUNC_ALT_5 +#define STM32F3_PINMUX_FUNC_PA5_SPI1_SCK STM32_PINMUX_FUNC_ALT_5 +#define STM32F3_PINMUX_FUNC_PA6_SPI1_MISO STM32_PINMUX_FUNC_ALT_5 +#define STM32F3_PINMUX_FUNC_PA7_SPI1_MOSI STM32_PINMUX_FUNC_ALT_5 + #endif /* _STM32F3_PINMUX_H_ */ From e243b1f71f9ebbd25350f27dd3f4d6e60694e121 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 28 Apr 2017 11:55:46 +0200 Subject: [PATCH 27/29] boards: nucleo_l476rg: Document default SPI pinmux Signed-off-by: Neil Armstrong --- boards/arm/nucleo_l476rg/doc/nucleol476rg.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/boards/arm/nucleo_l476rg/doc/nucleol476rg.rst b/boards/arm/nucleo_l476rg/doc/nucleol476rg.rst index 3c109d52da2b3e..9b22d0e9ed0c6a 100644 --- a/boards/arm/nucleo_l476rg/doc/nucleol476rg.rst +++ b/boards/arm/nucleo_l476rg/doc/nucleol476rg.rst @@ -106,6 +106,8 @@ The Zephyr nucleo_l476rg board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | PWM | on-chip | pwm | +-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -146,6 +148,18 @@ Default Zephyr Peripheral Mapping: - UART_3_RX : PB11 - I2C_1_SCL : PB6 - I2C_1_SDA : PB7 +- SPI_1_NSS : PA4 +- SPI_1_SCK : PB3 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PB12 +- SPI_2_SCK : PB13 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PB12 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 - PWM_2_CH1 : PA0 - USER_PB : PC13 - LD2 : PA5 From 5881297abdf48da923abb50416805024be78640e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 28 Apr 2017 11:55:20 +0200 Subject: [PATCH 28/29] pinmux: stm32: nucleo_l476rg: Fix SPI Pinmux Signed-off-by: Neil Armstrong --- .../pinmux/stm32/pinmux_board_nucleo_l476rg.c | 18 ++++++++++++++---- drivers/pinmux/stm32/pinmux_stm32l4x.h | 8 ++++++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/pinmux/stm32/pinmux_board_nucleo_l476rg.c b/drivers/pinmux/stm32/pinmux_board_nucleo_l476rg.c index f30ecb7100c8d8..219017c747c2d8 100644 --- a/drivers/pinmux/stm32/pinmux_board_nucleo_l476rg.c +++ b/drivers/pinmux/stm32/pinmux_board_nucleo_l476rg.c @@ -36,16 +36,26 @@ static const struct pin_config pinconf[] = { {STM32_PIN_PA0, STM32L4X_PINMUX_FUNC_PA0_PWM2_CH1}, #endif /* CONFIG_PWM_STM32_2 */ #ifdef CONFIG_SPI_1 + /* SPI1 on the Arduino connectors pins A2, D3, D12, D11 */ {STM32_PIN_PA4, STM32L4X_PINMUX_FUNC_PA4_SPI1_NSS}, + /* SPI1_SCK should output on PA5, but is used for LD2 */ {STM32_PIN_PB3, STM32L4X_PINMUX_FUNC_PB3_SPI1_SCK}, - {STM32_PIN_PA5, STM32L4X_PINMUX_FUNC_PA5_SPI1_SCK}, {STM32_PIN_PA6, STM32L4X_PINMUX_FUNC_PA6_SPI1_MISO}, {STM32_PIN_PA7, STM32L4X_PINMUX_FUNC_PA7_SPI1_MOSI}, #endif /* CONFIG_SPI_1 */ +#ifdef CONFIG_SPI_2 + /* SPI2 on the ST Morpho Connector CN10 pins 16, 30, 28, 26*/ + {STM32_PIN_PB12, STM32L4X_PINMUX_FUNC_PB12_SPI2_NSS}, + {STM32_PIN_PB13, STM32L4X_PINMUX_FUNC_PB13_SPI2_SCK}, + {STM32_PIN_PB14, STM32L4X_PINMUX_FUNC_PB14_SPI2_MISO}, + {STM32_PIN_PB15, STM32L4X_PINMUX_FUNC_PB15_SPI2_MOSI}, +#endif /* CONFIG_SPI_1 */ #ifdef CONFIG_SPI_3 - {STM32_PIN_PB3, STM32L4X_PINMUX_FUNC_PB3_SPI3_SCK}, - {STM32_PIN_PB4, STM32L4X_PINMUX_FUNC_PB4_SPI3_MISO}, - {STM32_PIN_PB5, STM32L4X_PINMUX_FUNC_PB5_SPI3_MOSI}, + /* SPI3 on the ST Morpho Connector CN7 pins 17, 1, 2, 3*/ + {STM32_PIN_PA15, STM32L4X_PINMUX_FUNC_PA15_SPI3_NSS}, + {STM32_PIN_PC10, STM32L4X_PINMUX_FUNC_PC10_SPI3_SCK}, + {STM32_PIN_PC11, STM32L4X_PINMUX_FUNC_PC11_SPI3_MISO}, + {STM32_PIN_PC12, STM32L4X_PINMUX_FUNC_PC12_SPI3_MOSI}, #endif /* CONFIG_SPI_3 */ }; diff --git a/drivers/pinmux/stm32/pinmux_stm32l4x.h b/drivers/pinmux/stm32/pinmux_stm32l4x.h index 29e8d9c09c30c8..312948788e80e8 100644 --- a/drivers/pinmux/stm32/pinmux_stm32l4x.h +++ b/drivers/pinmux/stm32/pinmux_stm32l4x.h @@ -24,6 +24,7 @@ #define STM32L4X_PINMUX_FUNC_PA10_USART1_RX STM32_PINMUX_FUNC_ALT_7 #define STM32L4X_PINMUX_FUNC_PA15_PWM2_CH1 STM32_PINMUX_FUNC_ALT_1 #define STM32L4X_PINMUX_FUNC_PA15_USART2_RX STM32_PINMUX_FUNC_ALT_3 +#define STM32L4X_PINMUX_FUNC_PA15_SPI3_NSS STM32_PINMUX_FUNC_ALT_6 /* Port B */ #define STM32L4X_PINMUX_FUNC_PB3_SPI1_SCK STM32_PINMUX_FUNC_ALT_5 @@ -40,16 +41,23 @@ #define STM32L4X_PINMUX_FUNC_PB10_USART3_TX STM32_PINMUX_FUNC_ALT_7 #define STM32L4X_PINMUX_FUNC_PB11_I2C2_SDA STM32_PINMUX_FUNC_ALT_4 #define STM32L4X_PINMUX_FUNC_PB11_USART3_RX STM32_PINMUX_FUNC_ALT_7 +#define STM32L4X_PINMUX_FUNC_PB12_SPI2_NSS STM32_PINMUX_FUNC_ALT_5 #define STM32L4X_PINMUX_FUNC_PB13_I2C2_SCL STM32_PINMUX_FUNC_ALT_4 +#define STM32L4X_PINMUX_FUNC_PB13_SPI2_SCK STM32_PINMUX_FUNC_ALT_5 #define STM32L4X_PINMUX_FUNC_PB14_I2C2_SDA STM32_PINMUX_FUNC_ALT_4 +#define STM32L4X_PINMUX_FUNC_PB14_SPI2_MISO STM32_PINMUX_FUNC_ALT_5 +#define STM32L4X_PINMUX_FUNC_PB15_SPI2_MOSI STM32_PINMUX_FUNC_ALT_5 /* Port C */ #define STM32L4X_PINMUX_FUNC_PC0_I2C3_SCL STM32_PINMUX_FUNC_ALT_4 #define STM32L4X_PINMUX_FUNC_PC1_I2C3_SDA STM32_PINMUX_FUNC_ALT_4 #define STM32L4X_PINMUX_FUNC_PC4_USART3_TX STM32_PINMUX_FUNC_ALT_7 #define STM32L4X_PINMUX_FUNC_PC5_USART3_RX STM32_PINMUX_FUNC_ALT_7 +#define STM32L4X_PINMUX_FUNC_PC10_SPI3_SCK STM32_PINMUX_FUNC_ALT_6 #define STM32L4X_PINMUX_FUNC_PC10_USART3_TX STM32_PINMUX_FUNC_ALT_7 +#define STM32L4X_PINMUX_FUNC_PC11_SPI3_MISO STM32_PINMUX_FUNC_ALT_6 #define STM32L4X_PINMUX_FUNC_PC11_USART3_RX STM32_PINMUX_FUNC_ALT_7 +#define STM32L4X_PINMUX_FUNC_PC12_SPI3_MOSI STM32_PINMUX_FUNC_ALT_6 /* Port D */ #define STM32L4X_PINMUX_FUNC_PD5_USART2_TX STM32_PINMUX_FUNC_ALT_7 From 6b90818ed40a7666f729cf81e1d26d6f3050a4c5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 24 May 2017 15:31:33 +0200 Subject: [PATCH 29/29] pinmux: stm32: nucleo_l432kc: Add SPI pins Signed-off-by: Neil Armstrong --- drivers/pinmux/stm32/pinmux_board_nucleo_l432kc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pinmux/stm32/pinmux_board_nucleo_l432kc.c b/drivers/pinmux/stm32/pinmux_board_nucleo_l432kc.c index 95254a6b9f9773..5fff8c837c5a21 100644 --- a/drivers/pinmux/stm32/pinmux_board_nucleo_l432kc.c +++ b/drivers/pinmux/stm32/pinmux_board_nucleo_l432kc.c @@ -31,6 +31,12 @@ static const struct pin_config pinconf[] = { #ifdef CONFIG_PWM_STM32_2 {STM32_PIN_PA0, STM32L4X_PINMUX_FUNC_PA0_PWM2_CH1}, #endif /* CONFIG_PWM_STM32_2 */ +#ifdef CONFIG_SPI_1 + {STM32_PIN_PA4, STM32L4X_PINMUX_FUNC_PA4_SPI1_NSS}, + {STM32_PIN_PA5, STM32L4X_PINMUX_FUNC_PA5_SPI1_SCK}, + {STM32_PIN_PA6, STM32L4X_PINMUX_FUNC_PA6_SPI1_MISO}, + {STM32_PIN_PA7, STM32L4X_PINMUX_FUNC_PA7_SPI1_MOSI}, +#endif /* CONFIG_SPI_1 */ }; static int pinmux_stm32_init(struct device *port)