From 98aff27c8ada08722b7631f5811097231143cbf4 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Mon, 13 Mar 2023 17:02:31 +0200 Subject: [PATCH] intel_adsp: cavs25: configure access to ALH For Intel cavs2.5, access from LPGPDMAC to Audio Link Hub RX/TX registers needs to be explicitly enabled before use. The logic follow hardware initialization done in SOF project sof/src/platform/intel/cavs/platform.c Signed-off-by: Kai Vehmanen --- drivers/dai/intel/alh/alh.c | 11 +++++++++++ .../cavs/include/intel_tgl_adsp/adsp_shim.h | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/drivers/dai/intel/alh/alh.c b/drivers/dai/intel/alh/alh.c index 646e09f3122ac3..63299bf6f2fc29 100644 --- a/drivers/dai/intel/alh/alh.c +++ b/drivers/dai/intel/alh/alh.c @@ -11,6 +11,10 @@ #include #include +#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 +#include +#endif + #define DT_DRV_COMPAT intel_alh_dai #define LOG_DOMAIN dai_intel_alh @@ -75,6 +79,10 @@ static void alh_claim_ownership(void) sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0x3), ALHASCTL); sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0x3), ALHCSCTL); #endif +#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 + /* Allow LPGPDMA connection to Audio Link Hub */ + sys_set_bits(ADSP_DSPALHO_ADDRESS, DSPALHO_ASO_FLAG | DSPALHO_CSO_FLAG); +#endif } static void alh_release_ownership(void) @@ -86,6 +94,9 @@ static void alh_release_ownership(void) sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0), ALHASCTL); sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0), ALHCSCTL); #endif +#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 + sys_clear_bits(ADSP_DSPALHO_ADDRESS, DSPALHO_ASO_FLAG | DSPALHO_CSO_FLAG); +#endif } diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h b/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h index e01527c91418c8..8ea0b4340f61ec 100644 --- a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h +++ b/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h @@ -145,4 +145,8 @@ struct cavs_win { #define GENO_MDIVOSEL BIT(1) #define GENO_DIOPTOSEL BIT(2) +#define DSPALHO_ASO_FLAG BIT(0) +#define DSPALHO_CSO_FLAG BIT(1) +#define DSPALHO_CFO_FLAG BIT(2) + #endif /* ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ */