Skip to content
View 0xArt's full-sized avatar

Block or report 0xArt

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Tiny_But_Mighty_I2C_Master_Verilog Tiny_But_Mighty_I2C_Master_Verilog Public

    I2C Master Verilog module

    SystemVerilog 27 10

  2. RGMII_Ethernet_Transceiver_Verilog RGMII_Ethernet_Transceiver_Verilog Public

    Verilog module to transmit/receive to/from RGMII compatible ethernet PHY

    Verilog 20 5

  3. Super_SPI_Master_Verilog Super_SPI_Master_Verilog Public

    SPI Master Verilog module

    SystemVerilog 7 4

  4. Passe_Passe_Network_Switch Passe_Passe_Network_Switch Public

    A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.

    SystemVerilog 4 1

  5. SuperHashProcessor SuperHashProcessor Public

    Quartus Prime project directory of a SHA1, SHA256, and MD5 hash processor written in System Verilog.

    SystemVerilog 3 2

  6. RaspberryPi_Servo_Control RaspberryPi_Servo_Control Public

    C 1