feat: Add `INCR` privileged instructions #734

Nashtare · 2024-10-18T16:16:11Z

Add a series of 4 INCR privileged instructions (INCR1, INCR2, INCR3 and INCR4) to increment by 1 the Nth element of the stack in place (i.e. no PUSH / POP).
Particularly helpful for accumulators increment previously requiring SWAPN PUSH 1 ADD SWAPN now only requiring INCRN.

Though having an overall lesser impact, we could see how interesting a DECR variant would be (we could add it at no cost by combining it with the INCR CPU column).

Removes 4% to 5% of CPU cycles on mainnet blocks.

Total CPU columns for vanilla type1: 86

MemBefore new initial size:

vanilla type1: 63199
type2: 62691

Nashtare · 2024-10-18T17:48:20Z

scripts/prove_stdio.sh

+        cat $TEST_OUT_PATH
+        echo "Failed to create proof witnesses. See $TEST_OUT_PATH for more details."


unrelated, but mentioned on slack

Nashtare · 2024-10-18T17:48:32Z

scripts/prove_rpc.sh

-# Circuit sizes only matter in non test_only mode.
-if ! [[ $8 == "test_only" ]]; then
-    export ARITHMETIC_CIRCUIT_SIZE="16..21"
-    export BYTE_PACKING_CIRCUIT_SIZE="8..21"
-    export CPU_CIRCUIT_SIZE="8..21"
-    export KECCAK_CIRCUIT_SIZE="4..20"
-    export KECCAK_SPONGE_CIRCUIT_SIZE="8..17"
-    export LOGIC_CIRCUIT_SIZE="4..21"
-    export MEMORY_CIRCUIT_SIZE="17..24"
-    export MEMORY_BEFORE_CIRCUIT_SIZE="16..23"
-    export MEMORY_AFTER_CIRCUIT_SIZE="7..23"
-fi


these match the default ones in .env

muursh

Very nice

hratoanina

Looks good, but there are some issues with the constraints. We should also be able to get rid of the memory operations for INCR1.

hratoanina · 2024-10-21T11:06:50Z

evm_arithmetization/src/cpu/incr.rs

+use super::dup_swap::{constrain_channel_ext_circuit, constrain_channel_packed};
+use crate::cpu::columns::CpuColumnsView;
+
+/// Evaluates the constraints for the DUP and SWAP opcodes.


Update comment.

hratoanina · 2024-10-21T11:07:46Z

evm_arithmetization/src/cpu/incr.rs

+
+    let n = lv.opcode_bits[0]
+        + lv.opcode_bits[1] * P::Scalar::from_canonical_u64(2)
+        + lv.opcode_bits[2] * P::Scalar::from_canonical_u64(4);


I thought n was only two bits?

hratoanina · 2024-10-21T11:18:19Z

evm_arithmetization/src/cpu/kernel/asm/bignum/modmul.asm

@@ -156,13 +156,12 @@ modmul_check_loop:
    SWAP1
    %decrement
    // stack: n-1, base_addr, i, j, retdest


Probably faster to do:

INCR3 INCR4 // stack: n-1, base_addr, i+1, j+1, retdest %stack (n, addr) -> (n, addr, n)

hratoanina · 2024-10-21T11:20:30Z

evm_arithmetization/src/cpu/kernel/asm/core/exception.asm

+    BYTES 3  // 0xe2, INCR3
+    BYTES 4  // 0xe3, INCR4
+
+    %rep 12 // 0xe5-0xef, invalid


Suggested change

%rep 12 // 0xe5-0xef, invalid

%rep 12 // 0xe4-0xef, invalid

hratoanina · 2024-10-21T11:30:20Z

evm_arithmetization/src/cpu/kernel/asm/hash/ripemd/update.asm

@@ -119,9 +119,9 @@ buffer_update:
    // stack: get, set, get  , set  , times  , retdest
    %mupdate_current_general
    // stack:           get  , set  , times  , retdest
-    %increment
+    INCR1
+    INCR2
    SWAP1 


Remove the two extra SWAP1.

hratoanina · 2024-10-21T12:14:56Z

evm_arithmetization/src/witness/operation.rs

@@ -597,6 +599,39 @@ pub(crate) fn generate_swap<F: RichField, T: Transition<F>>(
    Ok(())
 }

+pub(crate) fn generate_incr<F: RichField, T: Transition<F>>(


I'm actually not sure why it's working. For INCR2-4, there's no problem, but for INCR1 we are reading the stack (and writing) at address stack_len - 1. There is no guarantee that the current top of the stack has been written in memory, so I'm surprised the reads don't return a wrong value sometimes.

hratoanina · 2024-10-21T12:23:21Z

evm_arithmetization/src/cpu/incr.rs

Some constraints seem to be missing, and some seem to be unneeded.

The current set of constraints work as intended for INCR2-4, but for INCR1 we are not checking that the output channel is equal to the next top of the stack.
Moreover, the value read in the input channel is not constrained to match the current top of the stack (tests pass so it seems to be the case, but it sounds like coincidence to me).

I think the clean way to do it is to filter all of the current constraints with lv.opcode_bits[0] (with a new one making sure that the top of the stack doesn't change), and handle INCR1 separately with filter 1 - lv.opcode_bits[0] (you can even disable the memory channels to save some memory rows).

LindaGuiga

I have the same concerns as Hamy regarding generate_incr and constraints for INCR1. For INCR2-4, it looks good to me besides some nits.

LindaGuiga · 2024-10-21T12:10:25Z

evm_arithmetization/src/cpu/incr.rs

+use super::dup_swap::{constrain_channel_ext_circuit, constrain_channel_packed};
+use crate::cpu::columns::CpuColumnsView;
+
+/// Evaluates the constraints for the DUP and SWAP opcodes.


Suggested change

/// Evaluates the constraints for the DUP and SWAP opcodes.

/// Evaluates the constraints for the INCR opcode.

LindaGuiga · 2024-10-21T12:13:06Z

evm_arithmetization/src/cpu/incr.rs

+
+    let n = lv.opcode_bits[0]
+        + lv.opcode_bits[1] * P::Scalar::from_canonical_u64(2)
+        + lv.opcode_bits[2] * P::Scalar::from_canonical_u64(4);


The opcodes go from e0 to e3, so I don't think you need + lv.opcode_bits[2] * P::Scalar::from_canonical_u64(4);

Nashtare added 9 commits October 17, 2024 15:14

Add increment WIP

82c5982

Bring back arith op

cca978f

Tweak

1270181

Add CTLs

c69d9e9

Reduce memory

b99ed9c

Remove profile

89caabf

Add CPU constraints

a848075

Update doc

b45751c

Remove macro

f444249

Nashtare added the performance Performance improvement related changes label Oct 18, 2024

Nashtare added this to the Performance Tuning milestone Oct 18, 2024

Nashtare requested a review from hratoanina October 18, 2024 16:16

Nashtare self-assigned this Oct 18, 2024

Nashtare requested review from wborgeaud, muursh and LindaGuiga as code owners October 18, 2024 16:16

github-actions bot added crate: evm_arithmetization Anything related to the evm_arithmetization crate. specs labels Oct 18, 2024

Nashtare added 2 commits October 18, 2024 12:35

Ranges

58cf528

Fix

7c765fd

Nashtare commented Oct 18, 2024

View reviewed changes

Merge remote-tracking branch 'origin/develop' into feat/incr_opcode

b786905

muursh approved these changes Oct 21, 2024

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hratoanina requested changes Oct 21, 2024

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LindaGuiga reviewed Oct 21, 2024

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feat: Add `INCR` privileged instructions #734

feat: Add `INCR` privileged instructions #734

Nashtare commented Oct 18, 2024 •

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		cat $TEST_OUT_PATH
		echo "Failed to create proof witnesses. See $TEST_OUT_PATH for more details."

	/// Evaluates the constraints for the DUP and SWAP opcodes.
	/// Evaluates the constraints for the INCR opcode.

feat: Add INCR privileged instructions #734

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feat: Add `INCR` privileged instructions #734

feat: Add `INCR` privileged instructions #734

Nashtare commented Oct 18, 2024 •

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