Update riscvsingle.vhdl

AlexFW16 · Jun 2, 2023 · 381dbcf · 381dbcf
1 parent 0e77605
commit 381dbcf
Showing 1 changed file with 15 additions and 3 deletions.
diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
@@ -363,8 +363,7 @@ architecture struct of datapath is
   signal SrcA, SrcB:                STD_ULOGIC_VECTOR(31 downto 0); --new
   signal ShiftA, ShiftB, ShiftOut:            STD_ULOGIC_VECTOR(31 downto 0); --new
   signal Result:                    STD_ULOGIC_VECTOR(31 downto 0);
-  signal Zero_s:                    STD_ULOGIC_VECTOR(0 downto 0);
-  signal ZeroMuxOut:                STD_ULOGIC;
+  signal Zero_s, ZeroMuxOut:                STD_ULOGIC;
   signal PC_s, WriteData_s, ALUResult_s : STD_ULOGIC_VECTOR(31 downto 0);
 begin
   -- next PC logic
@@ -393,7 +392,7 @@ begin
   mainalu: alu port map(SrcA, SrcB,ALUControl, ALUResult_s, Zero_s);
   resultmux: mux4 generic map(32) port map(ALUResult_s, ReadData, PCPlus4, ShiftOut, ResultSrc,
                                            Result);
-  zeromux: mux2 generic map(1) port map(Zero_s, ALUResult_s(0), BLT, Zero);
+  zeromux: mux2_single generic map(1) port map(Zero_s, ALUResult_s(31), BLT, Zero);
 
   ALUResult <= ALUResult_s;
   WriteData <= WriteData_s;
@@ -550,6 +549,19 @@ begin
   y <= d1 when s='1' else d0;
 end;
 
+entity mux2_single is -- two-input multiplexer
+  generic(width: integer :=8);
+  port(d0: in STD_ULOGIC;
+       d1: in  STD_ULOGIC_VECTOR(width-1 downto 0);
+       s:      in  STD_ULOGIC;
+       y:      out STD_ULOGIC_VECTOR(width-1 downto 0));
+end;
+
+architecture behave of mux2_single is
+begin
+  y <= d1 when s='1' else d0;
+end;
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;