Update riscvsingle.vhdl

AlexFW16 · Jun 2, 2023 · 58b83c5 · 58b83c5
1 parent cd9a201
commit 58b83c5
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
@@ -615,7 +615,8 @@ end;
 architecture behave of shifter is  -- shift a left by b (as int)
 begin
   --y <= a sll to_integer(unsigned(b));
-  y <= std_logic_vector(shift_left(signed(a), to_integer(unsigned(b))));
+  shift_amount <= to_integer(unsigned(b(4 downto 0)));
+  y <= std_logic_vector(shift_left(signed(a), shift_amount));
 end;