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@AlexFW16
AlexFW16 committed Jun 3, 2023
1 parent b752947 commit 64c5a0b
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Showing 14 changed files with 38,953 additions and 31 deletions.
5,609 changes: 5,609 additions & 0 deletions project/template_2/convert.txt
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18 changes: 18 additions & 0 deletions project/template_2/program.txt
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00000513
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00000593
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163 changes: 132 additions & 31 deletions project/template_2/riscvsingle.vhdl
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Expand Up @@ -127,7 +127,9 @@ architecture struct of riscvsingle is
Jump: out STD_ULOGIC;
ImmSrc: out STD_ULOGIC_VECTOR(2 downto 0); -- 1 down to 0 before
ALUControl: out STD_ULOGIC_VECTOR(2 downto 0);
BLT,ShiftSrc: out STD_ULOGIC); -- new
BLT,ShiftSrc: out STD_ULOGIC;
Jalr: out STD_ULOGIC
); -- new
end component;
component datapath
port(clk, reset: in STD_ULOGIC;
Expand All @@ -143,21 +145,27 @@ architecture struct of riscvsingle is
Instr: in STD_ULOGIC_VECTOR(31 downto 0);
ALUResult, WriteData: out STD_ULOGIC_VECTOR(31 downto 0);
ReadData: in STD_ULOGIC_VECTOR(31 downto 0);
Jump: in STD_ULOGIC);
Jalr: in STD_ULOGIC
);
end component;

signal RegWrite, Jump, Zero, PCSrc, BLT, ShiftSrc: STD_ULOGIC;
signal RegWrite, Jump, Zero, PCSrc, BLT, ShiftSrc, Jalr: STD_ULOGIC;
signal ResultSrc, ALUSrc: STD_ULOGIC_VECTOR(1 downto 0);
signal ALUControl, ImmSrc: STD_ULOGIC_VECTOR(2 downto 0);
begin




c: controller port map(Instr(6 downto 0), Instr(14 downto 12),
Instr(30), Zero, ResultSrc, MemWrite,
PCSrc, ALUSrc, RegWrite, Jump,
ImmSrc, ALUControl, BLT, ShiftSrc);
ImmSrc, ALUControl, BLT, ShiftSrc, Jalr);
dp: datapath port map(clk, reset, ResultSrc, PCSrc, ALUSrc,
RegWrite, ImmSrc, ALUControl, BLT, ShiftSrc, Zero,
PC, Instr, ALUResult, WriteData,
ReadData, Jump); -- added BLT and ShiftSrc
ReadData, Jalr); -- added BLT and ShiftSrc



end;

Expand All @@ -176,7 +184,9 @@ entity controller is -- single-cycle controller
Jump: out STD_ULOGIC;
ImmSrc: out STD_ULOGIC_VECTOR(2 downto 0); -- 1 down to 0 before
ALUControl: out STD_ULOGIC_VECTOR(2 downto 0);
BLT,ShiftSrc: out STD_ULOGIC); -- new
BLT,ShiftSrc: out STD_ULOGIC;
Jalr: out STD_ULOGIC
); -- new
end;

architecture struct of controller is
Expand All @@ -190,7 +200,7 @@ architecture struct of controller is
RegWrite, Jump: out STD_ULOGIC;
ImmSrc: out STD_ULOGIC_VECTOR(2 downto 0); -- 1 down to 0 before
ALUOp: out STD_ULOGIC_VECTOR(1 downto 0);
BLT,ShiftSrc: out STD_ULOGIC); -- new
BLT,ShiftSrc, Jalr: out STD_ULOGIC); -- new
end component;
component aludec
port(opb5: in STD_ULOGIC;
Expand All @@ -205,7 +215,7 @@ architecture struct of controller is
signal Jump_s : STD_ULOGIC;
begin
md: maindec port map(op, funct3, ResultSrc, ALUSrc, MemWrite, Branch,
RegWrite, Jump_s, ImmSrc, ALUOp);
RegWrite, Jump_s, ImmSrc, ALUOp, BLT, ShiftSrc, Jalr);
ad: aludec port map(op(5), funct3, funct7b5, ALUOp, ALUControl);

PCSrc <= (Branch and Zero) or Jump_s;
Expand All @@ -225,32 +235,55 @@ entity maindec is -- main control decoder
RegWrite, Jump: out STD_ULOGIC;
ImmSrc: out STD_ULOGIC_VECTOR(2 downto 0);
ALUOp: out STD_ULOGIC_VECTOR(1 downto 0);
BLT,ShiftSrc: out STD_ULOGIC); -- new
BLT,ShiftSrc, Jalr: out STD_ULOGIC); -- new
end;

architecture behave of maindec is
signal controls: STD_ULOGIC_VECTOR(14 downto 0);
signal controls: STD_ULOGIC_VECTOR(15 downto 0);
begin
process(op,funct3) begin -- We should have implemented SHIFT as an ALU function, then we would not have to decode funct3 here. Too late for that now...

process(op, funct3) begin -- We should have implemented SHIFT as an ALU function, then we would not have to decode funct3 here. Too late for that now...

--debug
-- report "OP" severity note;
--report to_string(op) severity note;

-- report "control" severity note;
-- report to_string(controls) severity note;




report "Branch = " & to_string(Branch);


case op is
when "0000011" => controls <= "1000010010000-0"; -- lw
when "0100011" => controls <= "0001011000000-0"; -- sw
when "0110011" => controls <= "1---000000100-0"; -- R-type
when "0000011" => controls <= "1000010010000-00"; -- lw
when "0100011" => controls <= "0001011000000-00"; -- sw
when "0110011" => controls <= "1---000000100-00"; -- R-type
when "1100011" => case funct3 is -- B-type
when "000" => controls <= "001000000101000"; -- beq
when "100" => controls <= "0010000--110010"; -- blt
when others => controls <= "---------------"; -- not valid
when "000" => controls <= "0010000001010000"; -- beq
when "100" => controls <= "0010000--1100100"; -- blt
when others => controls <= "----------------"; -- not valid
end case;
when "0010011" => controls <= "1000010000100-0"; -- I-type ALU
when "1101111" => controls <= "1011000100001-0"; -- jal
when "1100111" => controls <= "1000010100001-0"; -- jalr
when "0010111" => controls <= "1100100000000-1"; -- U-Type (auipc)
when others => controls <= "---------------"; -- not valid
when "0010011" => case funct3 is
when "001" => controls <= "1000010110100-00"; -- slli
when others => controls <= "1000010000100-00"; -- I-type ALU
end case;

when "1101111" => controls <= "1011000100001-00"; -- jal
when "1100111" => controls <= "1000010100001-01"; -- jalr
when "0010111" => controls <= "1100100000000-10"; -- U-Type (auipc)
when others => controls <= "----------------"; -- not valid
end case;


end process;

(RegWrite, ImmSrc(2), ImmSrc(1), ImmSrc(0), ALUSrc(1), ALUSrc(0), MemWrite,
ResultSrc(1), ResultSrc(0), Branch, ALUOp(1), ALUOp(0), Jump, BLT, ShiftSrc) <= controls;
ResultSrc(1), ResultSrc(0), Branch, ALUOp(1), ALUOp(0), Jump, BLT, ShiftSrc, Jalr) <= controls;


end;

library IEEE;
Expand Down Expand Up @@ -278,6 +311,7 @@ begin
else
ALUControl <= "000"; -- add, addi
end if;
when "100" => ALUControl <= "001"; -- blt
when "010" => ALUControl <= "101"; -- slt, slti
when "110" => ALUControl <= "011"; -- or, ori
when "111" => ALUControl <= "010"; -- and, andi
Expand All @@ -289,7 +323,7 @@ end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--use IEEE.STD_LOGIC_ARITH.all;

entity datapath is -- RISC-V datapath
port(clk, reset: in STD_ULOGIC; -- TODO
Expand All @@ -305,9 +339,13 @@ entity datapath is -- RISC-V datapath
Instr: in STD_ULOGIC_VECTOR(31 downto 0);
ALUResult, WriteData: out STD_ULOGIC_VECTOR(31 downto 0);
ReadData: in STD_ULOGIC_VECTOR(31 downto 0);
Jump: in STD_ULOGIC);
Jalr: in STD_ULOGIC
);
end;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
architecture struct of datapath is
component flopr generic(width: integer);
port(clk, reset: in STD_ULOGIC;
Expand Down Expand Up @@ -374,16 +412,75 @@ architecture struct of datapath is
signal SrcA, SrcB: STD_ULOGIC_VECTOR(31 downto 0); --new
signal ShiftA, ShiftB, ShiftOut: STD_ULOGIC_VECTOR(31 downto 0); --new
signal Result: STD_ULOGIC_VECTOR(31 downto 0);
signal Zero_s, ZeroMuxOut: STD_ULOGIC;
signal Zero_s: STD_ULOGIC;
signal PC_s, WriteData_s, ALUResult_s : STD_ULOGIC_VECTOR(31 downto 0);
begin
-- next PC logic
pcreg: flopr generic map(32) port map(clk, reset, PCNext, PC_s);
pcadd4: adder port map(PC_s, X"00000004", PCPlus4);
pcaddbranch: adder port map(PC_s, ImmExt, PCTarget);
pcmux: mux3_pc generic map(32) port map(PCPlus4, PCTarget, ALUResult_s, (Jump & PCSrc), PCNext);
pcmux: mux3_pc generic map(32) port map(PCPlus4, PCTarget, ALUResult_s, (Jalr & PCSrc), PCNext);

PC <= PC_s;

process(PC_s) begin
report "-------------------" severity note;
report "PC = " & integer'image(to_integer(unsigned(PC_s)));

report "Result Src" severity note;
report to_string(ResultSrc) severity note;


report "Result" severity note;
report to_string(Result) severity note;

report "ALUResult" severity note;
report to_string(ALUResult) severity note;

report "SrcA" severity note;
report to_string(SRCA) severity note;

report "SrcB" severity note;
report to_string(SRCB) severity note;


report "ALUControl" severity note;
report to_string(ALUControl) severity note;

report "ALUSrc" severity note;
report to_string(ALUSrc) severity note;


report "Zero = " & to_string(Zero);
report "BLT = " & to_string(BLT);
report "ALUResult(31) = " & to_string(ALUResult_s(31));
report "zero_s = " & to_string(Zero_s);

report "--------";
report " " & to_string(Zero_s);
report "zero_s = " & to_string(Zero_s);



report "\n" severity note;


-- report "ShiftA" severity note;
-- report to_string(ShiftA) severity note;

-- report "ShiftB" severity note;
-- report to_string(ShiftB) severity note;

-- report "ShiftOut" severity note;
-- report to_string(ShiftOut) severity note;



end process;





-- register file logic
rf: regfile port map(clk, RegWrite, Instr(19 downto 15), Instr(24 downto 20),
Expand All @@ -392,21 +489,24 @@ begin

-- Shift logic
shiftmuxa: mux2 generic map(32) port map(RD1, ImmExt, ShiftSrc, ShiftA);
shiftmuxb: mux2 generic map(32) port map(ImmExt, X"00000012", ShiftSrc, ShiftB);
shiftmuxb: mux2 generic map(32) port map(ImmExt, X"0000000C", ShiftSrc, ShiftB);
shift: shifter port map(ShiftA, ShiftB, ShiftOut);


-- ALU logic
srcamux: mux2 generic map(32) port map(RD1, ShiftOut, ShiftSrc, SrcA);

srcbmux: mux3 generic map(32) port map(WriteData_s, ImmExt, PC_s, ALUSrc, SrcB);

mainalu: alu port map(SrcA, SrcB,ALUControl, ALUResult_s, Zero_s);
mainalu: alu port map(SrcA, SrcB, ALUControl, ALUResult_s, Zero_s);
resultmux: mux4 generic map(32) port map(ALUResult_s, ReadData, PCPlus4, ShiftOut, ResultSrc,
Result);
zeromux: mux2_single port map(Zero_s, ALUResult_s(31), BLT, Zero);

ALUResult <= ALUResult_s;
WriteData <= WriteData_s;


end;

library IEEE;
Expand Down Expand Up @@ -494,7 +594,8 @@ begin
immext <= (31 downto 0 => '-');
end case;
end process;
end;

end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
Expand Down
45 changes: 45 additions & 0 deletions project/template_2/sim/work-obj08.cf
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v 4
file "/home/vagrant/Desktop/projekt/rearch/project/template_2/" "riscvsingle.vhdl" "aa1d58c76212744e1865e2edf6ac7b95db861c3c" "20230603004832.294":
package checkresultpkg at 93( 3086) + 0 on 4268;
entity riscvsingle at 105( 3454) + 0 on 4269;
architecture struct of riscvsingle at 117( 3910) + 0 on 4270;
entity controller at 172( 6348) + 0 on 4271;
architecture struct of controller at 192( 7153) + 0 on 4272;
entity maindec at 225( 8473) + 0 on 4273;
architecture behave of maindec at 241( 9102) + 0 on 4274;
entity aludec at 289( 10723) + 0 on 4275;
architecture behave of aludec at 300( 11046) + 0 on 4276;
entity datapath at 324( 12176) + 0 on 4277;
architecture struct of datapath at 346( 13173) + 0 on 4278;
entity regfile at 512( 18826) + 0 on 4279;
architecture behave of regfile at 525( 19213) + 0 on 4280;
entity adder at 551( 19993) + 0 on 4281;
architecture behave of adder at 560( 20193) + 0 on 4282;
entity extend at 565( 20285) + 0 on 4283;
architecture behave of extend at 574( 20527) + 0 on 4284;
entity flopr at 600( 21386) + 0 on 4285;
architecture asynchronous of flopr at 611( 21701) + 0 on 4286;
entity flopenr at 620( 21900) + 0 on 4287;
architecture asynchronous of flopenr at 631( 22240) + 0 on 4288;
entity mux2 at 640( 22467) + 0 on 4289;
architecture behave of mux2 at 650( 22732) + 0 on 4290;
entity mux2_single at 655( 22805) + 0 on 4291;
architecture behave of mux2_single at 665( 23027) + 0 on 4292;
entity mux3 at 670( 23107) + 0 on 4293;
architecture behave of mux3 at 680( 23405) + 0 on 4294;
entity mux3_pc at 690( 23611) + 0 on 4295;
architecture behave of mux3_pc at 700( 23912) + 0 on 4296;
entity mux4 at 710( 24121) + 0 on 4297;
architecture behave of mux4 at 720( 24427) + 0 on 4298;
entity shifter at 731( 24672) + 0 on 4299;
architecture behave of shifter at 741( 24879) + 0 on 4300;
entity testbench at 748( 25082) + 0 on 4301;
architecture test of testbench at 756( 25227) + 0 on 4302;
entity top at 804( 27101) + 0 on 4303;
architecture test of top at 814( 27382) + 0 on 4304;
entity imem at 849( 28673) + 0 on 4305;
architecture behave of imem at 860( 28932) + 0 on 4306;
entity dmem at 888( 29709) + 0 on 4307;
architecture behave of dmem at 900( 30001) + 0 on 4308;
entity alu at 925( 30670) + 0 on 4309;
architecture behave of alu at 936( 30973) + 0 on 4310;
25 changes: 25 additions & 0 deletions project/template_2/test
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SRC = riscvsingle.vhdl

SIMDIR = sim

GHDL_FLAGS = --std=08 --ieee=synopsys --workdir=$(SIMDIR)

all: syntax analyse elaborate run

syntax:
[ -d $(SIMDIR) ] || mkdir -p $(SIMDIR)
ghdl -s $(GHDL_FLAGS) $(SRC)

analyse: syntax
ghdl -a -Wno-hide -Wno-library $(GHDL_FLAGS) $(SRC)

elaborate: analyse
ghdl -e $(GHDL_FLAGS) testbench

run: elaborate
ghdl -r $(GHDL_FLAGS) testbench --wave=trace.ghw --vcd=trace.vcd --ieee-asserts=disable

clean:
rm -rf $(SIMDIR)
rm -f *.o
rm -f testbench
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