Update riscvsingle.vhdl

AlexFW16 · Jun 2, 2023 · 72a6a1a · 72a6a1a
1 parent 14c0e29
commit 72a6a1a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
@@ -451,7 +451,7 @@ entity shifter is -- shifter
        y:     out STD_ULOGIC_VECTOR(31 downto 0));
 end;
 
-architecture behave of adder is  -- shift a left by b (as int)
+architecture behave of shifter is  -- shift a left by b (as int)
   begin
     y <= a sll to_integer(unsigned(b));
   end;