Update riscvsingle.vhdl

AlexFW16 · Jun 2, 2023 · 770d8c8 · 770d8c8
1 parent f908670
commit 770d8c8
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
@@ -606,14 +606,16 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.NUMERIC_STD.all;
 
+
 entity shifter is -- shifter
   port(a, b : in  STD_ULOGIC_VECTOR(31 downto 0);
        y:     out STD_ULOGIC_VECTOR(31 downto 0));
 end;
 
 architecture behave of shifter is  -- shift a left by b (as int)
 begin
-  y <= a sll to_integer(unsigned(b));
+  --y <= a sll to_integer(unsigned(b));
+  y <= shift_left(a, b);
 end;