Update riscvsingle.vhdl

AlexFW16 · Jun 2, 2023 · a792ede · a792ede
1 parent bc83f7c
commit a792ede
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
@@ -204,7 +204,7 @@ architecture struct of controller is
   signal Branch: STD_ULOGIC;
   signal Jump_s : STD_ULOGIC;
 begin
-  md: maindec port map(op, ResultSrc, MemWrite, Branch,
+  md: maindec port map(op, funct3, ResultSrc, MemWrite, Branch,
                        ALUSrc, RegWrite, Jump_s, ImmSrc, ALUOp);
   ad: aludec port map(op(5), funct3, funct7b5, ALUOp, ALUControl);