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Update riscvsingle.vhdl
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michael9186 committed Jun 2, 2023
1 parent 06e919c commit bab2299
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3 changes: 3 additions & 0 deletions project/template_2/riscvsingle.vhdl
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Expand Up @@ -546,6 +546,9 @@ begin
y <= d1 when s='1' else d0;
end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux2_single is -- two-input multiplexer
port(d0: in STD_ULOGIC;
d1: in STD_ULOGIC;
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