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feat: Avoid requiring arith gates in sequence (#4869)
Another installation in the series of PRs to allow for trace sorting. A common pattern in the builder is that the final gate in some sequence (usually aux or sort gates) is an arithmetic gate that serves two purposes: (1) provides wires values to the preceding gate via shifts, and (2) performs some check expressed as an arithmetic constraint. This causes problems if we sort the gates by type, which brings the arithmetic gate out of sequence. The solution is simply to add a dummy gate (for purpose 1) prior to the arithmetic gate (purpose 2). Note 1: I've added a `create_dummy_constraint` method and used it in some places to replace equivalent logic. Note 2: The additional dummy gate in the process ROM array logic changes the vkey for circuits that use it, hence the updated vk hash in the js test that checks vk hash consistency. No change: ``` -------------------------------------------------------------------------------- Benchmark Time CPU Iterations UserCounters... -------------------------------------------------------------------------------- ClientIVCBench/Full/6 32585 ms 26673 ms ```
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