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[RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (llvm#71501)
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vmv.s.x and vmv.x.s ignore LMUL, so we can replace the PseudoVMV_S_X_MX
and
PseudoVMV_X_S_MX with just one pseudo each. These pseudos use the VR
register
class (just like the actual instruction), so we now only have TableGen
patterns for vectors of LMUL <= 1.
We now rely on the existing combines that shrink LMUL down to 1 for
vmv_s_x_vl (and vfmv_s_f_vl). We could look into removing these combines
later and just inserting the nodes with the correct type in a later
patch.

The test diff is due to the fact that a PseudoVMV_S_X/PsuedoVMV_X_S no
longer
carries any information about LMUL, so if it's the only vector pseudo
instruction in a block then it now defaults to LMUL=1.
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@lukel97
lukel97 authored Jan 16, 2024
1 parent 44aa4d7 commit 286a366
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Showing 34 changed files with 859 additions and 886 deletions.
11 changes: 11 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15732,6 +15732,17 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,

break;
}
case RISCVISD::VMV_X_S: {
SDValue Vec = N->getOperand(0);
MVT VecVT = N->getOperand(0).getSimpleValueType();
const MVT M1VT = getLMUL1VT(VecVT);
if (M1VT.bitsLT(VecVT)) {
Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Vec,
DAG.getVectorIdxConstant(0, DL));
return DAG.getNode(RISCVISD::VMV_X_S, DL, N->getSimpleValueType(0), Vec);
}
break;
}
case ISD::INTRINSIC_VOID:
case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_WO_CHAIN: {
Expand Down
34 changes: 14 additions & 20 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Original file line number Diff line number Diff line change
Expand Up @@ -6764,24 +6764,18 @@ defm PseudoVID : VPseudoVID_V;

let Predicates = [HasVInstructions] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
foreach m = MxList in {
defvar mx = m.MX;
let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VMV_X_S in
def PseudoVMV_X_S # "_" # mx:
Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, ixlenimm:$sew), []>,
Sched<[WriteVIMovVX, ReadVIMovVX]>,
RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
Constraints = "$rd = $rs1" in
def PseudoVMV_S_X # "_" # mx: Pseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, GPR:$rs2,
AVL:$vl, ixlenimm:$sew),
[]>,
Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>,
RISCVVPseudo;
}
}
let HasSEWOp = 1, BaseInstr = VMV_X_S in
def PseudoVMV_X_S:
Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>,
Sched<[WriteVIMovVX, ReadVIMovVX]>,
RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
Constraints = "$rd = $rs1" in
def PseudoVMV_S_X: Pseudo<(outs VR:$rd),
(ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),
[]>,
Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>,
RISCVVPseudo;
}
} // Predicates = [HasVInstructions]

Expand Down Expand Up @@ -7408,10 +7402,10 @@ defm : VPatNullaryV<"int_riscv_vid", "PseudoVID">;
// 16.1. Integer Scalar Move Instructions
//===----------------------------------------------------------------------===//

foreach vti = AllIntegerVectors in {
foreach vti = NoGroupIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in
def : Pat<(XLenVT (riscv_vmv_x_s (vti.Vector vti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVMV_X_S_" # vti.LMul.MX) $rs2, vti.Log2SEW)>;
(PseudoVMV_X_S $rs2, vti.Log2SEW)>;
// vmv.s.x is handled with a custom node in RISCVInstrInfoVVLPatterns.td
}

Expand Down
26 changes: 16 additions & 10 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2794,16 +2794,19 @@ foreach mti = AllMasks in {
// 16. Vector Permutation Instructions

// 16.1. Integer Scalar Move Instructions
// 16.4. Vector Register Gather Instruction
foreach vti = AllIntegerVectors in {
foreach vti = NoGroupIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge),
vti.ScalarRegClass:$rs1,
VLOpFrag)),
(!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
vti.RegClass:$merge,
(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
(PseudoVMV_S_X $merge, vti.ScalarRegClass:$rs1, GPR:$vl,
vti.Log2SEW)>;
}
}

// 16.4. Vector Register Gather Instruction
foreach vti = AllIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
vti.RegClass:$rs1,
vti.RegClass:$merge,
Expand Down Expand Up @@ -2851,18 +2854,21 @@ foreach vti = AllIntegerVectors in {
}

// 16.2. Floating-Point Scalar Move Instructions
foreach vti = AllFloatVectors in {
foreach vti = NoGroupFloatVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
(vti.Scalar (fpimm0)),
VLOpFrag)),
(!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
vti.RegClass:$merge, (XLenVT X0), GPR:$vl, vti.Log2SEW)>;
(PseudoVMV_S_X $merge, (XLenVT X0), GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
(vti.Scalar (SelectFPImm (XLenVT GPR:$imm))),
VLOpFrag)),
(!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
vti.RegClass:$merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>;
(PseudoVMV_S_X $merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>;
}
}

foreach vti = AllFloatVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
vti.ScalarRegClass:$rs1,
VLOpFrag)),
Expand Down
8 changes: 1 addition & 7 deletions llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -370,13 +370,7 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
return MI.getOperand(1).getReg() == RISCV::X0;
case RISCV::PseudoAtomicLoadNand32:
return true;
case RISCV::PseudoVMV_X_S_MF8:
case RISCV::PseudoVMV_X_S_MF4:
case RISCV::PseudoVMV_X_S_MF2:
case RISCV::PseudoVMV_X_S_M1:
case RISCV::PseudoVMV_X_S_M2:
case RISCV::PseudoVMV_X_S_M4:
case RISCV::PseudoVMV_X_S_M8: {
case RISCV::PseudoVMV_X_S: {
// vmv.x.s has at least 33 sign bits if log2(sew) <= 5.
int64_t Log2SEW = MI.getOperand(2).getImm();
assert(Log2SEW >= 3 && Log2SEW <= 6 && "Unexpected Log2SEW");
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ body: |
; CHECK-NEXT: renamable $v0 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8)
; CHECK-NEXT: $x10 = LD $x2, 8 :: (load (s64) from %stack.15)
; CHECK-NEXT: renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: renamable $x13 = PseudoVMV_X_S killed renamable $v0, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: BLT killed renamable $x16, renamable $x27, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -206,7 +206,7 @@ body: |
renamable $x13 = nsw ADDI renamable $x16, -2
renamable $v0 = VL1RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8)
renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3, 1, implicit $vl, implicit $vtype
renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3, implicit $vl, implicit $vtype
renamable $x13 = PseudoVMV_X_S killed renamable $v0, 3, implicit $vl, implicit $vtype
BLT killed renamable $x16, renamable $x27, %bb.2
bb.1:
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
; CHECK-LABEL: extractelt_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i8> %v, i32 0
Expand Down Expand Up @@ -40,7 +40,7 @@ define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 %idx) {
define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
; CHECK-LABEL: extractelt_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i8> %v, i32 0
Expand Down Expand Up @@ -72,7 +72,7 @@ define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 %idx) {
define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
; CHECK-LABEL: extractelt_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i8> %v, i32 0
Expand Down Expand Up @@ -232,7 +232,7 @@ define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 %idx) {
define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
; CHECK-LABEL: extractelt_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i16> %v, i32 0
Expand Down Expand Up @@ -264,7 +264,7 @@ define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 %idx) {
define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
; CHECK-LABEL: extractelt_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i16> %v, i32 0
Expand Down Expand Up @@ -424,7 +424,7 @@ define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 %idx) {
define i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
; CHECK-LABEL: extractelt_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i32> %v, i32 0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
; CHECK-LABEL: extractelt_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i8> %v, i32 0
Expand Down Expand Up @@ -39,7 +39,7 @@ define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 zeroext %idx)
define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
; CHECK-LABEL: extractelt_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i8> %v, i32 0
Expand Down Expand Up @@ -71,7 +71,7 @@ define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 zeroext %idx)
define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
; CHECK-LABEL: extractelt_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i8> %v, i32 0
Expand Down Expand Up @@ -231,7 +231,7 @@ define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 zeroext %id
define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
; CHECK-LABEL: extractelt_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i16> %v, i32 0
Expand Down Expand Up @@ -263,7 +263,7 @@ define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 zeroext %i
define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
; CHECK-LABEL: extractelt_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i16> %v, i32 0
Expand Down Expand Up @@ -423,7 +423,7 @@ define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 zeroext
define signext i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
; CHECK-LABEL: extractelt_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i32> %v, i32 0
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,13 +32,13 @@ define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
define i8 @bitcast_v1i8_i8(<1 x i8> %a) {
; CHECK-LABEL: bitcast_v1i8_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v1i8_i8:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; ELEN32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <1 x i8> %a to i8
Expand All @@ -48,13 +48,13 @@ define i8 @bitcast_v1i8_i8(<1 x i8> %a) {
define i16 @bitcast_v2i8_i16(<2 x i8> %a) {
; CHECK-LABEL: bitcast_v2i8_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v2i8_i16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <2 x i8> %a to i16
Expand All @@ -64,13 +64,13 @@ define i16 @bitcast_v2i8_i16(<2 x i8> %a) {
define i16 @bitcast_v1i16_i16(<1 x i16> %a) {
; CHECK-LABEL: bitcast_v1i16_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v1i16_i16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <1 x i16> %a to i16
Expand All @@ -80,7 +80,7 @@ define i16 @bitcast_v1i16_i16(<1 x i16> %a) {
define i32 @bitcast_v4i8_i32(<4 x i8> %a) {
; CHECK-LABEL: bitcast_v4i8_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
Expand All @@ -96,7 +96,7 @@ define i32 @bitcast_v4i8_i32(<4 x i8> %a) {
define i32 @bitcast_v2i16_i32(<2 x i16> %a) {
; CHECK-LABEL: bitcast_v2i16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
Expand All @@ -112,7 +112,7 @@ define i32 @bitcast_v2i16_i32(<2 x i16> %a) {
define i32 @bitcast_v1i32_i32(<1 x i32> %a) {
; CHECK-LABEL: bitcast_v1i32_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
Expand Down Expand Up @@ -433,13 +433,13 @@ define double @bitcast_v1i64_f64(<1 x i64> %a) {
define <1 x i16> @bitcast_i16_v1i16(i16 %a) {
; CHECK-LABEL: bitcast_i16_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_i16_v1i16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; ELEN32-NEXT: vmv.s.x v8, a0
; ELEN32-NEXT: ret
%b = bitcast i16 %a to <1 x i16>
Expand All @@ -449,7 +449,7 @@ define <1 x i16> @bitcast_i16_v1i16(i16 %a) {
define <2 x i16> @bitcast_i32_v2i16(i32 %a) {
; CHECK-LABEL: bitcast_i32_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
;
Expand All @@ -465,7 +465,7 @@ define <2 x i16> @bitcast_i32_v2i16(i32 %a) {
define <1 x i32> @bitcast_i32_v1i32(i32 %a) {
; CHECK-LABEL: bitcast_i32_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
;
Expand Down
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