Stur instructions

…UQ-PAC/bap into implement-missing-aarch64-insns

separated into category files

LLVM can't seem to disassemble ARMv8.4 instructions like RMIF, SETF8
and SETF16. Also, CFINV gets turned into MSR (register) but LLVM
returns ill-formed asm...?
I've commented this in aarch64-pstate.lisp.

i typed is_zero with underscore instead of primitive is-zero

documentation added for macros and helper functions.

…UQ-PAC/bap into implement-missing-aarch64-insns

llvm mnemonics most likely incorrect, will investigate
why bap's llvm doesn't disassemble these insns

i've used ` bap mc --cpu=cortex-a55 --triple=aarch64`
to get the llvm mnemonic, but will need to talk to ivan
about lisp context and
specifying generic armv8.x instead of a specific cpu

…arch64-insns

…UQ-PAC/bap into implement-missing-aarch64-insns

… into tests-1458

The Primus Lisp semantic primitives were hardcoding 64-bit
arithmetic, which was obviously incorrect. In addition, the
shifting operations were coercing the operands to the same size,
like in arithmetic operations, which contradicts the established
semantics of shifts both in Core Theory and in BIL. Now, the shifting
operators will produce values of the same sort as the sort of the
first operand.

 updates to changes in BAP, improving `clz`

the result in decode-bit-masks should only be
replicated to the width of the registers being assigned to.
so, we need to pass in the register width when decoding.