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BHG_FP_CLK_DIVIDER_v1.2

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@BrianHGinc BrianHGinc released this 11 Aug 02:03
· 1 commit to main since this release
v1.2
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Verilog floating point fractional clock divider using 24.16 (m.n) math. v1.2, August 10, 2022.

  • v1.2a - Added a protection for when the integer divider has less than 2 bits.
  • v1.2b - Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.
  • v1.1 - Patches a simulation bug where Modelsim's 'Compile / Compile Options / Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.
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