Verilog RS232 Synch-UART & RS232 Debugger and PC host RS232 Hex-editor.
Debugger Hex Editor Changes v1.3, Jan 14, 2022.
- Now has an 'ENDIAN' setting which now shows you the correct 16bit values for 16bit ints.
- When editing cells, this also allows the use of the +/- keys to increment/decrement 16bit values with the new ENDIAN settings being taken into account.
- Also has a new Quartus save 32bit .mif files.
- Also, changing the ENDIAN before saving a 16bit or 32bit Quartus .mif file will also swap they byte order making it easy to render wide .mif files with reverse ENIANess.
This is a Verilog core which contains a PC compatible high speed Synchronous RS-232 UART and RS232 debugger server and real-time PC client software hex-editor with 4 utility 8 bit input ports and 4 utility 8 bit output ports.
The Verilog source is well documented in code. See the original project page from Nov 25, 2019 here: https://www.eevblog.com/forum/fpga/verilog-rs232-uart-and-rs232-debugger-source-code-and-educational-tutorial/
There are 3 pieces:
-
The ' SYNC_RS232_UART.v ' : A synchronizing RS232 transceiver. The 'synchronizing' transmitter with the receiver is crucial when interfacing with a PC as high speed full duplex communication require that the bit and word timing of serial data coming into the PC matches the clock and phase of the data the PC may be transmitting out at the same time. Many simple example Verilog RS232 UARTs arent capable of this. Read attached source code and see attached illustration to show you an example setup where my transmitter aligns itself to a received RS232 serial signal with a slightly different baud rate.
-
The ' RS232_Debugger.v ' : A Verilog module which uses the SYNC_RS232_UART.v, has an RS232 RXD input and TXD output. It also has a memory address output and 8 bit memory data input and output with a memory read request and memory write enable. This module also provides a reset output, 4 utility 8 bit output ports and 4 utility 8 bit input ports. Once again, everything is documented in the available 'RS232_Debugger.v' source code and I'm here to answer questions.
-
The ' RS232_Debugger.exe ' Viewer / HEX editor software. The software offers real-time viewing and editing of the user configured memory size set in the RS232_Debugger.v's memory address size parameter while also continuously displaying the values of the 4 utility 8 bit input ports as well as being able to set the values of the 4 utility 8 bit output ports. When the RS232 com port is closed, the RS232_Debugger.exe functions as a stand alone HEX / ASCII file editor which can edit up to 1 megabyte files.
The Verilog code was written using pure synchronous logic. No fancy async-reset/presets, no S/R, J-K flipflops. These examples should easily integrate into any vendor's FPGAs EDA tool platform. If anyone out there has success, let us know.