7-stage-MIPS-pipeline-CPU

assignment of Arch, modified on Loongson backbone

Contains identifiable bugs that I am not able to fix, be aware of the potential risk of direct copying.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
pipeline.cache		pipeline.cache
pipeline.hw		pipeline.hw
pipeline.ip_user_files		pipeline.ip_user_files
pipeline.runs		pipeline.runs
pipeline.sim/sim_1		pipeline.sim/sim_1
pipeline.srcs		pipeline.srcs
README.md		README.md
adder.v		adder.v
alu.v		alu.v
data_ram.ngc		data_ram.ngc
data_ram.v		data_ram.v
decode.v		decode.v
exe.v		exe.v
fetch.v		fetch.v
inst_rom.mif		inst_rom.mif
inst_rom.ngc		inst_rom.ngc
inst_rom.v		inst_rom.v
instructions.coe		instructions.coe
mem.v		mem.v
multiply.v		multiply.v
pipeline.xpr		pipeline.xpr
pipeline_cpu.v		pipeline_cpu.v
pipeline_cpu.xdc		pipeline_cpu.xdc
pipeline_cpu_display.v		pipeline_cpu_display.v
regfile.v		regfile.v
tb.v		tb.v
wb.v		wb.v

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