This project serves as a simple reference design for using the onboard DDR2 memory with Xilinx MIG IP of the Nexys 4 DDR / Nexys A7 FPGA Trainer board.
The included step-by-step PDF guide walks through the configuration process.
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ChrisPVille/mig_example
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Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
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