32-bit-ARM-Processor in Logisim

This is a 32-bit functional ARM processor capable of executing basic instructions in the ISA. It's a part of CSN-221 Computer Architecture course group project.

Video demonstration

Arm Single Cycle Processor implementation in logisim

Register File

Bit extender

Bit shifter

ALU

Control Unit

Main features

• Supports basic arithmetic and logical instructions.
• Has 15 32-bit-registers in a register file.
• ROM, RAM, ALU and Control Unit, along with shifter and extender logics

Supported Commands

• AND
• SUB
• ADD
• MOV
• ORR
• LSL
• LSR
• ASR
• STR
• LDR
• B

Acknowledgements

The project is based on the single cycle processor design proposed in the book Digital Design and Computer Architecture by David Harris & Sarah Harris. Link to the book is given below for reference.

Digital Design and Computer Architecture