ALU design in verilog

Operation table

op values	Operations	Status
000	Addition	✔️
001	Subtraction	✔️
010	And	✔️
011	Or	✔️
100	Not	✔️
101	Left Shift	✔️
110	Right Shift	✔️
111	Multiplication	✔️

Progress

Done

• CLA parameterised Adder
• RCA parameterised Adder
• Logic Operations
• Shifters
• Multiplier (Array)
• Combining all modules into 1 ALU

In-Progress

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Environment

• compiler - iverilog
• waveform veiwer - GTKWave

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Extras

Note -

For convinience

• Follow the following development convention
  • playground directory (./playground/) includes source files that are being construction
  • final directory (./final/src/) includes verified and working source files
• Run the following bash script

chmod +x ./scripts/bash_setup.sh
. ./scripts/bash_setup.sh

• Run the command

test -h