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swap ch32v003 swio get/put functions with PIO implementation. Not cur…
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…rently working.
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DESKTOP-M9CCUTI\ian committed Aug 5, 2024
1 parent 5a65ab2 commit ef8449d
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Showing 2 changed files with 34 additions and 18 deletions.
15 changes: 10 additions & 5 deletions lib/arduino-ch32v003-swio/arduino_ch32v003.c
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@
#include "usb_rx.h"
#include "usb_tx.h"
#include "tusb.h"
#include "lib/picorvd/picoswio.h"

void target_power(int x){
if (x)
Expand All @@ -35,19 +36,21 @@ void arduino_ch32v003(void) {

if(!tud_cdc_n_connected(1)) return;

if(!system_config.rts){
/*if(!system_config.rts){
//RTS is high, simulate arduino reset
//uart_init();
swio_init();
//swio_init();
bin_tx_fifo_put(PROTOCOL_START);
system_config.rts=1;
}
}*/

char c;

if(bin_rx_fifo_try_get(&c)) { //co-op multitask
switch (c) {
case PROTOCOL_TEST:
ch32vswio_reset(bio2bufiopin[BIO0], bio2bufdirpin[BIO0]);
bin_tx_fifo_put(PROTOCOL_ACK);
break;
case PROTOCOL_POWER_ON:
Expand All @@ -67,13 +70,15 @@ void arduino_ch32v003(void) {
bin_rx_fifo_get_blocking(&c);
val|=(c<<24);
}
swio_write_reg(reg, val);
//swio_write_reg(reg, val);
ch32vswio_put(reg, val);
bin_tx_fifo_put(PROTOCOL_ACK);
break;
case PROTOCOL_READ_REG:
//fread(&reg, sizeof(uint8_t), 1, uart);
bin_rx_fifo_get_blocking(&reg);
val = swio_read_reg(reg);
//val = swio_read_reg(reg);
val = ch32vswio_get(reg);
//fwrite(&val, sizeof(uint32_t), 1, uart);
for(uint8_t i=0;i<4;i++){
c=val&0xff;
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37 changes: 24 additions & 13 deletions lib/picorvd/picoswio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ Changed by: Ian Lesnet, 2024 Where Labs LLC for Bus Pirate 5
#include "ch32vswio.pio.h"
#include "debug_defines.h"
#include "hardware/pio.h"
//#include "utils.h"
#include "picoswio.h"

#define DUMP_COMMANDS

Expand All @@ -32,6 +32,10 @@ void ch32vswio_reset(int pin, int dirpin) {
gpio_set_slew_rate (pin, GPIO_SLEW_RATE_SLOW);
gpio_set_function (pin, GPIO_FUNC_PIO0);

gpio_set_drive_strength(dirpin, GPIO_DRIVE_STRENGTH_2MA);
gpio_set_slew_rate (dirpin, GPIO_SLEW_RATE_SLOW);
gpio_set_function (dirpin, GPIO_FUNC_PIO0);

// Reset PIO module
pio0->ctrl = 0b000100010001;
pio_sm_set_enabled(pio0, pio_sm, false);
Expand All @@ -45,37 +49,44 @@ void ch32vswio_reset(int pin, int dirpin) {
//in pin should be buffer IO
pio_sm_config c = pio_get_default_sm_config();
sm_config_set_wrap (&c, pio_offset + singlewire_wrap_target, pio_offset + singlewire_wrap);
sm_config_set_sideset (&c, 1, /*optional*/ false, /*pindirs*/ true);
sm_config_set_out_pins (&c, pin, 1);
//sm_config_set_sideset (&c, 1, /*optional*/ false, /*pindirs*/ true);
sm_config_set_sideset (&c, 1, /*optional*/ false, /*pindirs*/ false); //direct control of the buffer direction
sm_config_set_out_pins (&c, dirpin, 1);
sm_config_set_in_pins (&c, pin);
sm_config_set_set_pins (&c, pin, 1);
sm_config_set_set_pins (&c, dirpin, 1);
sm_config_set_sideset_pins(&c, dirpin);
sm_config_set_out_shift (&c, /*shift_right*/ false, /*autopull*/ false, /*pull_threshold*/ 32);
sm_config_set_in_shift (&c, /*shift_right*/ false, /*autopush*/ true, /*push_threshold*/ 32);

// 125 mhz / 12 = 96 nanoseconds per tick, close enough to 100 ns.
sm_config_set_clkdiv (&c, 12);

gpio_pull_down(pin);
pio_sm_set_pindirs_with_mask(pio0, pio_sm, 0, (1u<<pin)); //read pins to input (0, mask)
pio_sm_set_pindirs_with_mask(pio0, pio_sm, (1u<<dirpin), (1u<<dirpin)); //buf pins to output (pins, mask)
pio_sm_set_pins_with_mask(pio0, pio_sm, 0, (1u<<dirpin)); //buf dir to 0, buffer input/HiZ on the bus
pio_gpio_init(pio0, dirpin);

pio_sm_init (pio0, pio_sm, pio_offset, &c);
pio_sm_set_pins (pio0, pio_sm, 0);
//pio_sm_set_pins (pio0, pio_sm, 1);
pio_sm_set_enabled(pio0, pio_sm, true);

// Grab pin and send an 8 usec low pulse to reset debug module
// If we use the sdk functions to do this we get jitter :/
sio_hw->gpio_clr = (1 << pin);
/*sio_hw->gpio_clr = (1 << pin);
sio_hw->gpio_oe_set = (1 << pin);
iobank0_hw->io[pin].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
busy_wait_us(100); // ~8 usec
sio_hw->gpio_oe_clr = (1 << pin);
iobank0_hw->io[pin].ctrl = GPIO_FUNC_PIO0 << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;

*/
// Enable debug output pin on target
//put(WCH_DM_SHDWCFGR, 0x5AA50400);
//put(WCH_DM_CFGR, 0x5AA50400);
ch32vswio_put(WCH_DM_SHDWCFGR, 0x5AA50400);
ch32vswio_put(WCH_DM_CFGR, 0x5AA50400);

// Reset debug module on target
//put(DM_DMCONTROL, 0x00000000);
//put(DM_DMCONTROL, 0x00000001);
ch32vswio_put(DM_DMCONTROL, 0x00000000);
ch32vswio_put(DM_DMCONTROL, 0x00000001);
}

//------------------------------------------------------------------------------
Expand All @@ -85,7 +96,7 @@ uint32_t ch32vswio_get(uint32_t addr) {
pio_sm_put_blocking(pio0, 0, ((~addr) << 1) | 1);
uint32_t data = pio_sm_get_blocking(pio0, 0);
#ifdef DUMP_COMMANDS
printf("get_dbg %15s 0x%08x\n", ch32swio_addr_to_regname(addr), data);
printf("get_dbg %15s 0x%08x\r\n", ch32swio_addr_to_regname(addr), data);
#endif
return data;
}
Expand All @@ -95,7 +106,7 @@ uint32_t ch32vswio_get(uint32_t addr) {
void ch32vswio_put(uint32_t addr, uint32_t data) {
//cmd_count++;
#ifdef DUMP_COMMANDS
printf("set_dbg %15s 0x%08x\n", ch32swio_addr_to_regname(addr), data);
printf("set_dbg %15s 0x%08x\r\n", ch32swio_addr_to_regname(addr), data);
#endif
pio_sm_put_blocking(pio0, 0, ((~addr) << 1) | 0);
pio_sm_put_blocking(pio0, 0, ~data);
Expand Down

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