Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

i#6938 sched migrate: Add migration count to scheduler #6950

Merged
merged 2 commits into from
Aug 29, 2024
Merged

i#6938 sched migrate: Add migration count to scheduler #6950

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
480b49a
i#6938 sched migrate: Add migration count to scheduler
derekbruening Aug 29, 2024
6b956f4
Improve counter description
derekbruening Aug 29, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 5 additions & 0 deletions clients/drcachesim/common/memtrace_stream.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -93,6 +93,11 @@ class memtrace_stream_t {
SCHED_STAT_DIRECT_SWITCH_ATTEMPTS,
/** Count of #TRACE_MARKER_TYPE_DIRECT_THREAD_SWITCH attempts that succeeded. */
SCHED_STAT_DIRECT_SWITCH_SUCCESSES,
/**
* Counts the number of times an input switches from another core to this core:
* i.e., the number of input migrations to this core.
*/
SCHED_STAT_MIGRATIONS,
/** Count of statistic types. */
SCHED_STAT_TYPE_COUNT,
};
Expand Down
10 changes: 10 additions & 0 deletions clients/drcachesim/scheduler/scheduler.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -683,6 +683,8 @@ scheduler_tmpl_t<RecordType, ReaderType>::~scheduler_tmpl_t()
outputs_[i].stats[memtrace_stream_t::SCHED_STAT_DIRECT_SWITCH_ATTEMPTS]);
VPRINT(this, 1, " %-25s: %9" PRId64 "\n", "Direct switch successes",
outputs_[i].stats[memtrace_stream_t::SCHED_STAT_DIRECT_SWITCH_SUCCESSES]);
VPRINT(this, 1, " %-25s: %9" PRId64 "\n", "Migrations",
outputs_[i].stats[memtrace_stream_t::SCHED_STAT_MIGRATIONS]);
}
}

Expand Down Expand Up @@ -2621,6 +2623,14 @@ scheduler_tmpl_t<RecordType, ReaderType>::set_cur_input(output_ordinal_t output,

std::lock_guard<std::mutex> lock(*inputs_[input].lock);

if (inputs_[input].prev_output != INVALID_OUTPUT_ORDINAL &&
inputs_[input].prev_output != output) {
VPRINT(this, 3, "output[%d] migrating input %d from output %d\n", output, input,
inputs_[input].prev_output);
++outputs_[output].stats[memtrace_stream_t::SCHED_STAT_MIGRATIONS];
}
inputs_[input].prev_output = output;

if (prev_input < 0 && outputs_[output].stream->version_ == 0) {
// Set the version and filetype up front, to let the user query at init time
// as documented. Also set the other fields in case we did a skip for ROI.
Expand Down
1 change: 1 addition & 0 deletions clients/drcachesim/scheduler/scheduler.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1297,6 +1297,7 @@ template <typename RecordType, typename ReaderType> class scheduler_tmpl_t {
bool needs_advance = false;
bool needs_roi = true;
bool at_eof = false;
output_ordinal_t prev_output = INVALID_OUTPUT_ORDINAL;
uintptr_t next_timestamp = 0;
uint64_t instrs_in_quantum = 0;
int instrs_pre_read = 0;
Expand Down
28 changes: 15 additions & 13 deletions clients/drcachesim/tests/scheduler_unit_tests.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ static void
verify_scheduler_stats(scheduler_t::stream_t *stream, int64_t switch_input_to_input,
int64_t switch_input_to_idle, int64_t switch_idle_to_input,
int64_t switch_nop, int64_t preempts, int64_t direct_attempts,
int64_t direct_successes)
int64_t direct_successes, int64_t migrations)
{
// We assume our counts fit in the get_schedule_statistic()'s double's 54-bit
// mantissa and thus we can safely use "==".
Expand All @@ -156,6 +156,8 @@ verify_scheduler_stats(scheduler_t::stream_t *stream, int64_t switch_input_to_in
assert(stream->get_schedule_statistic(
memtrace_stream_t::SCHED_STAT_DIRECT_SWITCH_SUCCESSES) ==
direct_successes);
assert(stream->get_schedule_statistic(memtrace_stream_t::SCHED_STAT_MIGRATIONS) ==
migrations);
}

static void
Expand Down Expand Up @@ -1111,11 +1113,11 @@ test_synthetic()
verify_scheduler_stats(scheduler.get_stream(0), /*switch_input_to_input=*/10,
/*switch_input_to_idle=*/0, /*switch_idle_to_input=*/0,
/*switch_nop=*/0, /*preempts=*/6, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/7);
verify_scheduler_stats(scheduler.get_stream(1), /*switch_input_to_input=*/11,
/*switch_input_to_idle=*/1, /*switch_idle_to_input=*/0,
/*switch_nop=*/0, /*preempts=*/8, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/7);
#ifndef WIN32
// XXX: Windows microseconds on test VMs are very coarse and stay the same
// for long periods. Instruction quanta use wall-clock idle times, so
Expand Down Expand Up @@ -1300,11 +1302,11 @@ test_synthetic_time_quanta()
verify_scheduler_stats(scheduler.get_stream(0), /*switch_input_to_input=*/1,
/*switch_input_to_idle=*/1, /*switch_idle_to_input=*/0,
/*switch_nop=*/1, /*preempts=*/2, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/0);
verify_scheduler_stats(scheduler.get_stream(1), /*switch_input_to_input=*/2,
/*switch_input_to_idle=*/1, /*switch_idle_to_input=*/1,
/*switch_nop=*/0, /*preempts=*/1, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/1);
}
{
replay_file_checker_t checker;
Expand Down Expand Up @@ -1433,11 +1435,11 @@ test_synthetic_with_timestamps()
verify_scheduler_stats(scheduler.get_stream(0), /*switch_input_to_input=*/14,
/*switch_input_to_idle=*/1, /*switch_idle_to_input=*/0,
/*switch_nop=*/0, /*preempts=*/11, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/7);
verify_scheduler_stats(scheduler.get_stream(1), /*switch_input_to_input=*/12,
/*switch_input_to_idle=*/0, /*switch_idle_to_input=*/0,
/*switch_nop=*/2, /*preempts=*/9, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/8);
}

static void
Expand Down Expand Up @@ -1529,11 +1531,11 @@ test_synthetic_with_priorities()
verify_scheduler_stats(scheduler.get_stream(0), /*switch_input_to_input=*/12,
/*switch_input_to_idle=*/1, /*switch_idle_to_input=*/0,
/*switch_nop=*/2, /*preempts=*/9, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/8);
verify_scheduler_stats(scheduler.get_stream(1), /*switch_input_to_input=*/14,
/*switch_input_to_idle=*/0, /*switch_idle_to_input=*/0,
/*switch_nop=*/0, /*preempts=*/11, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/7);
}

static void
Expand Down Expand Up @@ -1861,11 +1863,11 @@ test_synthetic_with_syscalls_multiple()
verify_scheduler_stats(scheduler.get_stream(0), /*switch_input_to_input=*/17,
/*switch_input_to_idle=*/2, /*switch_idle_to_input=*/1,
/*switch_nop=*/2, /*preempts=*/11, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/9);
verify_scheduler_stats(scheduler.get_stream(1), /*switch_input_to_input=*/16,
/*switch_input_to_idle=*/1, /*switch_idle_to_input=*/1,
/*switch_nop=*/0, /*preempts=*/10, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/11);
}

static void
Expand Down Expand Up @@ -4261,7 +4263,7 @@ test_direct_switch()
verify_scheduler_stats(scheduler.get_stream(0), /*switch_input_to_input=*/3,
/*switch_input_to_idle=*/1, /*switch_idle_to_input=*/1,
/*switch_nop=*/0, /*preempts=*/0, /*direct_attempts=*/3,
/*direct_successes=*/2);
/*direct_successes=*/2, /*migrations=*/0);
}
{
// Test disabling direct switches.
Expand Down Expand Up @@ -4302,7 +4304,7 @@ test_direct_switch()
verify_scheduler_stats(scheduler.get_stream(0), /*switch_input_to_input=*/2,
/*switch_input_to_idle=*/2, /*switch_idle_to_input=*/2,
/*switch_nop=*/0, /*preempts=*/0, /*direct_attempts=*/0,
/*direct_successes=*/0);
/*direct_successes=*/0, /*migrations=*/0);
}
}

Expand Down
Loading