Improve 32bit constant usage in memory addressing

Update instcountci files.

FEXCore/Source/Interface/IR/PassManager.cpp

@@ -80,7 +80,8 @@ void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl *ctx, bool Inli
 
     InsertPass(CreateDeadStoreElimination(ctx->HostFeatures.SupportsAVX));
     InsertPass(CreatePassDeadCodeElimination());
-    InsertPass(CreateConstProp(InlineConstants, ctx->HostFeatures.SupportsTSOImm9));
+    InsertPass(CreateConstProp(
+        InlineConstants, ctx->HostFeatures.SupportsTSOImm9, Is64BitMode()));
 
     InsertPass(CreateDeadFlagCalculationEliminination());
 
@@ -121,5 +122,4 @@ bool PassManager::Run(IREmitter *IREmit) {
 
   return Changed;
 }
-
 }

FEXCore/Source/Interface/IR/Passes.h

@@ -16,15 +16,17 @@ class Pass;
 class RegisterAllocationPass;
 class RegisterAllocationData;
 
-fextl::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9);
+fextl::unique_ptr<FEXCore::IR::Pass>
+CreateConstProp(bool InlineConstants, bool SupportsTSOImm9, bool Is64BitMode);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination(bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateInlineCallOptimization(const FEXCore::CPUIDEmu* CPUID);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminination();
 fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination(bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreatePassDeadCodeElimination();
 fextl::unique_ptr<FEXCore::IR::Pass> CreateIRCompaction(FEXCore::Utils::IntrusivePooledAllocator &Allocator);
-fextl::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass,
-                                                                                  bool SupportsAVX);
+fextl::unique_ptr<FEXCore::IR::RegisterAllocationPass>
+CreateRegisterAllocationPass(FEXCore::IR::Pass *CompactionPass,
+                             bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateLongDivideEliminationPass();
 
 namespace Validation {

FEXCore/Source/Interface/IR/Passes/ConstProp.cpp

@@ -91,6 +91,7 @@ static bool IsTSOImm9(uint64_t imm) {
 }
 
 static std::tuple<MemOffsetType, uint8_t, OrderedNode*, OrderedNode*> MemExtendedAddressing(IREmitter *IREmit, uint8_t AccessSize,  IROp_Header* AddressHeader) {
+  LOGMAN_THROW_A_FMT(AddressHeader->Op == OP_ADD, "Invalid address Op");
   auto Src0Header = IREmit->GetOpHeader(AddressHeader->Args[0]);
   if (Src0Header->Size == 8) {
     //Try to optimize: Base + MUL(Offset, Scale)
@@ -141,7 +142,37 @@ static std::tuple<MemOffsetType, uint8_t, OrderedNode*, OrderedNode*> MemExtende
   }
 
   // no match anywhere, just add
-  return { MEM_OFFSET_SXTX, 1, IREmit->UnwrapNode(AddressHeader->Args[0]), IREmit->UnwrapNode(AddressHeader->Args[1]) };
+  // However, if we have one 32bit negative constant, we need to sign extend it
+  auto Arg0_ = AddressHeader->Args[0];
+  auto Arg1_ = AddressHeader->Args[1];
+  auto Arg0H = IREmit->GetOpHeader(Arg0_);
+  auto Arg1H = IREmit->GetOpHeader(Arg1_);
+  auto Arg0 = IREmit->UnwrapNode(Arg0_);
+  auto Arg1 = IREmit->UnwrapNode(Arg1_);
+
+  uint64_t ConstVal = 0;
+  OrderedNode *Cnt = nullptr;
+  OrderedNode *Base = nullptr;
+
+  if (IREmit->IsValueConstant(Arg0_, &ConstVal) && Arg0H->Size == 4) {
+    Cnt = Arg0;
+    Base = Arg1;
+  } else if (IREmit->IsValueConstant(Arg1_, &ConstVal) && Arg1H->Size == 4) {
+    Cnt = Arg1;
+    Base = Arg0;
+  }
+
+  if (Cnt) {
+    int32_t Val32 = (int32_t)ConstVal;
+
+    if (Val32 < 0) {
+      return {MEM_OFFSET_SXTW, 1, Base, Cnt};
+    } else {
+      return {MEM_OFFSET_SXTX, 1, Base, Cnt};
+    }
+  } else {
+    return {MEM_OFFSET_SXTX, 1, Arg0, Arg1};
+  }
 }
 
 static OrderedNodeWrapper RemoveUselessMasking(IREmitter *IREmit, OrderedNodeWrapper src, uint64_t mask) {
@@ -184,9 +215,10 @@ static bool IsBfeAlreadyDone(IREmitter *IREmit, OrderedNodeWrapper src, uint64_t
 
 class ConstProp final : public FEXCore::IR::Pass {
 public:
-  explicit ConstProp(bool DoInlineConstants, bool SupportsTSOImm9)
-    : InlineConstants(DoInlineConstants)
-    , SupportsTSOImm9 {SupportsTSOImm9} { }
+  explicit ConstProp(bool DoInlineConstants, bool SupportsTSOImm9,
+                     bool Is64BitMode)
+      : InlineConstants(DoInlineConstants), SupportsTSOImm9{SupportsTSOImm9},
+        Is64BitMode(Is64BitMode) {}
 
   bool Run(IREmitter *IREmit) override;
 
@@ -219,6 +251,7 @@ class ConstProp final : public FEXCore::IR::Pass {
     return Result.first->second;
   }
   bool SupportsTSOImm9{};
+  bool Is64BitMode;
   // This is a heuristic to limit constant pool live ranges to reduce RA interference pressure.
   // If the range is unbounded then RA interference pressure seems to increase to the point
   // that long blocks of constant usage can slow to a crawl.
@@ -525,12 +558,15 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
       auto Op = IROp->CW<IR::IROp_LoadMem>();
       auto AddressHeader = IREmit->GetOpHeader(Op->Addr);
 
-      if (AddressHeader->Op == OP_ADD && AddressHeader->Size == 8) {
-        auto [OffsetType, OffsetScale, Arg0, Arg1] = MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+      if (AddressHeader->Op == OP_ADD &&
+          ((Is64BitMode && AddressHeader->Size == 8) ||
+           (!Is64BitMode && AddressHeader->Size == 4))) {
+        auto [OffsetType, OffsetScale, Arg0, Arg1] =
+            MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
 
         Op->OffsetType = OffsetType;
         Op->OffsetScale = OffsetScale;
-        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0); // Addr
+        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0);   // Addr
         IREmit->ReplaceNodeArgument(CodeNode, Op->Offset_Index, Arg1); // Offset
 
         Changed = true;
@@ -542,7 +578,9 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
       auto Op = IROp->CW<IR::IROp_StoreMem>();
       auto AddressHeader = IREmit->GetOpHeader(Op->Addr);
 
-      if (AddressHeader->Op == OP_ADD && AddressHeader->Size == 8) {
+      if (AddressHeader->Op == OP_ADD &&
+          ((Is64BitMode && AddressHeader->Size == 8) ||
+           (!Is64BitMode && AddressHeader->Size == 4))) {
         auto [OffsetType, OffsetScale, Arg0, Arg1] = MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
 
         Op->OffsetType = OffsetType;
@@ -1295,8 +1333,9 @@ bool ConstProp::Run(IREmitter *IREmit) {
   return Changed;
 }
 
-fextl::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9) {
-  return fextl::make_unique<ConstProp>(InlineConstants, SupportsTSOImm9);
+fextl::unique_ptr<FEXCore::IR::Pass>
+CreateConstProp(bool InlineConstants, bool SupportsTSOImm9, bool Is64BitMode) {
+  return fextl::make_unique<ConstProp>(InlineConstants, SupportsTSOImm9,
+                                       Is64BitMode);
 }
-
 }

unittests/32Bit_ASM/subaddr.asm

@@ -0,0 +1,20 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0xdeadbeef"
+  },
+  "MemoryRegions": {
+    "0x10000000": "4096"
+  },
+  "MemoryData": {
+    "0x10000000": "0xdeadbeef"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+section .text
+
+lea eax, [0x10000040]
+mov eax, [eax-0x40]
+hlt