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Merge pull request #3512 from Sonicadvance1/panic_spilling_block
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InstcountCI: Adds a block that is causing panic spilling
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@alyssarosenzweig
alyssarosenzweig authored Mar 25, 2024
2 parents a8b59c1 + c025039 commit 150af80
Showing 1 changed file with 330 additions and 0 deletions.
330 changes: 330 additions & 0 deletions unittests/InstructionCountCI/FEXOpt/MultiInst.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1028,6 +1028,336 @@
"sub x11, x11, x5, lsl #3",
"mov w5, #0x0"
]
},
"Sekiro spill block": {
"ExpectedInstructionCount": 200,
"Comment": [
"This block of code came from the settings screen when it loaded",
"It was originally at RIP: 0x14232cca0 and has been deobfuscated"
],
"x86Insts": [
"mov QWORD [rsp+0x8],rcx",
"push rbx",
"push rbp",
"push rsi",
"push rdi",
"push r12",
"push r13",
"push r14",
"push r15",
"sub rsp,0x18",
"mov ecx,dword [rdx+0x24]",
"mov esi,dword [rdx]",
"mov ebp,dword [rdx+0x4]",
"mov r14d,dword [rdx+0x8]",
"mov r15d,dword [rdx+0xc]",
"mov r12d,dword [rdx+0x10]",
"mov r13d,dword [rdx+0x14]",
"mov r11d,dword [rdx+0x18]",
"mov ebx,dword [rdx+0x1c]",
"mov edi,dword [rdx+0x20]",
"imul eax,ecx,0x13",
"mov dword [rsp+0x68],ecx",
"add eax,0x1000000",
"shr eax,0x19",
"add eax,esi",
"sar eax,0x1a",
"add eax,ebp",
"sar eax,0x19",
"add eax,r14d",
"sar eax,0x1a",
"add eax,r15d",
"sar eax,0x19",
"add eax,r12d",
"sar eax,0x1a",
"add eax,r13d",
"sar eax,0x19",
"add eax,r11d",
"sar eax,0x1a",
"add eax,ebx",
"sar eax,0x19",
"add eax,edi",
"sar eax,0x1a",
"add eax,ecx",
"sar eax,0x19",
"imul eax,eax,0x13",
"add esi,eax",
"mov eax,esi",
"sar eax,0x1a",
"add ebp,eax",
"shl eax,0x1a",
"sub esi,eax",
"mov ecx,ebp",
"mov rax,qword [rsp+0x60]",
"sar ecx,0x19",
"add r14d,ecx",
"shl ecx,0x19",
"mov edx,r14d",
"sub ebp,ecx",
"sar edx,0x1a",
"add r15d,edx",
"mov dword [rax],esi",
"mov r8d,r15d",
"shl edx,0x1a",
"sar r8d,0x19",
"sub r14d,edx",
"add r12d,r8d",
"mov dword [rax+0x4],ebp",
"mov r9d,r12d",
"shl r8d,0x19",
"sar r9d,0x1a",
"sub r15d,r8d",
"add r13d,r9d",
"mov dword [rax+0x8],r14d",
"shl r9d,0x1a",
"mov r10d,r13d",
"sar r10d,0x19",
"sub r12d,r9d",
"add r11d,r10d",
"mov dword [rax+0xc],r15d",
"mov dword [rsp+0x70],r11d",
"mov rsi,rax",
"sar r11d,0x1a",
"add ebx,r11d",
"mov dword [rax+0x10],r12d",
"mov dword [rsp+0x78],ebx",
"sar ebx,0x19",
"add edi,ebx",
"mov dword [rsp],edi",
"sar edi,0x1a",
"add dword [rsp+0x68],edi",
"shl r10d,0x19",
"mov ecx,dword [rsp+0x68]",
"sub r13d,r10d",
"mov dword [rax+0x14],r13d",
"mov eax,dword [rsp+0x70]",
"shl r11d,0x1a",
"sub eax,r11d",
"shl ebx,0x19",
"mov dword [rsi+0x18],eax",
"mov eax,dword [rsp+0x78]",
"sub eax,ebx",
"shl edi,0x1a",
"mov dword [rsi+0x1c],eax",
"mov eax,dword [rsp]",
"sub eax,edi",
"mov dword [rsi+0x20],eax",
"mov eax,ecx",
"and eax,0xfe000000",
"sub ecx,eax",
"mov dword [rsi+0x24],ecx",
"add rsp,0x18",
"pop r15",
"pop r14",
"pop r13",
"pop r12",
"pop rdi",
"pop rsi",
"pop rbp",
"pop rbx"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x1e0 (480)",
"str x5, [x8, #8]",
"mov x20, x8",
"str x7, [x20, #-8]!",
"str x9, [x20, #-8]!",
"str x10, [x20, #-8]!",
"str x11, [x20, #-8]!",
"str x16, [x20, #-8]!",
"str x17, [x20, #-8]!",
"str x19, [x20, #-8]!",
"str x29, [x20, #-8]!",
"sub x20, x20, #0x18 (24)",
"str x20, [sp, #160]",
"ldr w20, [x6, #36]",
"str w20, [sp, #128]",
"ldr w20, [x6]",
"ldr w21, [x6, #4]",
"ldr w22, [x6, #8]",
"ldr w23, [x6, #12]",
"ldr w24, [x6, #16]",
"str w24, [sp]",
"ldr w24, [x6, #20]",
"str w24, [sp, #32]",
"ldr w24, [x6, #24]",
"str w24, [sp, #64]",
"ldr w24, [x6, #28]",
"str w24, [sp, #96]",
"ldr w24, [x6, #32]",
"str w24, [sp, #192]",
"mov w24, #0x13",
"ldr w25, [sp, #128]",
"mul w24, w25, w24",
"ldr x30, [sp, #160]",
"str w25, [x30, #104]",
"str x30, [sp, #224]",
"mov w30, #0x1000000",
"add w24, w24, w30",
"mov w24, w24",
"lsr w24, w24, #25",
"add w24, w24, w20",
"mov w24, w24",
"asr w24, w24, #26",
"add w24, w24, w21",
"mov w24, w24",
"asr w24, w24, #25",
"add w24, w24, w22",
"mov w24, w24",
"asr w24, w24, #26",
"add w24, w24, w23",
"mov w24, w24",
"asr w24, w24, #25",
"ldr w30, [sp]",
"add w24, w24, w30",
"str w30, [sp, #256]",
"mov w24, w24",
"asr w24, w24, #26",
"ldr w30, [sp, #32]",
"add w24, w24, w30",
"str w30, [sp, #288]",
"mov w24, w24",
"asr w24, w24, #25",
"ldr w30, [sp, #64]",
"add w24, w24, w30",
"str w30, [sp, #320]",
"mov w24, w24",
"asr w24, w24, #26",
"ldr w30, [sp, #96]",
"add w24, w24, w30",
"str w30, [sp, #352]",
"mov w24, w24",
"asr w24, w24, #25",
"ldr w30, [sp, #192]",
"add w24, w24, w30",
"str w30, [sp, #384]",
"mov w24, w24",
"asr w24, w24, #26",
"add w24, w24, w25",
"mov w24, w24",
"asr w24, w24, #25",
"mov w25, #0x13",
"mul w24, w24, w25",
"add w20, w20, w24",
"mov w24, w20",
"asr w24, w24, #26",
"add w21, w21, w24",
"mov w24, w24",
"lsl w24, w24, #26",
"sub w20, w20, w24",
"mov w24, w21",
"ldr x25, [sp, #224]",
"ldr x30, [x25, #96]",
"str x25, [sp, #416]",
"asr w24, w24, #25",
"add w22, w22, w24",
"mov w24, w24",
"lsl w24, w24, #25",
"mov w25, w22",
"sub w21, w21, w24",
"asr w24, w25, #26",
"add w23, w23, w24",
"mov w20, w20",
"str w20, [x30]",
"mov w20, w23",
"mov w24, w24",
"lsl w6, w24, #26",
"asr w20, w20, #25",
"sub w22, w22, w6",
"ldr w24, [sp, #256]",
"add w24, w24, w20",
"mov w21, w21",
"str w21, [x30, #4]",
"mov w21, w24",
"mov w20, w20",
"lsl w12, w20, #25",
"asr w20, w21, #26",
"sub w21, w23, w12",
"ldr w23, [sp, #288]",
"add w23, w23, w20",
"mov w22, w22",
"str w22, [x30, #8]",
"mov w20, w20",
"lsl w13, w20, #26",
"mov w20, w23",
"asr w20, w20, #25",
"sub w22, w24, w13",
"ldr w24, [sp, #320]",
"add w24, w24, w20",
"mov w21, w21",
"str w21, [x30, #12]",
"mov w21, w24",
"ldr x25, [sp, #416]",
"str w21, [x25, #112]",
"mov w21, w24",
"asr w21, w21, #26",
"ldr w24, [sp, #352]",
"add w24, w24, w21",
"mov w22, w22",
"str w22, [x30, #16]",
"mov w22, w24",
"str w22, [x25, #120]",
"mov w22, w24",
"asr w22, w22, #25",
"ldr w24, [sp, #384]",
"add w24, w24, w22",
"str w22, [sp, #448]",
"mov w22, w24",
"str w22, [x25]",
"mov w22, w24",
"asr w22, w22, #26",
"ldr w24, [x25, #104]",
"add w24, w24, w22",
"str w24, [x25, #104]",
"mov w20, w20",
"lsl w14, w20, #25",
"ldr w20, [x25, #104]",
"sub w23, w23, w14",
"mov w23, w23",
"str w23, [x30, #20]",
"ldr w23, [x25, #112]",
"mov w21, w21",
"lsl w15, w21, #26",
"sub w21, w23, w15",
"ldr w23, [sp, #448]",
"mov w23, w23",
"lsl w23, w23, #25",
"mov w21, w21",
"str w21, [x30, #24]",
"ldr w21, [x25, #120]",
"sub w21, w21, w23",
"mov w22, w22",
"lsl w22, w22, #26",
"mov w21, w21",
"str w21, [x30, #28]",
"ldr w21, [x25]",
"sub w21, w21, w22",
"mov w21, w21",
"str w21, [x30, #32]",
"and w4, w20, #0xfe000000",
"sub w5, w20, w4",
"mov w20, w5",
"str w20, [x30, #36]",
"mvn w27, w25",
"adds x26, x25, #0x18 (24)",
"ldr x29, [x26]",
"add x20, x26, #0x8 (8)",
"ldr x19, [x26, #8]",
"add x21, x20, #0x8 (8)",
"ldr x17, [x20, #8]",
"add x20, x21, #0x8 (8)",
"ldr x16, [x21, #8]",
"add x21, x20, #0x8 (8)",
"ldr x11, [x20, #8]",
"add x20, x21, #0x8 (8)",
"ldr x10, [x21, #8]",
"add x21, x20, #0x8 (8)",
"ldr x9, [x20, #8]",
"add x20, x21, #0x8 (8)",
"ldr x7, [x21, #8]",
"add x8, x20, #0x8 (8)",
"add sp, sp, #0x1e0 (480)"
]
}
}
}

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