Merge pull request #2038 from lioncash/vneg

IR: Handle 256-bit VNeg
FEX-Emu · Sep 28, 2022 · 1799d4c · 1799d4c
2 parents 808e1c0 + ce2286c
commit 1799d4c
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Showing 3 changed files with 74 additions and 30 deletions.
diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp
@@ -682,21 +682,24 @@ DEF_OP(VFRSqrt) {
 }
 
 DEF_OP(VNeg) {
-  auto Op = IROp->C<IR::IROp_VNeg>();
+  const auto Op = IROp->C<IR::IROp_VNeg>();
   const uint8_t OpSize = IROp->Size;
 
   void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
-  uint8_t Tmp[16];
+  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE];
 
-  const uint8_t Elements = OpSize / Op->Header.ElementSize;
+  const uint8_t ElementSize = Op->Header.ElementSize;
+  const uint8_t Elements = OpSize / ElementSize;
 
   const auto Func = [](auto a) { return -a; };
   switch (Op->Header.ElementSize) {
     DO_VECTOR_1SRC_OP(1, int8_t, Func)
     DO_VECTOR_1SRC_OP(2, int16_t, Func)
     DO_VECTOR_1SRC_OP(4, int32_t, Func)
     DO_VECTOR_1SRC_OP(8, int64_t, Func)
-    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
+      break;
   }
   memcpy(GDP, Tmp, OpSize);
 }

diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
@@ -1702,21 +1702,54 @@ DEF_OP(VFRSqrt) {
 }
 
 DEF_OP(VNeg) {
-  auto Op = IROp->C<IR::IROp_VNeg>();
-  switch (Op->Header.ElementSize) {
-  case 1:
-    neg(GetDst(Node).V16B(), GetSrc(Op->Vector.ID()).V16B());
-    break;
-  case 2:
-    neg(GetDst(Node).V8H(), GetSrc(Op->Vector.ID()).V8H());
-    break;
-  case 4:
-    neg(GetDst(Node).V4S(), GetSrc(Op->Vector.ID()).V4S());
-    break;
-  case 8:
-    neg(GetDst(Node).V2D(), GetSrc(Op->Vector.ID()).V2D());
-    break;
-  default: LOGMAN_MSG_A_FMT("Unsupported VNeg size: {}", IROp->Size);
+  const auto Op = IROp->C<IR::IROp_VNeg>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = Op->Header.ElementSize;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetDst(Node);
+  const auto Vector = GetSrc(Op->Vector.ID());
+
+  if (HostSupportsSVE) {
+    const auto Pred = Is256Bit ? PRED_TMP_32B.Merging()
+                               : PRED_TMP_16B.Merging();
+
+    switch (ElementSize) {
+      case 1:
+        neg(Dst.Z().VnB(), Pred, Vector.Z().VnB());
+        break;
+      case 2:
+        neg(Dst.Z().VnH(), Pred, Vector.Z().VnH());
+        break;
+      case 4:
+        neg(Dst.Z().VnS(), Pred, Vector.Z().VnS());
+        break;
+      case 8:
+        neg(Dst.Z().VnD(), Pred, Vector.Z().VnD());
+        break;
+      default:
+        LOGMAN_MSG_A_FMT("Unsupported VNeg size: {}", ElementSize);
+        break;
+    }
+  } else {
+    switch (ElementSize) {
+    case 1:
+      neg(Dst.V16B(), Vector.V16B());
+      break;
+    case 2:
+      neg(Dst.V8H(), Vector.V8H());
+      break;
+    case 4:
+      neg(Dst.V4S(), Vector.V4S());
+      break;
+    case 8:
+      neg(Dst.V2D(), Vector.V2D());
+      break;
+    default:
+      LOGMAN_MSG_A_FMT("Unsupported VNeg size: {}", ElementSize);
+      break;
+    }
   }
 }
 

diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
@@ -1016,26 +1016,34 @@ DEF_OP(VFRSqrt) {
 }
 
 DEF_OP(VNeg) {
-  auto Op = IROp->C<IR::IROp_VNeg>();
+  const auto Op = IROp->C<IR::IROp_VNeg>();
+
+  const auto ElementSize = Op->Header.ElementSize;
+
+  const auto Dst = ToYMM(GetDst(Node));
+  const auto Vector = ToYMM(GetSrc(Op->Vector.ID()));
+
   vpxor(xmm15, xmm15, xmm15);
-  switch (Op->Header.ElementSize) {
+  switch (ElementSize) {
     case 1: {
-      vpsubb(GetDst(Node), xmm15, GetSrc(Op->Vector.ID()));
-    break;
+      vpsubb(Dst, ymm15, Vector);
+      break;
     }
     case 2: {
-      vpsubw(GetDst(Node), xmm15, GetSrc(Op->Vector.ID()));
-    break;
+      vpsubw(Dst, ymm15, Vector);
+      break;
     }
     case 4: {
-      vpsubd(GetDst(Node), xmm15, GetSrc(Op->Vector.ID()));
-    break;
+      vpsubd(Dst, ymm15, Vector);
+      break;
     }
     case 8: {
-      vpsubq(GetDst(Node), xmm15, GetSrc(Op->Vector.ID()));
-    break;
+      vpsubq(Dst, ymm15, Vector);
+      break;
     }
-    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
+      break;
   }
 }