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Merge pull request #3357 from Sonicadvance1/remove_non_sra
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FEXCore: Removes SRA option, it's now permanently enabled
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@alyssarosenzweig
alyssarosenzweig authored Jan 3, 2024
2 parents 9841983 + d098545 commit 5467c3e
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Showing 20 changed files with 70 additions and 311 deletions.
7 changes: 0 additions & 7 deletions FEXCore/Source/Interface/Config/Config.json.in
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Expand Up @@ -260,13 +260,6 @@
"Disables optimizations passes for debugging."
]
},
"SRA": {
"Type": "bool",
"Default": "true",
"Desc": [
"Set to false to disable Static Register Allocation"
]
},
"GlobalJITNaming": {
"Type": "bool",
"Default": "false",
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2 changes: 0 additions & 2 deletions FEXCore/Source/Interface/Context/Context.h
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Expand Up @@ -210,7 +210,6 @@ namespace FEXCore::Context {
FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
FEX_CONFIG_OPT(ThunkHostLibsPath32, THUNKHOSTLIBS32);
FEX_CONFIG_OPT(ThunkConfigFile, THUNKCONFIG);
FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
FEX_CONFIG_OPT(GlobalJITNaming, GLOBALJITNAMING);
FEX_CONFIG_OPT(LibraryJITNaming, LIBRARYJITNAMING);
FEX_CONFIG_OPT(BlockJITNaming, BLOCKJITNAMING);
Expand Down Expand Up @@ -391,7 +390,6 @@ namespace FEXCore::Context {
std::shared_mutex CustomIRMutex;
std::atomic<bool> HasCustomIRHandlers{};
fextl::unordered_map<uint64_t, std::tuple<CustomIREntrypointHandler, void *, void *>> CustomIRHandlers;
FEXCore::CPU::DispatcherConfig DispatcherConfig;
};

uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args);
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8 changes: 0 additions & 8 deletions FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
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Expand Up @@ -611,10 +611,6 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
mrs(TmpReg, ARMEmitter::SystemRegister::NZCV);
str(TmpReg.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));

if (!StaticRegisterAllocation()) {
return;
}

// PF/AF are special, remove them from the mask
uint32_t PFAFMask = ((1u << REG_PF.Idx()) | ((1u << REG_AF.Idx())));
unsigned PFAFSpillMask = GPRSpillMask & PFAFMask;
Expand Down Expand Up @@ -728,10 +724,6 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
ldr(TmpReg.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
msr(ARMEmitter::SystemRegister::NZCV, TmpReg);

if (!StaticRegisterAllocation()) {
return;
}

if (FPRs) {
// Set up predicate registers.
// We don't bother spilling these in SpillStaticRegs,
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1 change: 0 additions & 1 deletion FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
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Expand Up @@ -238,7 +238,6 @@ class Arm64Emitter : public FEXCore::ARMEmitter::Emitter {

FEX_CONFIG_OPT(Disassemble, DISASSEMBLE);
#endif
FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
};

}
10 changes: 3 additions & 7 deletions FEXCore/Source/Interface/Core/Core.cpp
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Expand Up @@ -268,12 +268,10 @@ namespace FEXCore::Context {
return false;
}

DispatcherConfig.StaticRegisterAllocation = Config.StaticRegisterAllocation && BackendFeatures.SupportsStaticRegisterAllocation;
Dispatcher = FEXCore::CPU::Dispatcher::Create(this, DispatcherConfig);
Dispatcher = FEXCore::CPU::Dispatcher::Create(this);

// Set up the SignalDelegator config since core is initialized.
FEXCore::SignalDelegator::SignalDelegatorConfig SignalConfig {
.StaticRegisterAllocation = DispatcherConfig.StaticRegisterAllocation,
.SupportsAVX = HostFeatures.SupportsAVX,

.DispatcherBegin = Dispatcher->Start,
Expand Down Expand Up @@ -375,17 +373,15 @@ namespace FEXCore::Context {

Thread->CTX = this;

bool DoSRA = DispatcherConfig.StaticRegisterAllocation;

Thread->PassManager->AddDefaultPasses(this, Config.Core == FEXCore::Config::CONFIG_IRJIT, DoSRA);
Thread->PassManager->AddDefaultPasses(this, Config.Core == FEXCore::Config::CONFIG_IRJIT);
Thread->PassManager->AddDefaultValidationPasses();

Thread->PassManager->RegisterSyscallHandler(SyscallHandler);

// Create CPU backend
switch (Config.Core) {
case FEXCore::Config::CONFIG_IRJIT:
Thread->PassManager->InsertRegisterAllocationPass(DoSRA, HostFeatures.SupportsAVX);
Thread->PassManager->InsertRegisterAllocationPass(HostFeatures.SupportsAVX);
Thread->CPUBackend = FEXCore::CPU::CreateArm64JITCore(this, Thread);
break;
case FEXCore::Config::CONFIG_CUSTOM:
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43 changes: 15 additions & 28 deletions FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
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Expand Up @@ -31,10 +31,9 @@ static void SleepThread(FEXCore::Context::ContextImpl *CTX, FEXCore::Core::CpuSt

constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 2;

Dispatcher::Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config)
Dispatcher::Dispatcher(FEXCore::Context::ContextImpl *ctx)
: Arm64Emitter(ctx, FEXCore::Allocator::VirtualAlloc(MAX_DISPATCHER_CODE_SIZE, true), MAX_DISPATCHER_CODE_SIZE)
, CTX {ctx}
, config {config} {
, CTX {ctx} {
EmitDispatcher();
}

Expand Down Expand Up @@ -79,9 +78,7 @@ void Dispatcher::EmitDispatcher() {

AbsoluteLoopTopAddressFillSRA = GetCursorAddress<uint64_t>();

if (config.StaticRegisterAllocation) {
FillStaticRegs();
}
FillStaticRegs();

// We want to ensure that we are 16 byte aligned at the top of this loop
Align16B();
Expand Down Expand Up @@ -172,8 +169,7 @@ void Dispatcher::EmitDispatcher() {

{
ThreadStopHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
if (config.StaticRegisterAllocation)
SpillStaticRegs(TMP1);
SpillStaticRegs(TMP1);

ThreadStopHandlerAddress = GetCursorAddress<uint64_t>();

Expand All @@ -186,8 +182,7 @@ void Dispatcher::EmitDispatcher() {

{
ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
if (config.StaticRegisterAllocation)
SpillStaticRegs(TMP1);
SpillStaticRegs(TMP1);

ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
Expand All @@ -204,8 +199,7 @@ void Dispatcher::EmitDispatcher() {
blr(ARMEmitter::Reg::r2);
}

if (config.StaticRegisterAllocation)
FillStaticRegs();
FillStaticRegs();

ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x1, ARMEmitter::XReg::x1, 1);
Expand All @@ -222,8 +216,7 @@ void Dispatcher::EmitDispatcher() {
{
Bind(&NoBlock);

if (config.StaticRegisterAllocation)
SpillStaticRegs(TMP1);
SpillStaticRegs(TMP1);

ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
Expand All @@ -242,8 +235,7 @@ void Dispatcher::EmitDispatcher() {
blr(ARMEmitter::Reg::r4); // { CTX, Frame, RIP, MaxInst }
}

if (config.StaticRegisterAllocation)
FillStaticRegs();
FillStaticRegs();

ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
Expand Down Expand Up @@ -277,8 +269,7 @@ void Dispatcher::EmitDispatcher() {
// Needs to be distinct from the SignalHandlerReturnAddress
GuestSignal_SIGILL = GetCursorAddress<uint64_t>();

if (config.StaticRegisterAllocation)
SpillStaticRegs(TMP1);
SpillStaticRegs(TMP1);

hlt(0);
}
Expand All @@ -288,8 +279,7 @@ void Dispatcher::EmitDispatcher() {
// Needs to be distinct from the SignalHandlerReturnAddress
GuestSignal_SIGTRAP = GetCursorAddress<uint64_t>();

if (config.StaticRegisterAllocation)
SpillStaticRegs(TMP1);
SpillStaticRegs(TMP1);

brk(0);
}
Expand All @@ -299,8 +289,7 @@ void Dispatcher::EmitDispatcher() {
// Needs to be distinct from the SignalHandlerReturnAddress
GuestSignal_SIGSEGV = GetCursorAddress<uint64_t>();

if (config.StaticRegisterAllocation)
SpillStaticRegs(TMP1);
SpillStaticRegs(TMP1);

// hlt/udf = SIGILL
// brk = SIGTRAP
Expand All @@ -320,8 +309,7 @@ void Dispatcher::EmitDispatcher() {

{
ThreadPauseHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
if (config.StaticRegisterAllocation)
SpillStaticRegs(TMP1);
SpillStaticRegs(TMP1);

ThreadPauseHandlerAddress = GetCursorAddress<uint64_t>();
// We are pausing, this means the frontend should be waiting for this thread to idle
Expand Down Expand Up @@ -388,8 +376,7 @@ void Dispatcher::EmitDispatcher() {
str(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, State.rip));

// load static regs
if (config.StaticRegisterAllocation)
FillStaticRegs();
FillStaticRegs();

// Now go back to the regular dispatcher loop
b(&LoopTop);
Expand Down Expand Up @@ -558,8 +545,8 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread)
}
}

fextl::unique_ptr<Dispatcher> Dispatcher::Create(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
return fextl::make_unique<Dispatcher>(CTX, Config);
fextl::unique_ptr<Dispatcher> Dispatcher::Create(FEXCore::Context::ContextImpl *CTX) {
return fextl::make_unique<Dispatcher>(CTX);
}

}
11 changes: 2 additions & 9 deletions FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h
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Expand Up @@ -31,18 +31,14 @@ class ContextImpl;

namespace FEXCore::CPU {

struct DispatcherConfig {
bool StaticRegisterAllocation = false;
};

#define STATE_PTR(STATE_TYPE, FIELD) \
STATE.R(), offsetof(FEXCore::Core::STATE_TYPE, FIELD)

class Dispatcher final : public Arm64Emitter {
public:
static fextl::unique_ptr<Dispatcher> Create(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
static fextl::unique_ptr<Dispatcher> Create(FEXCore::Context::ContextImpl *CTX);

Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &Config);
Dispatcher(FEXCore::Context::ContextImpl *ctx);
~Dispatcher();

/**
Expand Down Expand Up @@ -106,11 +102,8 @@ class Dispatcher final : public Arm64Emitter {
}
}

const DispatcherConfig& GetConfig() const { return config; }

protected:
FEXCore::Context::ContextImpl *CTX;
DispatcherConfig config;

using AsmDispatch = void(*)(FEXCore::Core::CpuStateFrame *Frame);
using JITCallback = void(*)(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP);
Expand Down
10 changes: 0 additions & 10 deletions FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
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Expand Up @@ -594,15 +594,6 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::In
ClearCache();

// Setup dynamic dispatch.
if (CTX->Dispatcher->GetConfig().StaticRegisterAllocation) {
RT_LoadRegister = &Arm64JITCore::Op_LoadRegisterSRA;
RT_StoreRegister = &Arm64JITCore::Op_StoreRegisterSRA;
}
else {
RT_LoadRegister = &Arm64JITCore::Op_LoadRegister;
RT_StoreRegister = &Arm64JITCore::Op_StoreRegister;
}

if (ParanoidTSO()) {
RT_LoadMemTSO = &Arm64JITCore::Op_ParanoidLoadMemTSO;
RT_StoreMemTSO = &Arm64JITCore::Op_ParanoidStoreMemTSO;
Expand Down Expand Up @@ -920,7 +911,6 @@ fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl *

CPUBackendFeatures GetArm64JITBackendFeatures() {
return CPUBackendFeatures {
.SupportsStaticRegisterAllocation = true,
.SupportsFlags = true,
.SupportsSaturatingRoundingShifts = true,
.SupportsVTBL2 = true,
Expand Down
6 changes: 0 additions & 6 deletions FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
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Expand Up @@ -226,19 +226,13 @@ class Arm64JITCore final : public CPUBackend, public Arm64Emitter {
void VFScalarUnaryOperation(uint8_t OpSize, uint8_t ElementSize, bool ZeroUpperBits, ScalarUnaryOpCaller ScalarEmit, ARMEmitter::VRegister Dst, ARMEmitter::VRegister Vector1, std::variant<ARMEmitter::VRegister, ARMEmitter::Register> Vector2);

// Runtime selection;
// Load and store register style.
OpType RT_LoadRegister;
OpType RT_StoreRegister;
// Load and store TSO memory style
OpType RT_LoadMemTSO;
OpType RT_StoreMemTSO;

#define DEF_OP(x) void Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)

// Dynamic Dispatcher supporting operations
DEF_OP(LoadRegisterSRA);
DEF_OP(StoreRegisterSRA);

DEF_OP(ParanoidLoadMemTSO);
DEF_OP(ParanoidStoreMemTSO);

Expand Down
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