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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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alyssarosenzweig committed Mar 1, 2024
1 parent 1188045 commit 5fd91d3
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Showing 3 changed files with 40 additions and 56 deletions.
46 changes: 20 additions & 26 deletions unittests/InstructionCountCI/FlagM/Atomics.json
Original file line number Diff line number Diff line change
Expand Up @@ -1296,17 +1296,15 @@
]
},
"lock dec byte [rax]": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov w21, #0xff",
"ldaddalb w21, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"mov w20, #0xff",
"ldaddalb w20, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv"
"setf8 w26",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV"
]
},
"lock not byte [rax]": {
Expand Down Expand Up @@ -1396,17 +1394,15 @@
]
},
"lock dec word [rax]": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov w21, #0xffff",
"ldaddalh w21, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"mov w20, #0xffff",
"ldaddalh w20, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv"
"setf16 w26",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV"
]
},
"lock dec dword [rax]": {
Expand All @@ -1432,29 +1428,27 @@
]
},
"lock inc byte [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalb w20, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24",
"add w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv"
"setf8 w26",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV"
]
},
"lock inc word [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalh w20, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv"
"setf16 w26",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
]
},
"lock inc dword [rax]": {
Expand Down
10 changes: 4 additions & 6 deletions unittests/InstructionCountCI/FlagM/FlagOpts.json
Original file line number Diff line number Diff line change
Expand Up @@ -143,7 +143,7 @@
]
},
"8-bit DEC consumed": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"x86Insts": [
"sub al, ah",
"dec al"
Expand All @@ -155,13 +155,11 @@
"sub w20, w4, w20",
"cfinv",
"bfxil x4, x20, #0, #8",
"mov w20, #0x1",
"uxtb w27, w4",
"cset w21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"sub w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv",
"setf8 w26",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
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40 changes: 16 additions & 24 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
Original file line number Diff line number Diff line change
Expand Up @@ -2388,44 +2388,38 @@
]
},
"inc al": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP3 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"uxtb w27, w4",
"cset w21, hs",
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24",
"add w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv",
"setf8 w26",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"dec al": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"uxtb w27, w4",
"cset w21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"sub w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv",
"setf8 w26",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"inc ax": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"uxth w27, w4",
"cset w21, hs",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv",
"setf16 w26",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
Expand All @@ -2452,16 +2446,14 @@
]
},
"dec ax": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"uxth w27, w4",
"cset w21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x1 (1)",
"rmif x21, #63, #nzCv",
"setf16 w26",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
Expand Down

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