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instcountci: update
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@bylaws
bylaws committed Jan 21, 2024
1 parent 576cf61 commit c4c10d0
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Showing 2 changed files with 202 additions and 196 deletions.
188 changes: 96 additions & 92 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1230,23 +1230,23 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov w21, w4",
"lsl w22, w21, #2",
"orr w22, w22, w21, lsr #31",
"rmif x21, #29, #nzCv",
"orr w4, w22, w20, lsl #1"
"mov w20, w4",
"lsl w21, w20, #2",
"cset w22, hs",
"orr w21, w21, w20, lsr #31",
"rmif x20, #29, #nzCv",
"orr w4, w21, w22, lsl #1"
]
},
"rcl rax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"cset w20, hs",
"lsl x21, x4, #2",
"orr x21, x21, x4, lsr #63",
"lsl x20, x4, #2",
"cset w21, hs",
"orr x20, x20, x4, lsr #63",
"rmif x4, #61, #nzCv",
"orr x4, x21, x20, lsl #1"
"orr x4, x20, x21, lsl #1"
]
},
"rcr ax, 2": {
Expand Down Expand Up @@ -1278,23 +1278,23 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov w21, w4",
"lsr w22, w21, #2",
"orr w22, w22, w21, lsl #31",
"rmif x21, #0, #nzCv",
"orr w4, w22, w20, lsl #30"
"mov w20, w4",
"lsr w21, w20, #2",
"cset w22, hs",
"orr w21, w21, w20, lsl #31",
"rmif x20, #0, #nzCv",
"orr w4, w21, w22, lsl #30"
]
},
"rcr rax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"lsr x21, x4, #2",
"orr x21, x21, x4, lsl #63",
"lsr x20, x4, #2",
"cset w21, hs",
"orr x20, x20, x4, lsl #63",
"rmif x4, #0, #nzCv",
"orr x4, x21, x20, lsl #62"
"orr x4, x20, x21, lsl #62"
]
},
"shl ax, 2": {
Expand Down Expand Up @@ -2057,59 +2057,61 @@
]
},
"rcl eax, cl": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"mov w20, w5",
"cset w21, hs",
"cbz x20, #+0x54",
"mov w22, w4",
"lsl w23, w22, w20",
"mov w21, w4",
"lsl w22, w21, w20",
"cset w23, hs",
"and w20, w20, #0x1f",
"cbz x20, #+0x4c",
"mov w24, #0x21",
"sub w24, w24, w20",
"lsr w24, w22, w24",
"lsr w24, w21, w24",
"mov w25, #0x0",
"mrs x30, nzcv",
"cmp w20, #0x1 (1)",
"csel w24, w24, w25, hi",
"orr w23, w23, w24",
"orr w22, w22, w24",
"mov w24, #0x20",
"sub w24, w24, w20",
"lsr w22, w22, w24",
"lsr w21, w21, w24",
"msr nzcv, x30",
"rmif x22, #63, #nzCv",
"rmif x21, #63, #nzCv",
"sub w20, w20, #0x1 (1)",
"lsl x20, x21, x20",
"orr w4, w23, w20",
"eor w20, w4, w22, lsl #31",
"lsl x20, x23, x20",
"orr w4, w22, w20",
"eor w20, w4, w21, lsl #31",
"rmif x20, #31, #nzcV"
]
},
"rcl rax, cl": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 23,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"mov x20, x5",
"cset w21, hs",
"cbz x20, #+0x50",
"lsl x22, x4, x20",
"mov w23, #0x41",
"sub x23, x23, x20",
"lsr x23, x4, x23",
"mov w24, #0x0",
"mrs x25, nzcv",
"cmp x20, #0x1 (1)",
"csel x23, x23, x24, hi",
"orr x22, x22, x23",
"mov w23, #0x40",
"sub x23, x23, x20",
"lsr x23, x4, x23",
"msr nzcv, x25",
"rmif x23, #63, #nzCv",
"sub x20, x20, #0x1 (1)",
"lsl x20, x21, x20",
"orr x4, x22, x20",
"eor x20, x4, x23, lsl #63",
"mov x20, x4",
"lsl x21, x20, x5",
"cset w22, hs",
"and x23, x5, #0x3f",
"cbz x23, #+0x4c",
"mov w24, #0x41",
"sub x24, x24, x23",
"lsr x24, x20, x24",
"mov w25, #0x0",
"mrs x30, nzcv",
"cmp x23, #0x1 (1)",
"csel x24, x24, x25, hi",
"orr x21, x21, x24",
"mov w24, #0x40",
"sub x24, x24, x23",
"lsr x20, x20, x24",
"msr nzcv, x30",
"rmif x20, #63, #nzCv",
"sub x23, x23, #0x1 (1)",
"lsl x22, x22, x23",
"orr x4, x21, x22",
"eor x20, x4, x20, lsl #63",
"rmif x20, #63, #nzcV"
]
},
Expand Down Expand Up @@ -2141,58 +2143,60 @@
]
},
"rcr eax, cl": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov w21, w5",
"cbz x21, #+0x54",
"mov w22, w4",
"lsr w23, w22, w21",
"mov w20, w5",
"mov w21, w4",
"lsr w22, w21, w20",
"cset w23, hs",
"and w20, w20, #0x1f",
"cbz x20, #+0x4c",
"mov w24, #0x0",
"mov w25, #0x21",
"sub w25, w25, w21",
"lsl w25, w22, w25",
"sub w25, w25, w20",
"lsl w25, w21, w25",
"mrs x30, nzcv",
"cmp w21, #0x1 (1)",
"cmp w20, #0x1 (1)",
"csel w24, w25, w24, hi",
"orr w23, w23, w24",
"sub w24, w21, #0x1 (1)",
"lsr w22, w22, w24",
"orr w22, w22, w24",
"sub w24, w20, #0x1 (1)",
"lsr w21, w21, w24",
"msr nzcv, x30",
"rmif x22, #63, #nzCv",
"mov w22, #0x20",
"sub w21, w22, w21",
"lsl x20, x20, x21",
"orr w4, w23, w20",
"rmif x21, #63, #nzCv",
"mov w21, #0x20",
"sub w20, w21, w20",
"lsl x20, x23, x20",
"orr w4, w22, w20",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
]
},
"rcr rax, cl": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 23,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x21, x5",
"cbz x21, #+0x50",
"lsr x22, x4, x21",
"mov w23, #0x0",
"mov w24, #0x41",
"sub x24, x24, x21",
"lsl x24, x4, x24",
"mrs x25, nzcv",
"cmp x21, #0x1 (1)",
"csel x23, x24, x23, hi",
"orr x22, x22, x23",
"sub x23, x21, #0x1 (1)",
"lsr x23, x4, x23",
"msr nzcv, x25",
"rmif x23, #63, #nzCv",
"mov w23, #0x40",
"sub x21, x23, x21",
"lsl x20, x20, x21",
"orr x4, x22, x20",
"mov x20, x4",
"lsr x21, x20, x5",
"cset w22, hs",
"and x23, x5, #0x3f",
"cbz x23, #+0x4c",
"mov w24, #0x0",
"mov w25, #0x41",
"sub x25, x25, x23",
"lsl x25, x20, x25",
"mrs x30, nzcv",
"cmp x23, #0x1 (1)",
"csel x24, x25, x24, hi",
"orr x21, x21, x24",
"sub x24, x23, #0x1 (1)",
"lsr x20, x20, x24",
"msr nzcv, x30",
"rmif x20, #63, #nzCv",
"mov w20, #0x40",
"sub x20, x20, x23",
"lsl x20, x22, x20",
"orr x4, x21, x20",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV"
]
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