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Optimize large sign-extended constants #3655

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merged 3 commits into from
May 23, 2024
Merged

Optimize large sign-extended constants #3655

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8340012
InstCountCI: add wacky imul
alyssarosenzweig May 23, 2024
b33788e
Arm64Emitter: handle another class of constants
alyssarosenzweig May 23, 2024
79c609d
InstCountCI: Update
alyssarosenzweig May 23, 2024
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11 changes: 11 additions & 0 deletions FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -454,6 +454,17 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
}
}

// If we can't handle negatives with the orr, try with movn+movk
if (Is64Bit && ((~Constant) >> 32) == 0) {
movn(s, Reg, (~Constant) & 0xFFFF);
movk(s, Reg, (Constant >> 16) & 0xFFFF, 16);
if (NOPPad) {
nop();
nop();
}
return;
}

// ADRP+ADD is specifically optimized in hardware
// Check if we can use this
auto PC = GetCursorAddress<uint64_t>();
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13 changes: 13 additions & 0 deletions unittests/InstructionCountCI/FlagM/Secondary.json
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Expand Up @@ -1008,6 +1008,19 @@
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rsi, rax, 0xffffffff8646c299": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffc299",
"movk x20, #0x8646, lsl #16",
"smulh x21, x4, x20",
"mul x10, x4, x20",
"asr x20, x10, #63",
"cmp x21, x20",
"ccmn xzr, #0, #nzCV, eq"
]
},
"cmpxchg cl, bl": {
"ExpectedInstructionCount": 11,
"ExpectedArm64ASM": [
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