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wip doc, still not working for SPIKE32
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Axel Heider committed Mar 1, 2023
1 parent fe772d7 commit 3401808
Showing 1 changed file with 58 additions and 72 deletions.
130 changes: 58 additions & 72 deletions src/arch/riscv/traps.S
Original file line number Diff line number Diff line change
Expand Up @@ -26,92 +26,78 @@
trap_entry:

#ifdef ENABLE_SMP_SUPPORT
/* The sscratch contains the stack for the current core */
csrrw sp, sscratch, sp
/* Now we have a valid kernel stack */
STORE t0, (-2*REGBYTES)(sp)
LOAD t0, (-1*REGBYTES)(sp)
/* We need two things now:
* - the stack pointer for the kernel, which is in SSCRATCH
* - a pointer to a space where to store the thread context
*/
csrrw sp, sscratch, sp /* swap sp and sscratch to get a kernel stack */
STORE tp, (-2*REGBYTES)(sp) /* sp[-2] = tp/x4 */
LOAD tp, (-1*REGBYTES)(sp) /* tp = sp[-1] */
STORE ra, (0*REGBYTES)(tp) /* t0[0] = ra/x1 */
csrrw ra, sscratch, sp /* sscratch -> ra, sp -> scratch */
STORE ra, (1*REGBYTES)(tp) /* tp[1] = user sp */
LOAD ra, (-2*REGBYTES)(sp) /* get user tp from sscratch */
#else
csrrw t0, sscratch, t0
#endif
STORE ra, (0*REGBYTES)(t0)
#ifndef ENABLE_SMP_SUPPORT
STORE sp, (1*REGBYTES)(t0)
#endif
STORE gp, (2*REGBYTES)(t0)
STORE tp, (3*REGBYTES)(t0)
STORE t1, (5*REGBYTES)(t0)
STORE t2, (6*REGBYTES)(t0)
STORE s0, (7*REGBYTES)(t0)
STORE s1, (8*REGBYTES)(t0)
STORE a0, (9*REGBYTES)(t0)
STORE a1, (10*REGBYTES)(t0)
STORE a2, (11*REGBYTES)(t0)
STORE a3, (12*REGBYTES)(t0)
STORE a4, (13*REGBYTES)(t0)
STORE a5, (14*REGBYTES)(t0)
STORE a6, (15*REGBYTES)(t0)
STORE a7, (16*REGBYTES)(t0)
STORE s2, (17*REGBYTES)(t0)
STORE s3, (18*REGBYTES)(t0)
STORE s4, (19*REGBYTES)(t0)
STORE s5, (20*REGBYTES)(t0)
STORE s6, (21*REGBYTES)(t0)
STORE s7, (22*REGBYTES)(t0)
STORE s8, (23*REGBYTES)(t0)
STORE s9, (24*REGBYTES)(t0)
STORE s10, (25*REGBYTES)(t0)
STORE s11, (26*REGBYTES)(t0)
STORE t3, (27*REGBYTES)(t0)
STORE t4, (28*REGBYTES)(t0)
STORE t5, (29*REGBYTES)(t0)
STORE t6, (30*REGBYTES)(t0)
/* save t0 value */
#ifdef ENABLE_SMP_SUPPORT
LOAD x1, (-2*REGBYTES)(sp)
#else
csrr x1, sscratch
csrrw tp, sscratch, tp /* swap tp/x4 and sscratch */
STORE ra, (0*REGBYTES)(tp) /* tp[0] = ra/x1 */
STORE sp, (1*REGBYTES)(tp) /* tp[1] = sp/x2 */
la sp, (kernel_stack_alloc + BIT(CONFIG_KERNEL_STACK_BITS))
csrr ra, sscratch /* ra/x1 = sscratch (t0/x5 of user thread) */
#endif
STORE x1, (4*REGBYTES)(t0)

csrr x1, sstatus
STORE x1, (32*REGBYTES)(t0)

csrr s0, scause
STORE s0, (31*REGBYTES)(t0)
/* x1/ra and x2/sp have already been saved */
STORE gp, (2*REGBYTES)(tp) /* x3 */
STORE ra, (3*REGBYTES)(tp) /* user tp/x4 is in ra/x1 */
STORE t0, (4*REGBYTES)(tp) /* x5 */
STORE t1, (5*REGBYTES)(tp) /* x6 */
STORE t2, (6*REGBYTES)(tp) /* x7 */
STORE s0, (7*REGBYTES)(tp) /* x8 */
STORE s1, (8*REGBYTES)(tp) /* x9 */
STORE a0, (9*REGBYTES)(tp) /* x10 */
STORE a1, (10*REGBYTES)(tp) /* x11*/
STORE a2, (11*REGBYTES)(tp) /* x12 */
STORE a3, (12*REGBYTES)(tp) /* x13 */
STORE a4, (13*REGBYTES)(tp) /* x14 */
STORE a5, (14*REGBYTES)(tp) /* x15 */
STORE a6, (15*REGBYTES)(tp) /* x16 */
STORE a7, (16*REGBYTES)(tp) /* x17 */
STORE s2, (17*REGBYTES)(tp) /* x18 */
STORE s3, (18*REGBYTES)(tp) /* x19 */
STORE s4, (19*REGBYTES)(tp) /* x20 */
STORE s5, (20*REGBYTES)(tp) /* x21 */
STORE s6, (21*REGBYTES)(tp) /* x22 */
STORE s7, (22*REGBYTES)(tp) /* x23 */
STORE s8, (23*REGBYTES)(tp) /* x24 */
STORE s9, (24*REGBYTES)(tp) /* x25 */
STORE s10, (25*REGBYTES)(tp) /* x26 */
STORE s11, (26*REGBYTES)(tp) /* x27 */
STORE t3, (27*REGBYTES)(tp) /* x28 */
STORE t4, (28*REGBYTES)(tp) /* x29 */
STORE t5, (29*REGBYTES)(tp) /* x30 */
STORE t6, (30*REGBYTES)(tp) /* x31 */
csrr t0, scause
STORE t0, (31*REGBYTES)(tp)
csrr t1, sstatus
STORE t1, (32*REGBYTES)(tp)
csrr t2, sepc
STORE t2, (33*REGBYTES)(t0)

.option push
.option norelax
la gp, __global_pointer$
.option pop

#ifdef ENABLE_SMP_SUPPORT
/* save the user sp */
csrr x1, sscratch
STORE x1, (1*REGBYTES)(t0)
/* restore the sscratch */
csrw sscratch, sp
#else
/* Load kernel's stack address */
la sp, (kernel_stack_alloc + BIT(CONFIG_KERNEL_STACK_BITS))
#endif

/* Save exception PC */
csrr x1, sepc
STORE x1, (33*REGBYTES)(t0)

/* Check if it's an interrupt */
bltz s0, interrupt
bltz t0, interrupt

/* ratified priv has value 8 for ecall from U-mode exception */
li s4, 8
bne s0, s4, exception
bne t0, s4, exception

handle_syscall:
/* Set the return address to sepc + 4 in the case of a system/environment call */
addi x1, x1, 4
addi s2, s2, 4
/* Save NextIP */
STORE x1, (34*REGBYTES)(t0)
STORE s2, (34*REGBYTES)(t0)

#ifdef CONFIG_FASTPATH
li t3, SYSCALL_CALL
Expand All @@ -133,10 +119,10 @@ handle_syscall:
/* Not an interrupt or a syscall */
exception:
/* Save NextIP */
STORE x1, (34*REGBYTES)(t0)
STORE s2, (34*REGBYTES)(t0)
j c_handle_exception

interrupt:
/* Save NextIP */
STORE x1, (34*REGBYTES)(t0)
STORE s2, (34*REGBYTES)(t0)
j c_handle_interrupt

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