lab 2 project starter from future

Lab2_VHDL/Lab2_VHDL/simulation/modelsim.ini → Lab1_VHDL/simulation/modelsim.ini.sav

@@ -3,6 +3,8 @@ others = $MODEL_TECH/../modelsim.ini
 smartfusion2 = C:/Microsemi/Libero_SoC_v11.7///Designer//lib//modelsim//precompiled/vhdl/smartfusion2
 syncad_vhdl_lib = C:\Microsemi\Libero_SoC_v11.7\Designer/lib/actel/syncad_vhdl_lib
 
+postsynth = postsynth
+IGLOO2 = C:/Microsemi/Libero_SoC_v11.7///Designer//lib//modelsim//precompiled/vhdl/smartfusion2
 [vcom]
 VHDL93 = 1
 

Lab1_VHDL/synthesis/LedBlinkingDSpeed_syn.bak

@@ -0,0 +1,70 @@
+#--  Synopsys, Inc.
+#--  Version J-2015.03M-SP1-2
+#--  Project file C:\Users\ashj\Documents\LEARNING\Microsemi\Lab1_VHDL_VHDL\synthesis\LedBlinkingDSpeed_syn.prj
+
+#project files
+add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/ClkGen.vhd"
+add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/ClkGenNoSwitch.vhd"
+add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/Display.vhd"
+add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/Reset_out.vhd"
+add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/LedBlinkingDSpeed.vhd"
+add_file -fpga_constraint "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc"
+
+
+
+#implementation: "synthesis"
+impl -add synthesis -type fpga
+
+#device options
+set_option -technology IGLOO2
+set_option -part M2GL025
+set_option -package VF256
+set_option -speed_grade STD
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "work.LedBlinkingDSpeed"
+
+# mapper_options
+set_option -frequency 100.000
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -srs_instrumentation 1
+
+# actel_options
+set_option -rw_check_on_ram 0
+
+# Microsemi G4
+set_option -run_prop_extract 1
+set_option -maxfan 10000
+set_option -clock_globalthreshold 2
+set_option -async_globalthreshold 12
+set_option -globalthreshold 5000
+set_option -low_power_ram_decomp 0
+set_option -disable_io_insertion 0
+set_option -opcond COMTC
+set_option -retiming 0
+set_option -report_path 4000
+set_option -update_models_cp 0
+set_option -preserve_registers 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+# Compiler Options
+set_option -vhdl2008 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./LedBlinkingDSpeed.edn"
+impl -active "synthesis"

Lab2_VHDL/Lab2_VHDL/Lab2_VHDL.prjx → Lab2_VHDL/Lab2_VHDL.prjx

@@ -1,6 +1,7 @@
 KEY LIBERO "11.7"
 KEY CAPTURE "11.7.1.14"
-KEY DEFAULT_IMPORT_LOC ""
+KEY DEFAULT_IMPORT_LOC "C:\Actelprj\A3P_Verilog_labs\lab2"
+KEY DEFAULT_OPEN_LOC ""
 KEY ProjectID "0"
 KEY HDLTechnology "VHDL"
 KEY VERILOGMODE "VERILOG2001"
@@ -14,7 +15,9 @@ KEY VendorTechnology_DieVoltage "1.2"
 KEY VendorTechnology_PART_RANGE "COM"
 KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE "100_MS"
 KEY VendorTechnology_IO_DEFT_STD "LVCMOS33"
+KEY VendorTechnology_OPCONR ""
 KEY VendorTechnology_PLL_SUPPLY "PLL_SUPPLY_33"
+KEY VendorTechnology_RAD_EXPOSURE ""
 KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
 KEY VendorTechnology_RESTRICTPROBEPINS "0"
 KEY VendorTechnology_RESTRICTSPIPINS "0"
@@ -28,7 +31,7 @@ KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
 KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
 KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
 KEY VendorTechnology_VOLTR "COM"
-KEY ProjectLocation "C:\Users\ashj\Documents\LEARNING\Microsemi\Lab2_VHDL\Lab2_VHDL"
+KEY ProjectLocation "C:\Users\ashj\Documents\LEARNING\Microsemi\Lab2_VHDL"
 KEY ProjectDescription ""
 KEY Pa4PeripheralNewSeq "GOOD"
 KEY SimulationType "VHDL"
@@ -41,62 +44,130 @@ ENDLIST
 LIST FileManager
 VALUE "<project>\constraint\io\LedBlinkingDSpeed.io.pdc,io_pdc"
 STATE="utd"
-TIME="1489082277"
+TIME="1477216352"
 SIZE="1197"
 ENDFILE
 VALUE "<project>\constraint\LedBlinkingDSpeed_sdc.sdc,sdc"
 STATE="utd"
-TIME="1489082277"
+TIME="1477216352"
 SIZE="152"
 ENDFILE
+VALUE "<project>\designer\impl1\LedBlinkingDSpeed.ide_des,ide_des"
+STATE="utd"
+TIME="1477216382"
+SIZE="438"
+ENDFILE
 VALUE "<project>\hdl\ClkGen.vhd,hdl"
 STATE="utd"
-TIME="1489082275"
+TIME="1477216352"
 SIZE="4624"
 ENDFILE
 VALUE "<project>\hdl\ClkGenNoSwitch.vhd,hdl"
 STATE="utd"
-TIME="1489082275"
+TIME="1477216352"
 SIZE="4722"
 ENDFILE
 VALUE "<project>\hdl\Display.vhd,hdl"
 STATE="utd"
-TIME="1489082275"
+TIME="1477216352"
 SIZE="4734"
 ENDFILE
 VALUE "<project>\hdl\LedBlinkingDSpeed.vhd,hdl"
 STATE="utd"
-TIME="1489082275"
-SIZE="8892"
+TIME="1477216740"
+SIZE="8890"
 ENDFILE
 VALUE "<project>\hdl\Reset_out.vhd,hdl"
 STATE="utd"
-TIME="1489082275"
+TIME="1477216352"
 SIZE="3699"
 ENDFILE
+VALUE "<project>\simulation\run.do,do"
+STATE="utd"
+TIME="1477216662"
+SIZE="727"
+ENDFILE
+VALUE "<project>\stimulus\LedBlinkingDSpeed_tb.vhd,tb_hdl"
+STATE="utd"
+TIME="1477216430"
+SIZE="6181"
+ENDFILE
+VALUE "<project>\synthesis\LedBlinkingDSpeed.edn,syn_edn"
+STATE="utd"
+TIME="1477216774"
+SIZE="182614"
+ENDFILE
+VALUE "<project>\synthesis\LedBlinkingDSpeed.so,so"
+STATE="utd"
+TIME="1477216774"
+SIZE="259"
+ENDFILE
+VALUE "<project>\synthesis\LedBlinkingDSpeed.vhd,syn_hdl"
+STATE="utd"
+TIME="1477216778"
+SIZE="88479"
+ENDFILE
+VALUE "<project>\synthesis\LedBlinkingDSpeed_sdc.sdc,syn_sdc"
+STATE="utd"
+TIME="1477216774"
+SIZE="901"
+ENDFILE
+VALUE "<project>\synthesis\LedBlinkingDSpeed_syn.prj,prj"
+STATE="utd"
+TIME="1477216776"
+SIZE="2218"
+ENDFILE
 ENDLIST
 LIST UsedFile
 ENDLIST
 LIST NewModulesInfo
+LIST "LedBlinkingDSpeed::work"
+FILE "<project>\hdl\LedBlinkingDSpeed.vhd,hdl"
+LIST AssociatedStimulus
+VALUE "<project>\stimulus\LedBlinkingDSpeed_tb.vhd,tb_hdl"
+ENDLIST
+LIST SynthesisConstraints
+VALUE "<project>\constraint\LedBlinkingDSpeed_sdc.sdc,sdc"
+ENDLIST
+LIST TimingConstraints
+VALUE "<project>\constraint\LedBlinkingDSpeed_sdc.sdc,sdc"
+ENDLIST
+LIST ProjectState5.1
+LIST Impl1
+LiberoState=Post_Synthesis
+ideSTIMULUS=StateSuccess
+ideSYNTHESIS(<project>\synthesis\LedBlinkingDSpeed.edn,syn_edn)=StateSuccess
+LIST FlowOptions
+UsePhySynth=FALSE
+UseSynth=TRUE
+ENDLIST
+Used_File_List
+ENDUsed_File_List
+ENDLIST
+ENDLIST
+ENDLIST
 ENDLIST
 LIST AssociatedStimulus
+LIST LedBlinkingDSpeed
+VALUE "<project>\stimulus\LedBlinkingDSpeed_tb.vhd,tb_hdl"
+ENDLIST
 ENDLIST
 LIST Other_Association
 ENDLIST
 LIST SimulationOptions
 UseAutomaticDoFile=true
 IncludeWaveDo=false
 Type=max
-RunTime=1000ns
+RunTime=650us
 Resolution=1fs
 VsimOpt=
-EntityName=testbench
+EntityName=LedBlinkingDSpeed_tb
 TopInstanceName=<top>_0
 DoFileName=
 DoFileName2=wave.do
 DoFileParams=
 DisplayDUTWave=false
-LogAllSignals=false
+LogAllSignals=true
 DisablePulseFiltering=false
 DumpVCD=false
 VCDFileName=power.vcd
@@ -182,6 +253,19 @@ IS32BIT="1"
 EndProfile
 ENDLIST
 LIST ProjectState5.1
+LIST "LedBlinkingDSpeed::work"
+LIST Impl1
+LiberoState=Post_Synthesis
+ideSTIMULUS=StateSuccess
+ideSYNTHESIS(<project>\synthesis\LedBlinkingDSpeed.edn,syn_edn)=StateSuccess
+LIST FlowOptions
+UsePhySynth=FALSE
+UseSynth=TRUE
+ENDLIST
+Used_File_List
+ENDUsed_File_List
+ENDLIST
+ENDLIST
 ENDLIST
 LIST ExcludePackageForSimulation
 ENDLIST
@@ -195,10 +279,8 @@ LIST UserCustomizedFileList
 ENDLIST
 LIST OpenedFileList
 ORIENTATION;HORIZONTAL
-Reports;Reports;0
-ReportsCurrentItem;Project Summary:Lab2_VHDL.log
 StartPage;StartPage;0
-ACTIVEVIEW;Reports
+ACTIVEVIEW;StartPage
 ENDLIST
 LIST ModuleSubBlockList
 LIST "ClkGen::work","hdl\ClkGen.vhd","FALSE","FALSE"
@@ -215,6 +297,9 @@ SUBBLOCK "Reset_out::work","hdl\Reset_out.vhd","FALSE","FALSE"
 ENDLIST
 LIST "Reset_out::work","hdl\Reset_out.vhd","FALSE","FALSE"
 ENDLIST
+LIST "LedBlinkingDSpeed_tb::work","stimulus\LedBlinkingDSpeed_tb.vhd","FALSE","TRUE"
+SUBBLOCK "LedBlinkingDSpeed::work","hdl\LedBlinkingDSpeed.vhd","FALSE","FALSE"
+ENDLIST
 ENDLIST
 LIST ActiveTestBenchList
 ENDLIST

Lab2_VHDL/constraint/io/pre/LedBlinkingDSpeed.io.pdc

@@ -0,0 +1,81 @@
+# Microsemi I/O Physical Design Constraints file
+
+# User I/O Constraints file 
+
+# Version: v11.7 SP1 11.7.1.11
+
+# Family: IGLOO2 , Die: M2GL025 , Package: 256 VF
+
+# Date generated: Sun Oct 23 02:59:56 2016 
+
+
+# 
+# User Locked I/O Bank Settings
+# 
+
+
+# 
+# Unlocked I/O Bank Settings
+# The I/O Bank Settings can be locked by directly editing this file
+# or by making changes in the I/O Attribute Editor
+# 
+
+
+# 
+# User Locked I/O settings
+# 
+
+set_io SW1            \
+    -pinname H12      \
+    -fixed yes        \
+    -DIRECTION INPUT
+
+
+set_io SW2            \
+    -pinname H13      \
+    -fixed yes        \
+    -DIRECTION INPUT
+
+
+set_io clk            \
+    -pinname H16      \
+    -fixed yes        \
+    -DIRECTION INPUT
+
+
+set_io green_led1      \
+    -pinname J16       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
+
+
+set_io green_led2      \
+    -pinname M16       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
+
+
+set_io red_led1        \
+    -pinname K16       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
+
+
+set_io red_led2        \
+    -pinname N16       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
+
+
+
+# 
+# Dedicated Peripheral I/O Settings
+# 
+
+
+# 
+# Unlocked I/O settings
+# The I/Os in this section are unplaced or placed but are not locked
+# the other listed attributes have been applied
+# 
+