Merge branch 'main' into feat/esp32c3-icm42670-example

.github/workflows/ci.yml

@@ -131,8 +131,6 @@ jobs:
       # for each supported image format.
       - name: build esp32c2-hal (no features)
         run: cd esp32c2-hal/ && cargo build --examples
-      - name: build esp32c2-hal (direct-boot)
-        run: cd esp32c2-hal/ && cargo build --examples --features=direct-boot
       # Subsequent steps can just check the examples instead, as we're already
       # confident that they link.
       - name: check esp32c2-hal (common features)
@@ -183,8 +181,6 @@ jobs:
       # for each supported image format.
       - name: build esp32c3-hal (no features)
         run: cd esp32c3-hal/ && cargo +nightly build --examples
-      - name: build esp32c3-hal (direct-boot)
-        run: cd esp32c3-hal/ && cargo +nightly build --examples --features=direct-boot
       - name: build esp32c3-hal (mcu-boot)
         run: cd esp32c3-hal/ && cargo +nightly build --examples --features=mcu-boot
       # Subsequent steps can just check the examples instead, as we're already
@@ -242,8 +238,6 @@ jobs:
       # for each supported image format.
       - name: build esp32c6-hal (no features)
         run: cd esp32c6-hal/ && cargo +nightly build --examples
-      - name: build esp32c6-hal (direct-boot)
-        run: cd esp32c6-hal/ && cargo +nightly build --examples --features=direct-boot
       # Subsequent steps can just check the examples instead, as we're already
       # confident that they link.
       - name: check esp32c6-hal (common features)
@@ -314,8 +308,6 @@ jobs:
       # for each supported image format.
       - name: build esp32h2-hal (no features)
         run: cd esp32h2-hal/ && cargo +nightly build --examples
-      - name: build esp32h2-hal (direct-boot)
-        run: cd esp32h2-hal/ && cargo +nightly build --examples --features=direct-boot
       # Subsequent steps can just check the examples instead, as we're already
       # confident that they link.
       - name: check esp32h2-hal (common features)
@@ -348,7 +340,7 @@ jobs:
       - name: rustdoc
         run: cd esp32h2-hal/ && cargo doc --features=eh1
 
-  ulp-riscv-hal:
+  esp-ulp-riscv-hal:
     runs-on: ubuntu-latest
 
     steps:
@@ -362,11 +354,11 @@ jobs:
 
       # Perform a full build initially to verify that the examples not only
       # build, but also link successfully.
-      - name: build ulp-riscv-hal (esp32s3)
-        run: cd ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples
+      - name: build esp-ulp-riscv-hal (esp32s3)
+        run: cd esp-ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples
       # Ensure documentation can be built
       - name: rustdoc
-        run: cd ulp-riscv-hal/ && cargo doc --features=esp32s3
+        run: cd esp-ulp-riscv-hal/ && cargo doc --features=esp32s3
 
   esp32s2-hal:
     runs-on: ubuntu-latest
@@ -382,13 +374,13 @@ jobs:
         with:
           target: riscv32imc-unknown-none-elf
           toolchain: nightly
-          components: rust-src          
+          components: rust-src
       - uses: Swatinem/rust-cache@v2
 
-      # build the ulp-riscv-hal examples first to make sure the examples which expect
+      # build the esp-ulp-riscv-hal examples first to make sure the examples which expect
       # the ELF files to be present will compile
-      - name: build ulp-riscv-hal prerequisites
-        run: cd ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s2 --examples
+      - name: build esp-ulp-riscv-hal prerequisites
+        run: cd esp-ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s2 --examples
 
       # Perform a full build initially to verify that the examples not only
       # build, but also link successfully.
@@ -457,22 +449,20 @@ jobs:
         with:
           target: riscv32imc-unknown-none-elf
           toolchain: nightly
-          components: rust-src          
+          components: rust-src
       - uses: Swatinem/rust-cache@v2
 
-      # build the ulp-riscv-hal examples first to make sure the examples which expect
+      # build the esp-ulp-riscv-hal examples first to make sure the examples which expect
       # the ELF files to be present will compile
-      - name: build ulp-riscv-hal prerequisites
-        run: cd ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples
+      - name: build esp-ulp-riscv-hal prerequisites
+        run: cd esp-ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples
 
       # Perform a full build initially to verify that the examples not only
       # build, but also link successfully.
       # We also use this as an opportunity to verify that the examples link
       # for each supported image format.
       - name: build esp32s3-hal (no features)
         run: cd esp32s3-hal/ && cargo +esp build --examples
-      - name: build esp32s3-hal (direct-boot)
-        run: cd esp32s3-hal/ && cargo +esp build --examples --features=direct-boot
       # Subsequent steps can just check the examples instead, as we're already
       # confident that they link.
       - name: check esp32s3-hal (common features)
@@ -603,13 +593,13 @@ jobs:
         with:
           target: riscv32imc-unknown-none-elf
           toolchain: "1.67"
-          components: rust-src          
+          components: rust-src
       - uses: Swatinem/rust-cache@v2
 
-      # build the ulp-riscv-hal examples first to make sure the examples which expect
+      # build the esp-ulp-riscv-hal examples first to make sure the examples which expect
       # the ELF files to be present will compile
-      - name: build ulp-riscv-hal prerequisites
-        run: cd ulp-riscv-hal/ && RUSTC_BOOTSTRAP=1 cargo +1.67 build --release --features=esp32s3 --examples
+      - name: build esp-ulp-riscv-hal prerequisites
+        run: cd esp-ulp-riscv-hal/ && RUSTC_BOOTSTRAP=1 cargo +1.67 build --release --features=esp32s3 --examples
 
       # Verify the MSRV for all Xtensa chips.
       - name: msrv (esp32-hal)
@@ -638,25 +628,26 @@ jobs:
       - uses: actions/checkout@v3
       - uses: dtolnay/rust-toolchain@v1
         with:
+          target: riscv32imc-unknown-none-elf, riscv32imac-unknown-none-elf
           toolchain: stable
           components: clippy
       - uses: Swatinem/rust-cache@v2
 
       # Run clippy on all packages targeting RISC-V.
       - name: clippy (esp-riscv-rt)
-        run: cargo +stable clippy --manifest-path=esp-riscv-rt/Cargo.toml -- -D warnings
+        run: cd esp-riscv-rt && cargo +stable clippy -- -D warnings
       - name: clippy (esp32c2-hal)
-        run: cargo +stable clippy --manifest-path=esp32c2-hal/Cargo.toml -- -D warnings
+        run: cd esp32c2-hal && cargo +stable clippy -- -D warnings
       - name: clippy (esp32c3-hal)
-        run: cargo +stable clippy --manifest-path=esp32c3-hal/Cargo.toml -- -D warnings
+        run: cd esp32c3-hal && cargo +stable clippy -- -D warnings
       - name: clippy (esp32c6-hal)
-        run: cargo +stable clippy --manifest-path=esp32c6-hal/Cargo.toml -- -D warnings
+        run: cd esp32c6-hal && cargo +stable clippy -- -D warnings
       - name: clippy (esp32c6-lp-hal)
-        run: cargo +stable clippy --manifest-path=esp32c6-lp-hal/Cargo.toml -- -D warnings -A asm-sub-register
+        run: cd esp32c6-lp-hal && cargo +stable clippy -- -D warnings -A asm-sub-register
       - name: clippy (esp32h2-hal)
-        run: cargo +stable clippy --manifest-path=esp32h2-hal/Cargo.toml -- -D warnings
-      - name: clippy (ulp-riscv-hal)
-        run: cargo +stable clippy --manifest-path=ulp-riscv-hal/Cargo.toml --features=esp32s3 -- -D warnings -A asm-sub-register
+        run: cd esp32h2-hal && cargo +stable clippy -- -D warnings
+      - name: clippy (esp-ulp-riscv-hal)
+        run: cd esp-ulp-riscv-hal && cargo +stable clippy --features=esp32s3 -- -D warnings -A asm-sub-register
 
   clippy-xtensa:
     runs-on: ubuntu-latest
@@ -716,5 +707,5 @@ jobs:
         run: cargo fmt --all --manifest-path=esp32s2-hal/Cargo.toml -- --check
       - name: rustfmt (esp32s3-hal)
         run: cargo fmt --all --manifest-path=esp32s3-hal/Cargo.toml -- --check
-      - name: rustfmt (ulp-riscv-hal)
-        run: cargo fmt --all --manifest-path=ulp-riscv-hal/Cargo.toml -- --check
+      - name: rustfmt (esp-ulp-riscv-hal)
+        run: cargo fmt --all --manifest-path=esp-ulp-riscv-hal/Cargo.toml -- --check

.vscode/settings.json

@@ -23,6 +23,12 @@
   ],
 
   "[toml]": {
-    "editor.formatOnSave": false
+    "editor.formatOnSave": false,
+  },
+  "[markdown]": {
+    "editor.formatOnSave": false,
+  },
+  "[jsonc]": {
+    "editor.formatOnSave": false,
   }
 }

CHANGELOG.md

@@ -7,10 +7,43 @@ Please note that only changes to the `esp-hal-common` package are tracked in thi
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-[Unreleased]
+## [Unreleased]
 
 ### Added
+- ESP32-C6: LP core clock is configurable (#907)
+- Derive `Clone` and `Copy` for `EspTwaiFrame` (#914)
+- A way to configure inverted pins (#912)
 
+### Changed
+
+- C2, C3: atomic emulation trap is now opt-in (#904)
+- Improve DMA documentation & clean up module (#915)
+
+### Fixed
+
+- ESP32-C2/C3 examples: fix build error (#899)
+- ESP32-S3: Fix GPIO interrupt handler crashing when using GPIO48. (#898)
+- Fixed short wait times in embassy causing hangs (#906)
+- Make sure to clear LP/RTC RAM before loading code (#916)
+
+### Removed
+
+### Breaking
+- Direct boot support has been removed (#903).
+- `Spi::new`/`Spi::new_half_duplex` takes no gpio pin now, instead you need to call `with_pins` to setup those (#901).
+
+## [0.13.1] - 2023-11-02
+
+### Fixed
+
+- ESP32-C3: Make sure BLE and WiFi are not powered down when esp-wifi needs them (#891)
+- ESP32-C6/H2: Fix setting UART baud rate (#893)
+
+## [0.13.0] - 2023-10-31
+
+### Added
+
+- Implement SetFrequencyCycle and PwmPin from embedded_hal for PwmPin of MCPWM. (#880)
 - Added `embassy-time-systick` to ESP32-S2 (#827)
 - Implement enabling/disabling BLE clock on ESP32-C6 (#784)
 - Async support for RMT (#787)
@@ -19,8 +52,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add UART support for splitting into TX and RX (#754)
 - Async support for I2S (#801)
 - Async support for PARL_IO (#807)
-- Implement `embeded_hal_async::delay::DelayUs` trait for `SYSTIMER` alarms (#812)
-  - This trait is NOT implemented when the `embassy-time-systick` feature is enabled!
 - ETM driver, GPIO ETM (#819)
 - (G)DMA AES support (#821)
 - SYSTIMER ETM functionality (#828)
@@ -31,18 +62,25 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Embassy `#[main]` convenience macro (#841)
 - Add a `defmt` feature to the `esp-hal-smartled` package (#846)
 - Support 16MB octal PS-RAM for ESP32-S3 (#858)
+- RISCV TRACE Encoder driver for ESP32-C6 / ESP32-H2 (#864)
+- `embedded_hal` 1 `InputPin` and `embedded_hal_async` `Wait` impls for open drain outputs (#905)
 
 ### Changed
 
 - Bumped MSRV to 1.67 (#798)
 - Optimised multi-core critical section implementation (#797)
+- Changed linear- and curve-calibrated ADC to provide readings in mV (#836)
 
 ### Fixed
 
 - S3: Allow powering down RC_FAST_CLK (#796)
 - UART/ESP32: fix calculating FIFO counter with `get_rx_fifo_count()` (#804)
 - Xtensa targets: Use ESP32Reset - not Reset (#823)
 - Examples should now work with the `defmt` feature (#810)
+- Fixed a race condition causing SpiDma to stop working unexpectedly (#869)
+- Fixed async uart serial, and updated the embassy_serial examples (#871).
+- Fix ESP32-S3 direct-boot (#873)
+- Fix ESP32-C6 ADC (#876)
 
 ### Removed
 
@@ -70,7 +108,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - The SPI traits are no longer re-exported in the main prelude, but from preludes in `spi::master`/`spi::slave` instead (#860)
 - The `embedded-hal-1` and `embedded-hal-async` traits are no longer re-exported in the prelude (#860)
 
-## [0.12.0]
+## [0.12.0] - 2023-09-05
 
 ### Added
 
@@ -87,6 +125,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add `defmt` feature to enable log output (#773)
 - A new macro to load LP core code on ESP32-C6 (#779)
 - Add `ECC`` peripheral driver (#785)
+- Initial LLD support for Xtensa chips (#861).
 
 ### Changed
 
@@ -268,7 +307,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## [0.1.0] - 2022-08-05
 
-[Unreleased]: https://github.com/esp-rs/esp-hal/compare/v0.12.0...HEAD
+[Unreleased]: https://github.com/esp-rs/esp-hal/compare/v0.13.1...HEAD
+[0.13.1]: https://github.com/esp-rs/esp-hal/compare/v0.13.0...v0.13.1
+[0.13.0]: https://github.com/esp-rs/esp-hal/compare/v0.12.0...v0.13.0
 [0.12.0]: https://github.com/esp-rs/esp-hal/compare/v0.11.0...v0.12.0
 [0.11.0]: https://github.com/esp-rs/esp-hal/compare/v0.10.0...v0.11.0
 [0.10.0]: https://github.com/esp-rs/esp-hal/compare/v0.9.0...v0.10.0

README.md

@@ -23,29 +23,31 @@ If you have any questions, comments, or concerns, please [open an issue], [start
 
 For information relating to the development of Rust applications on ESP devices, please first read [The Rust on ESP Book].
 
-For information about the HAL and how to use it in your own projects, please refer to the documentation on [crates.io] for the relevant chip.
+For information about the HAL and how to use it in your own projects, please refer to the documentation on [docs.rs] for the relevant chip.
 
-[The Rust on ESP Book]: (https://esp-rs.github.io/book/)
-[crates.io]: https://crates.io
+[The Rust on ESP Book]: https://esp-rs.github.io/book/
+[docs.rs]: https://docs.rs
 
 ## Resources
 
 - [The Rust Programming Language](https://doc.rust-lang.org/book/)
 - [The Embedded Rust Book](https://docs.rust-embedded.org/book/index.html)
+- [The Embedonomicon](https://docs.rust-embedded.org/embedonomicon/)
 - [The Rust on ESP Book](https://esp-rs.github.io/book/)
+- [Embedded Rust (no_std) on Espressif](https://esp-rs.github.io/no_std-training/)
 
 ## HAL Crates
 
-|      Crate       |             Target             | Technical Reference Manual |
-| :--------------: | :----------------------------: | :------------------------: |
-|   [esp32-hal]    |    `xtensa-esp32-none-elf`     |          [ESP32]           |
-|  [esp32c2-hal]   | `riscv32imc-unknown-none-elf`  |         [ESP32-C2]         |
-|  [esp32c3-hal]   | `riscv32imc-unknown-none-elf`  |         [ESP32-C3]         |
-|  [esp32c6-hal]   | `riscv32imac-unknown-none-elf` |         [ESP32-C6]         |
-| [esp32c6-lp-hal] | `riscv32imac-unknown-none-elf` |            N/A             |
-|  [esp32h2-hal]   | `riscv32imac-unknown-none-elf` |         [ESP32-H2]         |
-|  [esp32s2-hal]   |   `xtensa-esp32s2-none-elf`    |         [ESP32-S2]         |
-|  [esp32s3-hal]   |   `xtensa-esp32s3-none-elf`    |         [ESP32-S3]         |
+|      Crate       |                   Documentation                    | Technical Reference Manual |             Target             |
+| :--------------: | :------------------------------------------------: | :------------------------: | :----------------------------: |
+|   [esp32-hal]    |   [![esp32-hal-docs]](https://docs.rs/esp32-hal)   |          [ESP32]           |    `xtensa-esp32-none-elf`     |
+|  [esp32c2-hal]   | [![esp32c2-hal-docs]](https://docs.rs/esp32c2-hal) |         [ESP32-C2]         | `riscv32imc-unknown-none-elf`  |
+|  [esp32c3-hal]   | [![esp32c3-hal-docs]](https://docs.rs/esp32c3-hal) |         [ESP32-C3]         | `riscv32imc-unknown-none-elf`  |
+|  [esp32c6-hal]   | [![esp32c6-hal-docs]](https://docs.rs/esp32c6-hal) |         [ESP32-C6]         | `riscv32imac-unknown-none-elf` |
+| [esp32c6-lp-hal] |                        N/A                         |            N/A             | `riscv32imac-unknown-none-elf` |
+|  [esp32h2-hal]   | [![esp32h2-hal-docs]](https://docs.rs/esp32h2-hal) |         [ESP32-H2]         | `riscv32imac-unknown-none-elf` |
+|  [esp32s2-hal]   | [![esp32s2-hal-docs]](https://docs.rs/esp32s2-hal) |         [ESP32-S2]         |   `xtensa-esp32s2-none-elf`    |
+|  [esp32s3-hal]   | [![esp32s3-hal-docs]](https://docs.rs/esp32s3-hal) |         [ESP32-S3]         |   `xtensa-esp32s3-none-elf`    |
 
 [esp32-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32-hal
 [esp32c2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c2-hal
@@ -55,6 +57,13 @@ For information about the HAL and how to use it in your own projects, please ref
 [esp32h2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32h2-hal
 [esp32s2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s2-hal
 [esp32s3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s3-hal
+[esp32-hal-docs]: https://img.shields.io/docsrs/esp32-hal?color=C96329&logo=rust&style=flat-square
+[esp32c2-hal-docs]: https://img.shields.io/docsrs/esp32c2-hal?color=C96329&logo=rust&style=flat-square
+[esp32c3-hal-docs]: https://img.shields.io/docsrs/esp32c3-hal?color=C96329&logo=rust&style=flat-square
+[esp32c6-hal-docs]: https://img.shields.io/docsrs/esp32c6-hal?color=C96329&logo=rust&style=flat-square
+[esp32h2-hal-docs]: https://img.shields.io/docsrs/esp32h2-hal?color=C96329&logo=rust&style=flat-square
+[esp32s2-hal-docs]: https://img.shields.io/docsrs/esp32s2-hal?color=C96329&logo=rust&style=flat-square
+[esp32s3-hal-docs]: https://img.shields.io/docsrs/esp32s3-hal?color=C96329&logo=rust&style=flat-square
 [esp32]: https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf
 [esp32-c2]: https://www.espressif.com/sites/default/files/documentation/esp8684_technical_reference_manual_en.pdf
 [esp32-c3]: https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
@@ -74,7 +83,7 @@ There are a number of other crates within the [esp-rs organization] which can be
 | [esp-ieee802154] |          Low-level IEEE802.15.4 driver for the ESP32-C6 and ESP32-H2           |
 |  [esp-println]   |                Provides `print!` and `println!` implementations                |
 |  [esp-storage]   | Implementation of [embedded-storage] traits to access unencrypted flash memory |
-|    [esp-wifi]    |                      `no_std` Wi-Fi/Bluetooth LE support                       |
+|    [esp-wifi]    |                       `no_std` Wi-Fi/BLE/ESP-NOW support                       |
 
 [esp-rs organization]: https://github.com/esp-rs
 [esp-alloc]: https://github.com/esp-rs/esp-alloc
@@ -103,7 +112,7 @@ The **M**inimum **S**upported **R**ust **V**ersion is `1.67.0` for all packages.
 
 RISC-V is officially supported by the official Rust compiler, however, it should be noted that targeting the Xtensa ISA currently requires the use of the [esp-rs/rust] compiler fork. Our recommend method of installation is [espup].
 
-When targetting the RISC-V architecture, it is necessary to set `RUSTC_BOOTSTRAP=1` in order to build with a previous stable release; this is not required when targeting Xtensa.
+When targetting the RISC-V architecture *and* using a `stable` Rust release, it is necessary to set `RUSTC_BOOTSTRAP=1` in order to build successfully; this is not required when using a `nightly` release or when targeting Xtensa.
 
 [esp-rs/rust]: https://github.com/esp-rs/rust
 [espup]: https://github.com/esp-rs/espup