Update sys.

BK0011M.qpf

@@ -1,12 +1,2 @@
-#
-# please keep this file read-only!
-# Quartus changes this file everytime revision is switched, 
-# and it will be marked as changed with every commit.
-#
-
-QUARTUS_VERSION = "16.1"
-DATE = "23:13:02  April 27, 2017"
-
-# Revisions
-
+QUARTUS_VERSION = "17.0"
 PROJECT_REVISION = "BK0011M"

BK0011M.sv

@@ -31,7 +31,7 @@ module emu
 	input         RESET,
 
 	//Must be passed to hps_io module
-	inout  [44:0] HPS_BUS,
+	inout  [45:0] HPS_BUS,
 
 	//Base video clock. Usually equals to CLK_SYS.
 	output        CLK_VIDEO,
@@ -65,7 +65,9 @@ module emu
 	output [15:0] AUDIO_R,
 	output        AUDIO_S, // 1 - signed audio samples, 0 - unsigned
 	output  [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
-	input         TAPE_IN,
+
+	//ADC
+	inout   [3:0] ADC_BUS,
 
 	// SD-SPI
 	output        SD_SCK,
@@ -117,7 +119,8 @@ module emu
 
 	input         OSD_STATUS
 );
-
+
+assign ADC_BUS  = 'Z;
 assign USER_OUT = '1;
 assign {UART_RTS, UART_TXD, UART_DTR} = 0;
 assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;

BK0011M_Q13.qpf

@@ -0,0 +1,2 @@
+QUARTUS_VERSION = "13.1"
+PROJECT_REVISION = "BK0011M_Q13"

BK0011M_Q13.qsf

@@ -0,0 +1,45 @@
+# --------------------------------------------------------------------------
+#
+# MiSTer project
+#
+# WARNING WARNING WARNING:
+# Do not add files to project in Quartus IDE! It will mess this file!
+# Add the files manually to files.qip file.
+#
+# --------------------------------------------------------------------------
+
+set_global_assignment -name TOP_LEVEL_ENTITY sys_top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
+set_global_assignment -name SEED 1
+
+source sys/sys.tcl
+set_global_assignment -name QIP_FILE files.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BK0011M_Q13.srf

@@ -0,0 +1,28 @@
+{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL information at MC6845.v(280): always construct contains both blocking and non-blocking assignments" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(601): object \"VSET\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic." {  } {  } 0 12030 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Dummy RLC values generated in IBIS model files for device 5CSEBA6 with package UFBGA and pin count 672" {  } {  } 0 205009 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Ignored filter at sys_top.sdc(10): vip\|output_inst\|vid_clk could not be matched with a net" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(9): Argument <targets> is an empty collection" {  } {  } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Ignored filter at sys_top.sdc(29): VID_CLK could not be matched with a clock" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Timing characteristics of device 5CSEBA6U23I7 are preliminary" {  } {  } 0 334000 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"emu:emu\|rom_map_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument <targets> is an empty collection" {  } {  } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Ignored locations or region assignments to the following nodes" {  } {  } 0 15705 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Design contains 4 input pin(s) that do not drive logic" {  } {  } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "24 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Following 5 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" {  } {  } 0 169064 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "altera_pll.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "altera_cyclonev_pll.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "altera_pll_reconfig_core.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}

files.qip

@@ -0,0 +1,9 @@
+set_global_assignment -name QIP_FILE VM1/VM1.qip
+set_global_assignment -name QIP_FILE sdram.qip
+set_global_assignment -name SYSTEMVERILOG_FILE ym2149.sv
+set_global_assignment -name SYSTEMVERILOG_FILE video.sv
+set_global_assignment -name VERILOG_FILE translate.v
+set_global_assignment -name SYSTEMVERILOG_FILE memory.sv
+set_global_assignment -name SYSTEMVERILOG_FILE keyboard.sv
+set_global_assignment -name SYSTEMVERILOG_FILE disk.sv
+set_global_assignment -name SYSTEMVERILOG_FILE BK0011M.sv

sdram.sdc

@@ -1,6 +1,6 @@
 derive_pll_clocks
 
-create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|*[1].*|divclk}] \
                        -name SDRAM_CLK [get_ports {SDRAM_CLK}]
 
 derive_clock_uncertainty
@@ -9,9 +9,5 @@ derive_clock_uncertainty
 set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
 set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
 
-set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
-                    -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-                                                  -setup 2
-
 set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
 set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]

sys/alsa.sv

@@ -23,18 +23,21 @@ module alsa
 (
 	input             reset,
 
+	output reg        en_out,
+	input             en_in,
+
 	input             ram_clk,
 	output reg [28:0] ram_address,
 	output reg  [7:0] ram_burstcount,
 	input             ram_waitrequest,
 	input      [63:0] ram_readdata,
 	input             ram_readdatavalid,
 	output reg        ram_read,
-	
+
 	input             spi_ss,
 	input             spi_sck,
 	input             spi_mosi,
-	
+
 	output reg [15:0] pcm_l,
 	output reg [15:0] pcm_r
 );
@@ -44,7 +47,7 @@ reg [127:0] spi_data;
 always @(posedge spi_sck, posedge spi_ss) begin
 	reg [7:0] mosi;
 	reg [6:0] spicnt = 0;
-	
+
 	if(spi_ss) spicnt <= 0;
 	else begin
 		mosi <= {mosi[6:0],spi_mosi};
@@ -68,18 +71,18 @@ always @(posedge ram_clk) begin
 	n1 <= spi_new;
 	n2 <= n1;
 	n3 <= n2;
-	
+
 	data1 <= spi_data;
 	data2 <= data1;
-	
+
 	if(~n3 & n2) {buf_wptr,buf_len,buf_addr} <= data2[95:0];
 end
 
 reg [31:0] buf_rptr = 0;
 always @(posedge ram_clk) begin
 	reg got_first = 0;
 	reg ready = 0;
-	reg ud;
+	reg ud = 0;
 	reg [31:0] readdata;
 
 	if(~ram_waitrequest) ram_read <= 0;
@@ -90,15 +93,15 @@ always @(posedge ram_clk) begin
 		if(buf_rptr[31:2] >= buf_len[31:2]) buf_rptr <= 0;
 	end
 
-	if(reset) {ready, got_first} <= 0;
+	if(reset) {ready, got_first, ram_burstcount} <= 0;
 	else
 	if(buf_rptr[31:2] != buf_wptr[31:2]) begin
 		if(~got_first) begin
 			buf_rptr <= buf_wptr;
 			got_first <= 1;
 		end
 		else
-		if(!ram_burstcount && ~ram_waitrequest && ~ready) begin
+		if(!ram_burstcount && ~ram_waitrequest && ~ready && en_out == en_in) begin
 			ram_address <= buf_addr[31:3] + buf_rptr[31:3];
 			ud <= buf_rptr[2];
 			ram_burstcount <= 1;
@@ -111,6 +114,8 @@ always @(posedge ram_clk) begin
 		{pcm_r,pcm_l} <= readdata;
 		ready <= 0;
 	end
+
+	if(ce_48k) en_out <= ~en_out;
 end
 
 reg ce_48k;