core: arm: imx: add 6ULL EVK support

Add i.MX6 ULL EVK support.
i.MX6ULL is derivative from i.MX6UL, so reuse some code for i.MX6UL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

.travis.yml

@@ -187,6 +187,9 @@ script:
   # i.MX6UL 14X14 EVK
   - $make PLATFORM=imx-mx6ulevk ARCH=arm CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0x80800000 CFG_DT_ADDR=0x83000000 CFG_DT=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4
 
+  # i.MX6ULL 14X14 EVK
+  - $make PLATFORM=imx-mx6ullevk ARCH=arm CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0x80800000 CFG_DT=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4
+
   # i.MX6Quad SABRE
   - $make PLATFORM=imx-mx6qsabrelite
   - $make PLATFORM=imx-mx6qsabresd

MAINTAINERS.md

@@ -13,6 +13,7 @@ for these platforms.
 | FSL i.MX6 Quad SABRE Lite Board	|`Yan Yan <yan.yan@windriver.com>`,`Feng Yu <Yu.Feng@windriver.com>`|
 | FSL i.MX6 Quad SABRE SD Board		|`Yan Yan <yan.yan@windriver.com>`,`Feng Yu <Yu.Feng@windriver.com>`|
 | FSL i.MX6 UltraLite EVK Board		|`Peng Fan <peng.fan@nxp.com>`|
+| NXP i.MX6 ULL EVK Board		|`Peng Fan <peng.fan@nxp.com>`|
 | ARM Foundation FVP			|`Linaro <op-tee@linaro.org>`|
 | HiKey Board (HiSilicon Kirin 620)	|`Linaro <op-tee@linaro.org>`|
 | HiSilicon D02				|`Linaro <op-tee@linaro.org>`|

core/arch/arm/plat-imx/conf.mk

@@ -2,13 +2,16 @@ PLATFORM_FLAVOR ?= mx6ulevk
 
 # Get SoC associated with the PLATFORM_FLAVOR
 mx6ul-flavorlist = mx6ulevk
+mx6ull-flavorlist = mx6ullevk
 mx6q-flavorlist = mx6qsabrelite mx6qsabresd
 mx6d-flavorlist =
 mx6dl-flavorlist = mx6dlsabresd
 mx6s-flavorlist =
 
 ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
 $(call force,CFG_MX6UL,y)
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
+$(call force,CFG_MX6ULL,y)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
 $(call force,CFG_MX6Q,y)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
@@ -35,8 +38,8 @@ CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
 CFG_WITH_STACK_CANARIES ?= y
 
 
-# i.MX6UL specific config
-ifeq ($(CFG_MX6UL),y)
+# i.MX6UL/ULL specific config
+ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL)))
 include core/arch/arm/cpu/cortex-a7.mk
 
 $(call force,CFG_MX6,y)

core/arch/arm/plat-imx/imx-regs.h

@@ -73,7 +73,7 @@
 #define GIC_BASE			0x00A00000
 #define GICD_OFFSET			0x1000
 
-#if defined(CFG_MX6UL)
+#if defined(CFG_MX6UL) || defined(CFG_MX6ULL)
 #define GICC_OFFSET			0x2000
 /* No CAAM on i.MX6ULL */
 #define CAAM_BASE			0x02140000
@@ -141,7 +141,7 @@
 #define CSU_ACCESS_ALL			0x00FF00FF
 #define CSU_SETTING_LOCK		0x01000100
 
-#ifdef CFG_MX6UL
+#if defined(CFG_MX6UL) || defined(CFG_MX6ULL)
 #define DRAM0_BASE			0x80000000
 #else
 #define DRAM0_BASE			0x10000000

core/arch/arm/plat-imx/platform_config.h

@@ -32,9 +32,9 @@
 
 #define STACK_ALIGNMENT			64
 
-/* For i.MX 6UltraLite EVK board */
+/* For i.MX 6UltraLite and 6ULL EVK board */
 
-#if defined(CFG_MX6UL)
+#if defined(CFG_MX6UL) || defined(CFG_MX6ULL)
 #include <imx-regs.h>
 
 #ifdef CFG_WITH_PAGER

core/arch/arm/plat-imx/sub.mk

@@ -9,8 +9,7 @@ ifneq (,$(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL)))
 srcs-y += a9_plat_init.S imx6.c
 endif
 
-ifneq (,$(filter y, $(CFG_MX6UL))
+ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL)))
 srcs-y += a7_plat_init.S
+srcs-y += imx6ul.c
 endif
-
-srcs-$(CFG_MX6UL) += imx6ul.c