Fix FIQ mask for the native interrupt handler for arm32

In Arm aarch32 mode, FIQ is not masked by hardware in IRQ mode.
For GICv2, IRQ is for foreign interrupt and already masked by hardware
in FIQ mode which is used for native interrupt.
For GICv3, FIQ is for foreign interrupt. It's not masked by hardware in
IRQ mode which is used for natvie interrupt. We need to mask it explicitly.

Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core/arch/arm/kernel/thread_a32.S

@@ -443,6 +443,16 @@ END_FUNC thread_rpc
 
 /* The handler of native interrupt. */
 .macro	native_intr_handler mode:req
+	.ifc	\mode\(),irq
+	/*
+	 * Foreign interrupts should be masked.
+	 * For GICv2, IRQ is for foreign interrupt and already masked by
+	 * hardware in FIQ mode which is used for native interrupt.
+	 * For GICv3, FIQ is for foreign interrupt. It's not masked by hardware
+	 * in IRQ mode which is used for natvie interrupt.
+	 */
+	cpsid	f
+	.endif
 	/*
 	 * FIQ and IRQ have a +4 offset for lr compared to preferred return
 	 * address