plat-ti: Add secure paging support for DRA7xx/AM57xx

Add definitions for secure SRAM and DRAM space for builds with CFG_WITH_PAGER enabled. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
OP-TEE · Apr 27, 2017 · 6e2a00b · 6e2a00b
1 parent a105bde
commit 6e2a00b
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diff --git a/core/arch/arm/plat-ti/main.c b/core/arch/arm/plat-ti/main.c
@@ -54,6 +54,7 @@ static struct gic_data gic_data;
 static struct serial8250_uart_data console_data __early_bss;
 static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH];
 
+register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, CFG_TEE_RAM_VA_SIZE);
 register_phys_mem(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE);
 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);

diff --git a/core/arch/arm/plat-ti/platform_config.h b/core/arch/arm/plat-ti/platform_config.h
@@ -37,6 +37,11 @@
 #define TZDRAM_BASE     0xbdb00000
 #define TZDRAM_SIZE     0x01c00000
 
+#ifdef CFG_WITH_PAGER
+#define TZSRAM_BASE     0x40300000
+#define TZSRAM_SIZE     (256 * 1024)
+#endif /* CFG_WITH_PAGER */
+
 #define CFG_TEE_CORE_NB_CORE	2
 
 #define UART1_BASE      0x4806A000
@@ -111,6 +116,25 @@
 /* Make stacks aligned to data cache line length */
 #define STACK_ALIGNMENT		64
 
+#ifdef CFG_WITH_PAGER
+/*
+ * Use TZSRAM for TEE, page out everything else to TZDRAM.
+ * +--------+----------+
+ * |  DRAM  |  SHMEM   |
+ * +--------+----------+
+ * |        | TA_RAM   |
+ * | TZDRAM +----------+
+ * |        | PAGE_RAM |
+ * +--------+----------+
+ * | TZSRAM | TEE_RAM  |
+ * +--------+----------+
+ */
+#define CFG_TEE_RAM_VA_SIZE     (1 * 1024 * 1024)
+#define CFG_TEE_RAM_PH_SIZE     TZSRAM_SIZE
+#define CFG_TEE_RAM_START       TZSRAM_BASE
+#define CFG_TEE_LOAD_ADDR       (CFG_TEE_RAM_START + 0x1000)
+
+#else /* CFG_WITH_PAGER */
 /*
  * Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist,
  * everything is in TZDRAM.
@@ -127,6 +151,8 @@
 #define CFG_TEE_RAM_START       TZDRAM_BASE
 #define CFG_TEE_LOAD_ADDR       (CFG_TEE_RAM_START + 0x100)
 
+#endif /* CFG_WITH_PAGER */
+
 #define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
 #define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \