plat-vexpress: add juno flavor

Adds support for ARM Versatile Express V2M-Juno by adding flavor juno.

UART3 (SoC UART1) is used as console uart instead of UART1 (FPGA UART1)
which is used by TSP in ARM Trusted Firmware. UART3 is used for OP-TEE
since that uart is easily accessible on the Juno board, while UART0 and
UART1 only are accessible via headers on the motherboard.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno and FVP)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

core/arch/arm32/include/arm32.h

@@ -49,7 +49,8 @@
 #define CPSR_FIA	(CPSR_F | CPSR_I | CPSR_A)
 
 #define MPIDR_CPU_MASK		0xff
-#define MPIDR_CLUSTER_MASK	(0xff << 8)
+#define MPIDR_CLUSTER_SHIFT	8
+#define MPIDR_CLUSTER_MASK	(0xff << MPIDR_CLUSTER_SHIFT)
 
 #define SCR_NS		(1 << 0)
 #define SCR_IRQ		(1 << 1)

core/arch/arm32/include/arm32_macros.S

@@ -54,6 +54,10 @@
 	mcr	p15, 0, \reg, c3, c0, 0
 	.endm
 
+	.macro read_dfsr reg
+	mrc	p15, 0, \reg, c5, c0, 0
+	.endm
+
 	.macro write_iciallu
 	/* Invalidate all instruction caches to PoU (register ignored) */
 	mcr	p15, 0, r0, c7, c5, 0

core/arch/arm32/kernel/misc.S

@@ -29,6 +29,9 @@
 #include <arm32.h>
 #include <arm32_macros.S>
 
+/* Let platforms override this if needed */
+.weak get_core_pos
+
 FUNC get_core_pos , :
 	read_mpidr r0
 	/* Calculate CorePos = (ClusterId * 4) + CoreId */

core/arch/arm32/plat-vexpress/conf.mk

@@ -3,6 +3,7 @@ CROSS_COMPILE	?= $(CROSS_PREFIX)-
 include mk/gcc.mk
 
 PLATFORM_FLAVOR ?= fvp
+PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) := y
 
 platform-cpuarch = cortex-a15
 platform-cflags	 = -mcpu=$(platform-cpuarch) -mthumb
@@ -27,6 +28,13 @@ platform-cflags += -g
 platform-aflags += -g
 
 ifeq ($(PLATFORM_FLAVOR),fvp)
+platform-flavor-armv8 := 1
+endif
+ifeq ($(PLATFORM_FLAVOR),juno)
+platform-flavor-armv8 := 1
+endif
+
+ifeq ($(platform-flavor-armv8),1)
 # ARM debugger needs this
 platform-cflags += -gdwarf-2
 platform-aflags += -gdwarf-2
@@ -37,11 +45,11 @@ endif
 
 core-platform-subdirs += \
 	$(addprefix $(arch-dir)/, kernel mm tee sta) $(platform-dir)
-ifneq ($(PLATFORM_FLAVOR),fvp)
+ifeq ($(platform-flavor-armv8),1)
+core-platform-cppflags += -DWITH_ARM_TRUSTED_FW=1
+else
 core-platform-subdirs += $(arch-dir)/sm
 core-platform-cppflags += -DWITH_SEC_MON=1
-else
-core-platform-cppflags += -DWITH_ARM_TRUSTED_FW=1
 endif
 
 CFG_PM_DEBUG ?= 0

core/arch/arm32/plat-vexpress/core_bootcfg.c

@@ -220,8 +220,8 @@ static struct map_area bootcfg_stih416_memory[] = {
 
 	{	/* UART */
 	 .type = MEM_AREA_IO_NSEC,
-	 .pa = UART0_BASE & ~SECTION_MASK, .size = SECTION_SIZE,
-	 .device = true, .secure = false, .rw = true,
+	 .pa = CONSOLE_UART_BASE & ~SECTION_MASK, .size = SECTION_SIZE,
+	 .device = true, .secure = true, .rw = true,
 	 },
 
 	{	/* GIC */

core/arch/arm32/plat-vexpress/entry.S

@@ -61,10 +61,10 @@ LOCAL_FUNC reset , :
 
 	mov	r4, lr
 	bl	get_core_pos
-	lsl	r0, #2
 	cmp	r0, #CFG_TEE_CORE_NB_CORE
 	/* Unsupported CPU, park it before it breaks something */
 	bge	unhandled_cpu
+	lsl	r0, #2
 	ldr	r1, =stack_tmp_top
 	ldr	sp, [r1, r0]
 
@@ -80,10 +80,10 @@ LOCAL_FUNC reset , :
 	mov	r0, r4
 	bl	main_init
 
-#if PLATFORM_FLAVOR == PLATFORM_FLAVOR_FVP
+#if defined(WITH_ARM_TRUSTED_FW)
 	/* Pass the vector address returned from main_init */
 	mov     r1, r0
-#elif PLATFORM_FLAVOR == PLATFORM_FLAVOR_QEMU
+#else
 	mov	r1, #0
 	mov	r2, #0
 	mov	r3, #0
@@ -98,7 +98,7 @@ LOCAL_FUNC unhandled_cpu , :
 	b	unhandled_cpu
 END_FUNC unhandled_cpu
 
-#if PLATFORM_FLAVOR == PLATFORM_FLAVOR_FVP
+#if defined(WITH_ARM_TRUSTED_FW)
 FUNC cpu_on_handler , :
 	mov	r4, r0
 	mov	r5, r1
@@ -112,6 +112,9 @@ FUNC cpu_on_handler , :
 
 	mov	r4, lr
 	bl	get_core_pos
+	cmp	r0, #CFG_TEE_CORE_NB_CORE
+	/* Unsupported CPU, park it before it breaks something */
+	bge	unhandled_cpu
 	lsl	r0, #2
 	ldr	r1, =stack_tmp_top
 	ldr	sp, [r1, r0]
@@ -128,6 +131,7 @@ FUNC cpu_on_handler , :
 	mov	r0, r4
 	mov	r1, r5
 	bl	main_cpu_on_handler
+
 	bx	r6
 END_FUNC cpu_on_handler
 #endif

core/arch/arm32/plat-vexpress/juno_core_pos.S

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014, STMicroelectronics International N.V.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <asm.S>
+#include <arm32.h>
+#include <arm32_macros.S>
+
+/* For Juno number the two A57s as 4 to 5 and A53s as 0 to 3 */
+FUNC get_core_pos , :
+	read_mpidr r0
+	/* Calculate CorePos = ((ClusterId ^ 1) * 4) + CoreId */
+	and	r1, r0, #MPIDR_CPU_MASK
+	and	r0, r0, #MPIDR_CLUSTER_MASK
+	eor	r0, r0, #(1 << MPIDR_CLUSTER_SHIFT)
+	add	r0, r1, r0, LSR #6
+	bx	lr
+END_FUNC get_core_pos
+

core/arch/arm32/plat-vexpress/main.c

@@ -233,18 +233,19 @@ static void main_init_sec_mon(size_t pos, uint32_t nsec_entry)
 }
 #endif
 
-#if PLATFORM_FLAVOR_IS(fvp)
+#if PLATFORM_FLAVOR_IS(fvp) || PLATFORM_FLAVOR_IS(juno)
 static void main_init_gic(void)
 {
 	/*
-	 * In FVP, GIC configuration is initialized in ARM-TF,
-	 * Initialize GIC base address here for debugging.
+	 * On ARMv8, GIC configuration is initialized in ARM-TF,
 	 */
 	gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
 	gic_it_add(IT_CONSOLE_UART);
-	gic_it_set_cpu_mask(IT_CONSOLE_UART, 0x1);
+	/* Route FIQ to primary CPU */
+	gic_it_set_cpu_mask(IT_CONSOLE_UART, gic_it_get_target(0));
 	gic_it_set_prio(IT_CONSOLE_UART, 0x1);
 	gic_it_enable(IT_CONSOLE_UART);
+
 }
 #elif PLATFORM_FLAVOR_IS(qemu)
 static void main_init_gic(void)
@@ -266,6 +267,7 @@ static void main_init_gic(void)
 
 static void main_init_helper(bool is_primary, size_t pos, uint32_t nsec_entry)
 {
+
 	/*
 	 * Mask external Abort, IRQ and FIQ before switch to the thread
 	 * vector as the thread handler requires externl Abort, IRQ and FIQ
@@ -280,7 +282,7 @@ static void main_init_helper(bool is_primary, size_t pos, uint32_t nsec_entry)
 		uintptr_t bss_end = (uintptr_t)&__bss_end;
 		size_t n;
 
-		/* Initialize uart with physical address */
+		/* Initialize uart with virtual address */
 		uart_init(CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
 			  CONSOLE_BAUDRATE);
 
@@ -343,16 +345,18 @@ static void main_fiq(void)
 {
 	uint32_t iar;
 
-	DMSG("%s\n", __func__);
+	DMSG("enter");
 
 	iar = gic_read_iar();
 
-	while (uart_have_rx_data(CONSOLE_UART_BASE))
-		DMSG("got 0x%x\n", uart_getchar(CONSOLE_UART_BASE));
+	while (uart_have_rx_data(CONSOLE_UART_BASE)) {
+		DMSG("cpu %zu: got 0x%x",
+		     get_core_pos(), uart_getchar(CONSOLE_UART_BASE));
+	}
 
 	gic_write_eoir(iar);
 
-	DMSG("return from %s\n", __func__);
+	DMSG("return");
 }
 
 #if defined(WITH_ARM_TRUSTED_FW)

core/arch/arm32/plat-vexpress/platform_config.h

@@ -31,6 +31,7 @@
 #define PLATFORM_FLAVOR_ID_fvp		0
 #define PLATFORM_FLAVOR_ID_qemu		1
 #define PLATFORM_FLAVOR_ID_qemu_virt	2
+#define PLATFORM_FLAVOR_ID_juno		3
 #define PLATFORM_FLAVOR_IS(flav) \
 	(PLATFORM_FLAVOR == PLATFORM_FLAVOR_ID_ ## flav)
 
@@ -52,6 +53,32 @@
 #define CONSOLE_UART_BASE	UART1_BASE
 #define IT_CONSOLE_UART		IT_UART1
 
+#elif PLATFORM_FLAVOR_IS(juno)
+
+#define GIC_BASE		0x2c010000
+
+/* FPGA UART0 */
+#define UART0_BASE		0x1c090000
+/* FPGA UART1 */
+#define UART1_BASE		0x1c0a0000
+/* SoC UART0 */
+#define UART2_BASE		0x7ff80000
+/* SoC UART1 */
+#define UART3_BASE		0x7ff70000
+
+
+#define UART0_CLK_IN_HZ		24000000
+#define UART1_CLK_IN_HZ		24000000
+#define UART2_CLK_IN_HZ		7273800
+#define UART3_CLK_IN_HZ		7273800
+
+
+#define IT_UART3		116
+
+#define CONSOLE_UART_BASE	UART3_BASE
+#define IT_CONSOLE_UART		IT_UART3
+#define CONSOLE_UART_CLK_IN_HZ	UART3_CLK_IN_HZ
+
 #elif PLATFORM_FLAVOR_IS(qemu_virt)
 
 #define GIC_BASE		0x08000000
@@ -103,6 +130,48 @@
 #define GICC_OFFSET		0x0
 #define GICD_OFFSET		0x3000000
 
+#elif PLATFORM_FLAVOR_IS(juno)
+
+/*
+ * Juno specifics.
+ */
+
+#define DRAM0_BASE		0x80000000
+#define DRAM0_SIZE		0x7F000000
+
+/*
+ * Last part of DRAM is reserved as secure dram, note that the last 2MiB
+ * of DRAM0 is used by SCP dor DDR retraining.
+ */
+#define TZDRAM_BASE		0xFF000000
+/*
+ * Should be
+ * #define TZDRAM_SIZE		0x00FF8000
+ * but is smaller due to SECTION_SIZE alignment, can be fixed once
+ * OP-TEE OS is mapped using small pages instead.
+ */
+#define TZDRAM_SIZE		0x00E00000
+
+#define CFG_TEE_CORE_NB_CORE	6
+
+#define DDR_PHYS_START		DRAM0_BASE
+#define DDR_SIZE		DRAM0_SIZE
+
+#define CFG_DDR_START		DDR_PHYS_START
+#define CFG_DDR_SIZE		DDR_SIZE
+
+#define CFG_DDR_TEETZ_RESERVED_START	TZDRAM_BASE
+#define CFG_DDR_TEETZ_RESERVED_SIZE	TZDRAM_SIZE
+
+#define TEE_RAM_START		(TZDRAM_BASE)
+#define TEE_RAM_SIZE		0x0010000
+
+#define CFG_SHMEM_START		(DRAM0_BASE + DRAM0_SIZE - CFG_SHMEM_SIZE)
+#define CFG_SHMEM_SIZE		0x100000
+
+#define GICC_OFFSET		0x1f000
+#define GICD_OFFSET		0
+
 #elif PLATFORM_FLAVOR_IS(qemu)
 /*
  * QEMU specifics.

core/arch/arm32/plat-vexpress/sub.mk

@@ -5,3 +5,4 @@ srcs-y += tee_common_otp.c
 srcs-y += core_bootcfg.c
 srcs-y += core_chip.c
 srcs-y += rng_support.c
+srcs-$(PLATFORM_FLAVOR_juno) += juno_core_pos.S