arm: imx: add i.MX7D support

Add i.MX7D support.
 - Add register definition
 - Add gpcv2 to powerup and powerdown cpu
 - Introduce soc runtime detection
 - Add PSCI cpu/off/affinity

The scripts to build 7dsdb image.
make PLATFORM=imx-mx7dsabresd
./mkimage -A arm -O linux -C none -a 0xbdffffe4 -e 0xbe000000
-d out/arm-plat-imx/core/tee.bin uTee-7d

Signed-off-by: Peng Fan <peng.fan@nxp.com>

core/arch/arm/plat-imx/conf.mk

@@ -7,6 +7,7 @@ mx6q-flavorlist = mx6qsabrelite mx6qsabresd
 mx6d-flavorlist =
 mx6dl-flavorlist = mx6dlsabresd
 mx6s-flavorlist =
+mx7-flavorlist = mx7dsabresd
 
 ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
 $(call force,CFG_MX6UL,y)
@@ -20,10 +21,19 @@ else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
 $(call force,CFG_MX6DL,y)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
 $(call force,CFG_MX6S,y)
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7-flavorlist)))
+$(call force,CFG_MX7,y)
 else
 $(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
 endif
 
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
+CFG_DDR_SIZE ?= 0x40000000
+CFG_DT ?= y
+CFG_NS_ENTRY_ADDR ?= 0x80800000
+CFG_PSCI_ARM32 ?= y
+CFG_TEE_CORE_NB_CORE ?= 2
+endif
 
 # Common i.MX6 config
 core_arm32-platform-aflags	+= -mfpu=neon
@@ -60,6 +70,11 @@ CFG_BOOT_SYNC_CPU ?= y
 CFG_BOOT_SECONDARY_REQUEST ?= y
 endif
 
+ifeq ($(filter y, $(CFG_MX7)), y)
+include core/arch/arm/cpu/cortex-a7.mk
 
-ta-targets = ta_arm32
+$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
+CFG_BOOT_SECONDARY_REQUEST ?= y
+endif
 
+ta-targets = ta_arm32

core/arch/arm/plat-imx/config/config_imx7.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CFG_UART_BASE
+#define CFG_UART_BASE	(UART1_BASE)
+#endif
+
+#ifndef CFG_DDR_SIZE
+#error "CFG_DDR_SIZE not defined"
+#endif
+
+#define DRAM0_BASE		0x80000000
+#define DRAM0_SIZE		CFG_DDR_SIZE
+
+/* Location of trusted dram */
+#define TZDRAM_BASE		(DRAM0_BASE + CFG_DDR_SIZE - 32 * 1024 * 1024)
+#define TZDRAM_SIZE		(30 * 1024 * 1024)
+
+/* Full GlobalPlatform test suite requires CFG_SHMEM_SIZE to be at least 2MB */
+#define CFG_SHMEM_START		(TZDRAM_BASE + TZDRAM_SIZE)
+#define CFG_SHMEM_SIZE		0x200000
+
+#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+
+/*
+ * Everything is in TZDRAM.
+ * +------------------+
+ * |        | TEE_RAM |
+ * + TZDRAM +---------+
+ * |        | TA_RAM  |
+ * +--------+---------+
+ */
+#define CFG_TEE_RAM_PH_SIZE     CFG_TEE_RAM_VA_SIZE
+#define CFG_TEE_RAM_START	TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+					CORE_MMU_DEVICE_SIZE)
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+					  CORE_MMU_DEVICE_SIZE)
+
+#ifndef CFG_TEE_LOAD_ADDR
+#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#endif
+
+#define CONSOLE_UART_BASE	(CFG_UART_BASE)

core/arch/arm/plat-imx/gpcv2.c

@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2017 NXP
+ * All rights reserved.
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <imx.h>
+#include <io.h>
+#include <mm/core_memprot.h>
+#include <platform_config.h>
+#include <stdint.h>
+
+static vaddr_t gpc_base(void)
+{
+	return core_mmu_get_va(GPC_BASE, MEM_AREA_IO_SEC);
+}
+
+void imx_gpcv2_set_core_pgc(bool enable, uint32_t offset)
+{
+	uint32_t val = read32(gpc_base() + offset) & (~GPC_PGC_PCG_MASK);
+
+	if (enable)
+		val |= GPC_PGC_PCG_MASK;
+
+	write32(val, gpc_base() + offset);
+}
+
+void imx_gpcv2_set_core1_pdn_by_software(void)
+{
+	uint32_t val = read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ);
+
+	imx_gpcv2_set_core_pgc(true, GPC_PGC_C1);
+
+	val |= GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK;
+
+	write32(val, gpc_base() + GPC_CPU_PGC_SW_PDN_REQ);
+
+	while ((read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ) &
+	       GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK) != 0)
+		;
+
+	imx_gpcv2_set_core_pgc(false, GPC_PGC_C1);
+}
+
+void imx_gpcv2_set_core1_pup_by_software(void)
+{
+	uint32_t val = read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ);
+
+	imx_gpcv2_set_core_pgc(true, GPC_PGC_C1);
+
+	val |= GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK;
+
+	write32(val, gpc_base() + GPC_CPU_PGC_SW_PUP_REQ);
+
+	while ((read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ) &
+	       GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK) != 0)
+		;
+
+	imx_gpcv2_set_core_pgc(false, GPC_PGC_C1);
+}

core/arch/arm/plat-imx/imx-common.c

@@ -35,16 +35,111 @@
 #include <mm/core_memprot.h>
 #include <platform_config.h>
 
+static uint32_t imx_digproc(void)
+{
+	static uint32_t reg;
+	vaddr_t anatop_addr;
+
+	if (!reg) {
+		anatop_addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC);
+
+		/* TODO: Handle SL here */
+#ifdef CFG_MX7
+		reg = read32(anatop_addr + OFFSET_DIGPROG_IMX7D);
+#else
+		reg = read32(anatop_addr + OFFSET_DIGPROG);
+#endif
+	}
+
+	return reg;
+}
+
+static uint32_t imx_soc_rev_major(void)
+{
+	return ((imx_digproc() & 0xff00) >> 8) + 1;
+}
+
+uint32_t imx_soc_type(void)
+{
+	return (imx_digproc() >> 16) & 0xff;
+}
+
+bool soc_is_imx6ul(void)
+{
+	return imx_soc_type() == SOC_MX6UL;
+}
+
+bool soc_is_imx6ull(void)
+{
+	return imx_soc_type() == SOC_MX6ULL;
+}
+
+bool soc_is_imx6sdl(void)
+{
+	return imx_soc_type() == SOC_MX6DL;
+}
+
+bool soc_is_imx6dq(void)
+{
+	return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 1);
+}
+
+bool soc_is_imx6dqp(void)
+{
+	return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 2);
+}
+
+bool soc_is_imx7s(void)
+{
+	vaddr_t addr = core_mmu_get_va(OCOTP_BASE + 0x450, MEM_AREA_IO_SEC);
+	uint32_t val = read32(addr);
+
+	if (soc_is_imx7ds()) {
+		if (val & 1)
+			return true;
+		else
+			return false;
+	}
+
+	return false;
+}
+
+bool soc_is_imx7d(void)
+{
+	vaddr_t addr = core_mmu_get_va(OCOTP_BASE + 0x450, MEM_AREA_IO_SEC);
+	uint32_t val = read32(addr);
+
+	if (soc_is_imx7ds()) {
+		if (val & 1)
+			return false;
+		else
+			return true;
+	}
+
+	return false;
+}
+
+bool soc_is_imx7ds(void)
+{
+	return imx_soc_type() == SOC_MX7D;
+}
+
 uint32_t imx_get_src_gpr(int cpu)
 {
 	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
 
-	return read32(va + SRC_GPR1 + cpu * 8 + 4);
+	if (soc_is_imx7d())
+		return read32(va + SRC_GPR1_MX7 + cpu * 8 + 4);
+	else
+		return read32(va + SRC_GPR1 + cpu * 8 + 4);
 }
 
 void imx_set_src_gpr(int cpu, uint32_t val)
 {
 	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
 
-	write32(val, va + SRC_GPR1 + cpu * 8 + 4);
+	if (soc_is_imx7d())
+		write32(val, va + SRC_GPR1_MX7 + cpu * 8 + 4);
+	else
+		write32(val, va + SRC_GPR1 + cpu * 8 + 4);
 }