Add i.MX PSCI CPU off and update i.MX6UL

.travis.yml

@@ -187,6 +187,9 @@ script:
   # i.MX6UL 14X14 EVK
   - $make PLATFORM=imx-mx6ulevk ARCH=arm CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0x80800000 CFG_DT_ADDR=0x83000000 CFG_DT=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4
 
+  # i.MX6ULL 14X14 EVK
+  - $make PLATFORM=imx-mx6ullevk ARCH=arm CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0x80800000 CFG_DT=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4
+
   # i.MX6Quad SABRE
   - $make PLATFORM=imx-mx6qsabrelite
   - $make PLATFORM=imx-mx6qsabresd

MAINTAINERS.md

@@ -13,6 +13,7 @@ for these platforms.
 | FSL i.MX6 Quad SABRE Lite Board	|`Yan Yan <yan.yan@windriver.com>`,`Feng Yu <Yu.Feng@windriver.com>`|
 | FSL i.MX6 Quad SABRE SD Board		|`Yan Yan <yan.yan@windriver.com>`,`Feng Yu <Yu.Feng@windriver.com>`|
 | FSL i.MX6 UltraLite EVK Board		|`Peng Fan <peng.fan@nxp.com>`|
+| NXP i.MX6 ULL EVK Board		|`Peng Fan <peng.fan@nxp.com>`|
 | ARM Foundation FVP			|`Linaro <op-tee@linaro.org>`|
 | HiKey Board (HiSilicon Kirin 620)	|`Linaro <op-tee@linaro.org>`|
 | HiSilicon D02				|`Linaro <op-tee@linaro.org>`|

core/arch/arm/include/arm32.h

@@ -658,6 +658,11 @@ static inline uint64_t read_pmu_ccnt(void)
 	asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(val));
 	return val;
 }
+
+static inline void wfi(void)
+{
+	asm volatile("wfi");
+}
 #endif /*ASM*/
 
 #endif /*ARM32_H*/

core/arch/arm/include/sm/psci.h

@@ -58,3 +58,5 @@ int psci_node_hw_state(uint32_t cpu_id, uint32_t power_level);
 int psci_stat_residency(uint32_t cpu_id, uint32_t power_state);
 int psci_stat_count(uint32_t cpu_id, uint32_t power_state);
 void tee_psci_handler(struct thread_smc_args *args);
+
+void psci_armv7_cpu_off(void);

core/arch/arm/plat-imx/imx6ul-regs.h → core/arch/arm/plat-imx/a7_plat_init.S

@@ -1,9 +1,9 @@
 /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- * All rights reserved.
- * Copyright (c) 2016, Wind River Systems.
+ * Copyright (c) 2017, NXP
  * All rights reserved.
  *
+ * Peng Fan  <peng.fan@nxp.com>
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *
@@ -27,31 +27,40 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#define GIC_BASE			0xA00000
-#define GIC_SIZE			0x8000
-#define GICC_OFFSET			0x2000
-#define GICD_OFFSET			0x1000
-#define UART0_BASE			0x2020000
-#define UART1_BASE			0x21E8000
-#define UART2_BASE			0x21EC000
+/*
+ * Entry points for the A7 init.
+ * It is assume no stack is available when these routines are called.
+ * It is assume each routine is called with return address in LR
+ * and with ARM registers R0, R1, R2, R3 being scratchable.
+ */
+
+#include <arm32.h>
+#include <arm32_macros.S>
+#include <asm.S>
+#include <kernel/unwind.h>
+#include <platform_config.h>
 
-#define AHB1_BASE			0x02000000
-#define AHB1_SIZE			0x100000
-#define AHB2_BASE			0x02100000
-#define AHB2_SIZE			0x100000
-#define AHB3_BASE			0x02200000
-#define AHB3_SIZE			0x100000
+.section .text
+.balign 4
+.code 32
 
-#define AIPS_TZ1_BASE_ADDR		0x02000000
-#define AIPS1_OFF_BASE_ADDR		(AIPS_TZ1_BASE_ADDR + 0x80000)
+/*
+ * Cortex A7 configuration early configuration
+ *
+ * Use scratables registers R0-R3.
+ * No stack usage.
+ * LR store return address.
+ * Trap CPU in case of error.
+ */
+FUNC plat_cpu_reset_early , :
+UNWIND(	.fnstart)
 
-#define DRAM0_BASE			0x80000000
-#define DRAM0_SIZE			0x20000000
+	mov_imm r0, 0x00000040
+	write_actlr r0
 
-/* Central Security Unit register values */
-#define CSU_BASE			0x021C0000
-#define CSU_CSL_START			0x0
-#define CSU_CSL_END			0xA0
-#define CSU_ACCESS_ALL			0x00FF00FF
-#define CSU_SETTING_LOCK		0x01000100
+	mov_imm r0, 0x00040C00
+	write_nsacr r0
 
+	bx	lr
+UNWIND(	.fnend)
+END_FUNC plat_cpu_reset_early

core/arch/arm/plat-imx/conf.mk

@@ -2,13 +2,16 @@ PLATFORM_FLAVOR ?= mx6ulevk
 
 # Get SoC associated with the PLATFORM_FLAVOR
 mx6ul-flavorlist = mx6ulevk
+mx6ull-flavorlist = mx6ullevk
 mx6q-flavorlist = mx6qsabrelite mx6qsabresd
 mx6d-flavorlist =
 mx6dl-flavorlist = mx6dlsabresd
 mx6s-flavorlist =
 
 ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
 $(call force,CFG_MX6UL,y)
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
+$(call force,CFG_MX6ULL,y)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
 $(call force,CFG_MX6Q,y)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
@@ -35,18 +38,20 @@ CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
 CFG_WITH_STACK_CANARIES ?= y
 
 
-# i.MX6UL specific config
-ifeq ($(CFG_MX6UL),y)
+# i.MX6UL/ULL specific config
+ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL)))
 include core/arch/arm/cpu/cortex-a7.mk
 
-$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+$(call force,CFG_MX6,y)
+$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
 endif
 
 
 # i.MX6 Solo/DualLite/Dual/Quad specific config
 ifeq ($(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
 include core/arch/arm/cpu/cortex-a9.mk
 
+$(call force,CFG_MX6,y)
 $(call force,CFG_PL310,y)
 $(call force,CFG_PL310_LOCKED,y)
 $(call force,CFG_SECURE_TIME_SOURCE_REE,y)

core/arch/arm/plat-imx/imx-common.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <console.h>
+#include <io.h>
+#include <imx.h>
+#include <mm/core_mmu.h>
+#include <mm/core_memprot.h>
+#include <platform_config.h>
+
+uint32_t imx_get_src_gpr(int cpu)
+{
+	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
+
+	return read32(va + SRC_GPR1 + cpu * 8 + 4);
+}
+
+void imx_set_src_gpr(int cpu, uint32_t val)
+{
+	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
+
+	write32(val, va + SRC_GPR1 + cpu * 8 + 4);
+}

core/arch/arm/plat-imx/imx-regs.h

@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * All rights reserved.
+ * Copyright (c) 2016, Wind River Systems.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef PLAT_IMX_IMX_REGS_H
+#define PLAT_IMX_IMX_REGS_H
+
+#ifdef CFG_MX6
+#define UART1_BASE			0x2020000
+#define IOMUXC_BASE			0x020E0000
+#define IOMUXC_SIZE			0x4000
+#define IOMUXC_GPR_BASE			0x020E4000
+#define SRC_BASE			0x020D8000
+#define SRC_SIZE			0x4000
+#define CCM_BASE			0x020C4000
+#define CCM_SIZE			0x4000
+#define ANATOP_BASE			0x020C8000
+#define ANATOP_SIZE			0x1000
+#define SNVS_BASE			0x020CC000
+#define GPC_BASE			0x020DC000
+#define GPC_SIZE			0x4000
+#define WDOG_BASE			0x020BC000
+#define SEMA4_BASE			0x02290000
+#define SEMA4_SIZE			0x4000
+#define MMDC_P0_BASE			0x021B0000
+#define MMDC_P0_SIZE			0x4000
+#define MMDC_P1_BASE			0x021B4000
+#define MMDC_P1_SIZE			0x4000
+#define TZASC_BASE			0x21D0000
+#define TZASC2_BASE			0x21D4000
+#define UART2_BASE			0x021E8000
+#define UART3_BASE			0x021EC000
+#define UART4_BASE			0x021F0000
+#define UART5_BASE			0x021F4000
+#define AIPS1_BASE			0x02000000
+#define AIPS1_SIZE			0x100000
+#define AIPS2_BASE			0x02100000
+#define AIPS2_SIZE			0x100000
+#define AIPS3_BASE			0x02200000
+#define AIPS3_SIZE			0x100000
+
+#define SCU_BASE			0x00A00000
+#define PL310_BASE			0x00A02000
+#define SRC_BASE			0x020D8000
+#define IRAM_BASE			0x00900000
+
+#define OCOTP_BASE			0x021BC000
+
+#define GIC_BASE			0x00A00000
+#define GICD_OFFSET			0x1000
+
+#if defined(CFG_MX6UL) || defined(CFG_MX6ULL)
+#define GICC_OFFSET			0x2000
+/* No CAAM on i.MX6ULL */
+#define CAAM_BASE			0x02140000
+#else
+#define GICC_OFFSET			0x100
+#define CAAM_BASE			0x02100000
+#endif
+
+#define GIC_CPU_BASE			(GIC_BASE + GICC_OFFSET)
+#define GIC_DIST_BASE			(GIC_BASE + GICD_OFFSET)
+
+/* Central Security Unit register values */
+#define CSU_BASE			0x021C0000
+#define CSU_CSL_START			0x0
+#define CSU_CSL_END			0xA0
+#define CSU_CSL5			0x14
+#define CSU_CSL15			0x3C
+#define CSU_CSL16			0x40
+#define	CSU_ACCESS_ALL			0x00FF00FF
+#define CSU_SETTING_LOCK		0x01000100
+
+/* Used in suspend/resume and low power idle */
+#define MX6Q_SRC_GPR1			0x20
+#define MX6Q_SRC_GPR2			0x24
+#define MX6Q_MMDC_MISC			0x18
+#define MX6Q_MMDC_MAPSR			0x404
+#define MX6Q_MMDC_MPDGCTRL0		0x83c
+#define MX6Q_GPC_IMR1			0x08
+#define MX6Q_GPC_IMR2			0x0c
+#define MX6Q_GPC_IMR3			0x10
+#define MX6Q_GPC_IMR4			0x14
+#define MX6Q_CCM_CCR			0x0
+#define MX6Q_ANATOP_CORE		0x140
+
+#define IOMUXC_GPR9_OFFSET		0x24
+#define IOMUXC_GPR10_OFFSET		0x28
+
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET	5
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK		GENMASK_32(10, 5)
+
+#define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET		4
+#define IOMUXC_GPR10_OCRAM_TZ_EN_MASK		GENMASK_32(4, 4)
+
+#define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET	20
+#define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK	GENMASK_32(20, 20)
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET	21
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK	GENMASK_32(26, 21)
+
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET_6UL	11
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK_6UL	GENMASK_32(15, 11)
+#define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET_6UL	10
+#define IOMUXC_GPR10_OCRAM_TZ_EN_MASK_6UL	GENMASK_32(10, 10)
+
+#define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET_6UL	26
+#define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK_6UL		GENMASK_32(26, 26)
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET_6UL	(27)
+#define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK_6UL	GENMASK_32(31, 27)
+
+/* Central Security Unit register values */
+#define CSU_BASE			0x021C0000
+#define CSU_CSL_START			0x0
+#define CSU_CSL_END			0xA0
+#define CSU_CSL5			0x14
+#define CSU_CSL16			0x40
+#define CSU_ACCESS_ALL			0x00FF00FF
+#define CSU_SETTING_LOCK		0x01000100
+
+#if defined(CFG_MX6UL) || defined(CFG_MX6ULL)
+#define DRAM0_BASE			0x80000000
+#else
+#define DRAM0_BASE			0x10000000
+#endif
+
+#define SRC_SCR				0x000
+#define SRC_GPR1			0x020
+#define SRC_SCR_CPU_ENABLE_ALL		SHIFT_U32(0x7, 22)
+#define SRC_SCR_CORE1_RST_OFFSET	14
+#define SRC_SCR_CORE1_ENABLE_OFFSET	22
+#else
+#error "CFG_MX6 not defined"
+#endif
+
+#define IOMUXC_GPR4_OFFSET	0x10
+#define IOMUXC_GPR5_OFFSET	0x14
+#define ARM_WFI_STAT_MASK(n)	BIT(n)
+
+#endif